From patchwork Wed Sep 18 16:06:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 11150809 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4572A14DB for ; Wed, 18 Sep 2019 17:12:34 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D65A620665 for ; Wed, 18 Sep 2019 17:12:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D65A620665 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kaod.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:33164 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAdVH-0000cg-V7 for patchwork-qemu-devel@patchwork.kernel.org; Wed, 18 Sep 2019 13:12:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55568) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iAcUT-0003bG-RO for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iAcUS-0002x0-6T for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:37 -0400 Received: from 3.mo7.mail-out.ovh.net ([46.105.34.113]:53205) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iAcUS-0002vy-0C for qemu-devel@nongnu.org; Wed, 18 Sep 2019 12:07:36 -0400 Received: from player799.ha.ovh.net (unknown [10.108.54.72]) by mo7.mail-out.ovh.net (Postfix) with ESMTP id AD0CC13378F for ; Wed, 18 Sep 2019 18:07:34 +0200 (CEST) Received: from kaod.org (lfbn-1-2240-157.w90-76.abo.wanadoo.fr [90.76.60.157]) (Authenticated sender: clg@kaod.org) by player799.ha.ovh.net (Postfix) with ESMTPSA id 3F6E69F0E598; Wed, 18 Sep 2019 16:07:29 +0000 (UTC) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: David Gibson Date: Wed, 18 Sep 2019 18:06:27 +0200 Message-Id: <20190918160645.25126-8-clg@kaod.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918160645.25126-1-clg@kaod.org> References: <20190918160645.25126-1-clg@kaod.org> MIME-Version: 1.0 X-Ovh-Tracer-Id: 6216656339133041638 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgedufedrudekgdeliecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemucehtddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 46.105.34.113 Subject: [Qemu-devel] [PATCH v4 07/25] ppc/spapr: Implement the XiveFabric interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?C=C3=A9dric_Le_Goater?= , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The CAM line matching sequence in the pseries machine does not change much apart from the use of the new QOM interfaces. There is an extra indirection because of the sPAPR IRQ backend of the machine. Only the XIVE backend implements the new 'match_nvt' handler. Signed-off-by: Cédric Le Goater --- include/hw/ppc/spapr_irq.h | 6 ++++++ hw/ppc/spapr.c | 34 ++++++++++++++++++++++++++++++++++ hw/ppc/spapr_irq.c | 25 +++++++++++++++++++++++++ 3 files changed, 65 insertions(+) diff --git a/include/hw/ppc/spapr_irq.h b/include/hw/ppc/spapr_irq.h index 5db305165ce2..859780efaf95 100644 --- a/include/hw/ppc/spapr_irq.h +++ b/include/hw/ppc/spapr_irq.h @@ -31,6 +31,8 @@ int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align, Error **errp); void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num); +struct XiveTCTXMatch; + typedef struct SpaprIrq { uint32_t nr_irqs; uint32_t nr_msis; @@ -50,6 +52,10 @@ typedef struct SpaprIrq { void (*set_irq)(void *opaque, int srcno, int val); const char *(*get_nodename)(SpaprMachineState *spapr); void (*init_kvm)(SpaprMachineState *spapr, Error **errp); + int (*match_nvt)(SpaprMachineState *spapr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, struct XiveTCTXMatch *match); } SpaprIrq; extern SpaprIrq spapr_irq_xics; diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 2725b139a7f0..90f6f5fb9536 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -4360,6 +4360,37 @@ static void spapr_pic_print_info(InterruptStatsProvider *obj, kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); } +static int spapr_xive_match_nvt(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) +{ + SpaprMachineState *spapr = SPAPR_MACHINE(xfb); + int count; + + count = spapr->irq->match_nvt(spapr, format, nvt_blk, nvt_idx, cam_ignore, + priority, logic_serv, match); + if (count < 0) { + return count; + } + + /* + * When we implement the save and restore of the thread interrupt + * contexts in the enter/exit CPU handlers of the machine and the + * escalations in QEMU, we should be able to handle non dispatched + * vCPUs. + * + * Until this is done, the sPAPR machine should find at least one + * matching context always. + */ + if (count == 0) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", + nvt_blk, nvt_idx); + } + + return count; +} + int spapr_get_vcpu_id(PowerPCCPU *cpu) { return cpu->vcpu_id; @@ -4456,6 +4487,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); + XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); mc->desc = "pSeries Logical Partition (PAPR compliant)"; mc->ignore_boot_device_suffixes = true; @@ -4514,6 +4546,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) */ mc->numa_mem_align_shift = 28; mc->numa_mem_supported = true; + xfc->match_nvt = spapr_xive_match_nvt; smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; @@ -4547,6 +4580,7 @@ static const TypeInfo spapr_machine_info = { { TYPE_PPC_VIRTUAL_HYPERVISOR }, { TYPE_XICS_FABRIC }, { TYPE_INTERRUPT_STATS_PROVIDER }, + { TYPE_XIVE_FABRIC }, { } }, }; diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index d8f46b6797f8..8a6d79a59af2 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -257,6 +257,7 @@ SpaprIrq spapr_irq_xics = { .set_irq = spapr_irq_set_irq_xics, .get_nodename = spapr_irq_get_nodename_xics, .init_kvm = spapr_irq_init_kvm_xics, + .match_nvt = NULL, /* should not be used */ }; /* @@ -406,6 +407,18 @@ static void spapr_irq_init_kvm_xive(SpaprMachineState *spapr, Error **errp) } } +static int spapr_irq_match_nvt_xive(SpaprMachineState *spapr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) +{ + XivePresenter *xptr = XIVE_PRESENTER(spapr->xive); + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); + + return xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, + priority, logic_serv, match); +} + /* * XIVE uses the full IRQ number space. Set it to 8K to be compatible * with XICS. @@ -431,6 +444,7 @@ SpaprIrq spapr_irq_xive = { .set_irq = spapr_irq_set_irq_xive, .get_nodename = spapr_irq_get_nodename_xive, .init_kvm = spapr_irq_init_kvm_xive, + .match_nvt = spapr_irq_match_nvt_xive, }; /* @@ -585,6 +599,15 @@ static const char *spapr_irq_get_nodename_dual(SpaprMachineState *spapr) return spapr_irq_current(spapr)->get_nodename(spapr); } +static int spapr_irq_match_nvt_dual(SpaprMachineState *spapr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) +{ + return spapr_irq_current(spapr)->match_nvt(spapr, format, nvt_blk, nvt_idx, + cam_ignore, priority, logic_serv, match); +} + /* * Define values in sync with the XIVE and XICS backend */ @@ -608,6 +631,7 @@ SpaprIrq spapr_irq_dual = { .set_irq = spapr_irq_set_irq_dual, .get_nodename = spapr_irq_get_nodename_dual, .init_kvm = NULL, /* should not be used */ + .match_nvt = spapr_irq_match_nvt_dual, }; @@ -825,4 +849,5 @@ SpaprIrq spapr_irq_xics_legacy = { .set_irq = spapr_irq_set_irq_xics, .get_nodename = spapr_irq_get_nodename_xics, .init_kvm = spapr_irq_init_kvm_xics, + .match_nvt = NULL, /* should not be used */ };