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[97.113.7.119]) by smtp.gmail.com with ESMTPSA id 193sm4179986pfc.59.2019.09.20.21.33.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Sep 2019 21:33:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 6/7] target/alpha: Mask IOV exception with INV for user-only Date: Fri, 20 Sep 2019 21:32:55 -0700 Message-Id: <20190921043256.4575-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190921043256.4575-1-richard.henderson@linaro.org> References: <20190921043256.4575-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The kernel masks the integer overflow exception with the software invalid exception mask. Include IOV in the set of exception bits masked by fpcr_exc_enable. Fixes the new float_convs test. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée Tested-by: Alex Bennée --- target/alpha/helper.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 1b3479738b..55d7274d94 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -58,6 +58,13 @@ void cpu_alpha_store_fpcr(CPUAlphaState *env, uint64_t val) */ uint32_t soft_fpcr = alpha_ieee_swcr_to_fpcr(env->swcr) >> 32; fpcr |= soft_fpcr & (FPCR_STATUS_MASK | FPCR_DNZ); + + /* + * The IOV exception is disabled by the kernel with SWCR_TRAP_ENABLE_INV, + * which got mapped by alpha_ieee_swcr_to_fpcr to FPCR_INVD. + * Add FPCR_IOV to fpcr_exc_enable so that it is handled identically. + */ + t |= CONVERT_BIT(soft_fpcr, FPCR_INVD, FPCR_IOV); #endif t |= CONVERT_BIT(fpcr, FPCR_INED, FPCR_INE);