target/xtensa: regenerate and re-import test_mmuhifi_c3 core

Commit Message

Max Filippov Oct. 9, 2019, 2:57 a.m. UTC

Overlay part of the test_mmuhifi_c3 core has GPL3 copyright headers in
it. Fix that by regenerating test_mmuhifi_c3 core overlay and
re-importing it.

Fixes: d848ea776728 ("target/xtensa: add test_mmuhifi_c3 core")
Reported-by: Thomas Huth <[e-mail]>
Signed-off-by: Max Filippov <[e-mail]>
---
 target/xtensa/core-test_mmuhifi_c3.c          |    3 +-
 target/xtensa/core-test_mmuhifi_c3/core-isa.h |  116 +-
 .../core-test_mmuhifi_c3/gdb-config.inc.c     |  114 +-
 .../core-test_mmuhifi_c3/xtensa-modules.inc.c | 6384 ++++++++---------
 4 files changed, 3385 insertions(+), 3232 deletions(-)

Comments

Thomas Huth Oct. 9, 2019, 8:47 a.m. UTC | #1

On 09/10/2019 04.57, Max Filippov wrote:
> Overlay part of the test_mmuhifi_c3 core has GPL3 copyright headers in
> it. Fix that by regenerating test_mmuhifi_c3 core overlay and
> re-importing it.
> 
> Fixes: d848ea776728 ("target/xtensa: add test_mmuhifi_c3 core")
> Reported-by: Thomas Huth <[e-mail]>
> Signed-off-by: Max Filippov <[e-mail]>
> ---
>  target/xtensa/core-test_mmuhifi_c3.c          |    3 +-
>  target/xtensa/core-test_mmuhifi_c3/core-isa.h |  116 +-
>  .../core-test_mmuhifi_c3/gdb-config.inc.c     |  114 +-
>  .../core-test_mmuhifi_c3/xtensa-modules.inc.c | 6384 ++++++++---------
>  4 files changed, 3385 insertions(+), 3232 deletions(-)

FWIW,
Acked-by: Thomas Huth <[e-mail]>

Thanks for the quick update! I think we should include the patch also in
future stable releases if necessary, so I've added qemu-stable to CC: now.

 Thomas

[e-mail] Oct. 9, 2019, 5:06 p.m. UTC | #2

Patchew URL: https://patchew.org/QEMU/[e-mail]/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH] target/xtensa: regenerate and re-import test_mmuhifi_c3 core
Type: series
Message-id: [e-mail]

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Switched to a new branch 'test'
b98c824 target/xtensa: regenerate and re-import test_mmuhifi_c3 core

=== OUTPUT BEGIN ===
ERROR: code indent should never use tabs
#46: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:3:
+ *^I^I^I^Iprocessor CORE configuration$

WARNING: Block comments use a leading /* on a separate line
#55: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:8:
+/* Xtensa processor core configuration information.

WARNING: Block comments use * on subsequent lines
#56: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:9:
+/* Xtensa processor core configuration information.
+

WARNING: Block comments use a trailing */ on a separate line
#76: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:29:
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */

WARNING: line over 80 characters
#89: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:57:
+#define XCHAL_LOOP_BUFFER_SIZE         0       /* zero-ov. loop instr buffer size */

ERROR: code indent should never use tabs
#89: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:57:
+#define XCHAL_LOOP_BUFFER_SIZE^I^I0^I/* zero-ov. loop instr buffer size */$

WARNING: line over 80 characters
#97: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:85:
+#define XCHAL_HAVE_MX                  1       /* MX core (Tensilica internal) */

ERROR: code indent should never use tabs
#97: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:85:
+#define XCHAL_HAVE_MX^I^I^I1^I/* MX core (Tensilica internal) */$

ERROR: code indent should never use tabs
#100: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:88:
+#define XCHAL_HAVE_PSO^I^I^I0^I/* Power Shut-Off */$

ERROR: code indent should never use tabs
#101: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:89:
+#define XCHAL_HAVE_PSO_CDM^I^I0^I/* core/debug/mem pwr domains */$

ERROR: code indent should never use tabs
#102: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:90:
+#define XCHAL_HAVE_PSO_FULL_RETENTION^I0^I/* all regs preserved on PSO */$

ERROR: code indent should never use tabs
#110: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:97:
+#define XCHAL_HAVE_FP^I^I^I0^I/* single prec floating point */$

ERROR: code indent should never use tabs
#111: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:98:
+#define XCHAL_HAVE_FP_DIV^I^I0^I/* FP with DIV instructions */$

ERROR: code indent should never use tabs
#112: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:99:
+#define XCHAL_HAVE_FP_RECIP^I^I0^I/* FP with RECIP instructions */$

ERROR: code indent should never use tabs
#113: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:100:
+#define XCHAL_HAVE_FP_SQRT^I^I0^I/* FP with SQRT instructions */$

ERROR: code indent should never use tabs
#114: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:101:
+#define XCHAL_HAVE_FP_RSQRT^I^I0^I/* FP with RSQRT instructions */$

ERROR: code indent should never use tabs
#116: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:103:
+#define XCHAL_HAVE_DFP_DIV^I^I0^I/* DFP with DIV instructions */$

ERROR: code indent should never use tabs
#117: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:104:
+#define XCHAL_HAVE_DFP_RECIP^I^I0^I/* DFP with RECIP instructions*/$

ERROR: code indent should never use tabs
#118: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:105:
+#define XCHAL_HAVE_DFP_SQRT^I^I0^I/* DFP with SQRT instructions */$

ERROR: code indent should never use tabs
#119: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:106:
+#define XCHAL_HAVE_DFP_RSQRT^I^I0^I/* DFP with RSQRT instructions*/$

ERROR: code indent should never use tabs
#124: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:111:
+#define XCHAL_HAVE_HIFI3^I^I0^I/* HiFi3 Audio Engine pkg */$

ERROR: code indent should never use tabs
#126: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:113:
+#define XCHAL_HAVE_HIFI2EP^I^I0^I/* HiFi2EP */$

ERROR: trailing whitespace
#127: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:114:
+#define XCHAL_HAVE_HIFI_MINI^I^I0^I$

ERROR: code indent should never use tabs
#127: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:114:
+#define XCHAL_HAVE_HIFI_MINI^I^I0^I$

ERROR: code indent should never use tabs
#129: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:116:
+#define XCHAL_HAVE_BBE16^I^I0^I/* ConnX BBE16 pkg */$

ERROR: code indent should never use tabs
#130: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:117:
+#define XCHAL_HAVE_BBE16_RSQRT^I^I0^I/* BBE16 & vector recip sqrt */$

ERROR: code indent should never use tabs
#131: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:118:
+#define XCHAL_HAVE_BBE16_VECDIV^I^I0^I/* BBE16 & vector divide */$

ERROR: code indent should never use tabs
#132: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:119:
+#define XCHAL_HAVE_BBE16_DESPREAD^I0^I/* BBE16 & despread */$

ERROR: code indent should never use tabs
#133: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:120:
+#define XCHAL_HAVE_BBENEP^I^I0^I/* ConnX BBENEP pkgs */$

ERROR: code indent should never use tabs
#134: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:121:
+#define XCHAL_HAVE_BSP3^I^I^I0^I/* ConnX BSP3 pkg */$

ERROR: code indent should never use tabs
#135: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:122:
+#define XCHAL_HAVE_BSP3_TRANSPOSE^I0^I/* BSP3 & transpose32x32 */$

ERROR: code indent should never use tabs
#136: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:123:
+#define XCHAL_HAVE_SSP16^I^I0^I/* ConnX SSP16 pkg */$

ERROR: code indent should never use tabs
#137: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:124:
+#define XCHAL_HAVE_SSP16_VITERBI^I0^I/* SSP16 & viterbi */$

ERROR: code indent should never use tabs
#138: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:125:
+#define XCHAL_HAVE_TURBO16^I^I0^I/* ConnX Turbo16 pkg */$

ERROR: code indent should never use tabs
#139: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:126:
+#define XCHAL_HAVE_BBP16^I^I0^I/* ConnX BBP16 pkg */$

ERROR: code indent should never use tabs
#140: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:127:
+#define XCHAL_HAVE_FLIX3^I^I0^I/* basic 3-way FLIX option */$

ERROR: code indent should never use tabs
#147: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:134:
+#define XCHAL_NUM_LOADSTORE_UNITS^I1^I/* load/store units */$

ERROR: code indent should never use tabs
#151: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:138:
+#define XCHAL_DATA_PIPE_DELAY^I^I1^I/* d-side pipeline delay$

WARNING: Block comments use a leading /* on a separate line
#151: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:138:
+#define XCHAL_DATA_PIPE_DELAY          1       /* d-side pipeline delay

ERROR: code indent should never use tabs
#152: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:139:
+^I^I^I^I^I^I   (1 = 5-stage, 2 = 7-stage) */$

WARNING: Block comments use * on subsequent lines
#152: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:139:
+#define XCHAL_DATA_PIPE_DELAY          1       /* d-side pipeline delay
+                                                  (1 = 5-stage, 2 = 7-stage) */

WARNING: Block comments use a trailing */ on a separate line
#152: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:139:
+                                                  (1 = 5-stage, 2 = 7-stage) */

ERROR: code indent should never use tabs
#160: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:146:
+#define XCHAL_SW_VERSION^I^I1000006^I/* sw version of this header */$

ERROR: code indent should never use tabs
#174: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:191:
+#define XCHAL_HAVE_PREFETCH^I^I0^I/* PREFCTL register */$

ERROR: code indent should never use tabs
#175: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:192:
+#define XCHAL_HAVE_PREFETCH_L1^I^I0^I/* prefetch to L1 dcache */$

ERROR: code indent should never use tabs
#176: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:193:
+#define XCHAL_PREFETCH_CASTOUT_LINES^I0^I/* dcache pref. castout bufsz */$

ERROR: code indent should never use tabs
#185: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:231:
+#define XCHAL_DCACHE_BANKS^I^I1^I/* number of banks */$

ERROR: code indent should never use tabs
#194: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:248:
+#define XCHAL_HAVE_IMEM_LOADSTORE^I1^I/* can load/store to IROM/IRAM*/$

ERROR: code indent should never use tabs
#203: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:324:
+#define XCHAL_INTTYPE_MASK_PROFILING^I0x00000000$

ERROR: code indent should never use tabs
#230: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:356:
+#define XCHAL_INT0_EXTNUM^I^I0^I/* (intlevel 1) */$

ERROR: code indent should never use tabs
#231: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:357:
+#define XCHAL_INT1_EXTNUM^I^I1^I/* (intlevel 1) */$

ERROR: code indent should never use tabs
#232: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:358:
+#define XCHAL_INT2_EXTNUM^I^I2^I/* (intlevel 1) */$

ERROR: code indent should never use tabs
#233: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:359:
+#define XCHAL_INT3_EXTNUM^I^I3^I/* (intlevel 1) */$

ERROR: code indent should never use tabs
#234: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:360:
+#define XCHAL_INT4_EXTNUM^I^I4^I/* (intlevel 1) */$

ERROR: code indent should never use tabs
#235: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:361:
+#define XCHAL_INT5_EXTNUM^I^I5^I/* (intlevel 1) */$

ERROR: code indent should never use tabs
#236: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:362:
+#define XCHAL_INT9_EXTNUM^I^I6^I/* (intlevel 1) */$

ERROR: code indent should never use tabs
#237: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:363:
+#define XCHAL_INT10_EXTNUM^I^I7^I/* (intlevel 1) */$

ERROR: code indent should never use tabs
#238: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:364:
+#define XCHAL_INT11_EXTNUM^I^I8^I/* (intlevel 1) */$

WARNING: line over 80 characters
#247: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:374:
+                                                          0 == XEAX (extern) or TX */

ERROR: code indent should never use tabs
#247: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:374:
+^I^I^I^I^I^I^I   0 == XEAX (extern) or TX */$

WARNING: Block comments use a trailing */ on a separate line
#247: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:374:
+                                                          0 == XEAX (extern) or TX */

ERROR: code indent should never use tabs
#252: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:379:
+#define XCHAL_HAVE_HALT^I^I^I0^I/* halt architecture option */$

ERROR: code indent should never use tabs
#253: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:380:
+#define XCHAL_HAVE_BOOTLOADER^I^I0^I/* boot loader (for TX) */$

ERROR: code indent should never use tabs
#262: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:420:
+^I^I^I^IDEBUG MODULE$

ERROR: code indent should never use tabs
#266: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:424:
+#define XCHAL_HAVE_DEBUG_ERI^I^I0^I/* ERI to debug module */$

ERROR: code indent should never use tabs
#267: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:425:
+#define XCHAL_HAVE_DEBUG_APB^I^I0^I/* APB to debug module */$

ERROR: code indent should never use tabs
#268: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:426:
+#define XCHAL_HAVE_DEBUG_JTAG^I^I0^I/* JTAG to debug module */$

ERROR: code indent should never use tabs
#275: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:432:
+#define XCHAL_HAVE_OCD_DIR_ARRAY^I0^I/* faster OCD option (to LX4) */$

ERROR: code indent should never use tabs
#276: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:433:
+#define XCHAL_HAVE_OCD_LS32DDR^I^I0^I/* L32DDR/S32DDR (faster OCD) */$

ERROR: code indent should never use tabs
#279: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:436:
+#define XCHAL_HAVE_TRAX^I^I^I0^I/* TRAX in debug module */$

ERROR: code indent should never use tabs
#280: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:437:
+#define XCHAL_TRAX_MEM_SIZE^I^I0^I/* TRAX memory size in bytes */$

ERROR: code indent should never use tabs
#281: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:438:
+#define XCHAL_TRAX_MEM_SHAREABLE^I0^I/* start/end regs; ready sig. */$

ERROR: code indent should never use tabs
#282: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:439:
+#define XCHAL_TRAX_ATB_WIDTH^I^I0^I/* ATB width (bits), 0=no ATB */$

ERROR: code indent should never use tabs
#283: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:440:
+#define XCHAL_TRAX_TIME_WIDTH^I^I0^I/* timestamp bitwidth, 0=none */$

ERROR: code indent should never use tabs
#286: FILE: target/xtensa/core-test_mmuhifi_c3/core-isa.h:443:
+#define XCHAL_NUM_PERF_COUNTERS^I^I0^I/* performance counters */$

WARNING: Block comments use a trailing */ on a separate line
#331: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:22:
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */

ERROR: space required after that ',' (ctx:VxV)
#341: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:63:
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)
            ^

ERROR: space required after that ',' (ctx:VxV)
#341: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:63:
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)
                ^

ERROR: space required after that ',' (ctx:VxV)
#341: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:63:
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)
                         ^

ERROR: space required after that ',' (ctx:VxV)
#341: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:63:
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)
                                ^

ERROR: space required after that ',' (ctx:VxO)
#341: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:63:
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#341: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:63:
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#341: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:63:
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#341: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:63:
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#341: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:63:
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)
                                                                   ^

ERROR: space required after that ',' (ctx:VxV)
#341: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:63:
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)
                                                                     ^

ERROR: space required after that ',' (ctx:VxV)
#341: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:63:
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)
                                                                       ^

ERROR: space required after that ',' (ctx:VxV)
#341: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:63:
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)
                                                                         ^

ERROR: space required after that ',' (ctx:VxV)
#341: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:63:
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)
                                                                           ^

ERROR: space prohibited after that open parenthesis '('
#341: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:63:
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)

ERROR: space required after that ',' (ctx:VxV)
#342: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:64:
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)
            ^

ERROR: space required after that ',' (ctx:VxV)
#342: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:64:
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)
                ^

ERROR: space required after that ',' (ctx:VxV)
#342: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:64:
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)
                         ^

ERROR: space required after that ',' (ctx:VxV)
#342: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:64:
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)
                                ^

ERROR: space required after that ',' (ctx:VxO)
#342: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:64:
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#342: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:64:
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#342: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:64:
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#342: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:64:
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#342: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:64:
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)
                                                                   ^

ERROR: space required after that ',' (ctx:VxV)
#342: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:64:
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)
                                                                     ^

ERROR: space required after that ',' (ctx:VxV)
#342: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:64:
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)
                                                                       ^

ERROR: space required after that ',' (ctx:VxV)
#342: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:64:
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)
                                                                         ^

ERROR: space required after that ',' (ctx:VxV)
#342: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:64:
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)
                                                                           ^

ERROR: space prohibited after that open parenthesis '('
#342: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:64:
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)

ERROR: space required after that ',' (ctx:VxV)
#350: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:142:
+  XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
            ^

ERROR: space required after that ',' (ctx:VxV)
#350: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:142:
+  XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#350: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:142:
+  XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#350: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:142:
+  XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#350: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:142:
+  XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#350: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:142:
+  XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#350: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:142:
+  XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#351: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:143:
+            0,0,&xtensa_mask0,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#351: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:143:
+            0,0,&xtensa_mask0,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#351: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:143:
+            0,0,&xtensa_mask0,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#351: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:143:
+            0,0,&xtensa_mask0,0,0,0)
                              ^

ERROR: space required after that ',' (ctx:VxV)
#351: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:143:
+            0,0,&xtensa_mask0,0,0,0)
                                ^

ERROR: space required after that ',' (ctx:VxV)
#351: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:143:
+            0,0,&xtensa_mask0,0,0,0)
                                  ^

ERROR: space required after that ',' (ctx:VxV)
#352: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:144:
+  XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
            ^

ERROR: space required after that ',' (ctx:VxV)
#352: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:144:
+  XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#352: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:144:
+  XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#352: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:144:
+  XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#352: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:144:
+  XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#352: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:144:
+  XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#352: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:144:
+  XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#353: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:145:
+            0,0,&xtensa_mask1,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#353: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:145:
+            0,0,&xtensa_mask1,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#353: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:145:
+            0,0,&xtensa_mask1,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#353: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:145:
+            0,0,&xtensa_mask1,0,0,0)
                              ^

ERROR: space required after that ',' (ctx:VxV)
#353: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:145:
+            0,0,&xtensa_mask1,0,0,0)
                                ^

ERROR: space required after that ',' (ctx:VxV)
#353: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:145:
+            0,0,&xtensa_mask1,0,0,0)
                                  ^

ERROR: space required after that ',' (ctx:VxV)
#354: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:146:
+  XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
            ^

ERROR: space required after that ',' (ctx:VxV)
#354: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:146:
+  XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#354: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:146:
+  XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#354: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:146:
+  XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#354: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:146:
+  XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#354: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:146:
+  XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#354: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:146:
+  XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#355: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:147:
+            0,0,&xtensa_mask2,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#355: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:147:
+            0,0,&xtensa_mask2,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#355: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:147:
+            0,0,&xtensa_mask2,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#355: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:147:
+            0,0,&xtensa_mask2,0,0,0)
                              ^

ERROR: space required after that ',' (ctx:VxV)
#355: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:147:
+            0,0,&xtensa_mask2,0,0,0)
                                ^

ERROR: space required after that ',' (ctx:VxV)
#355: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:147:
+            0,0,&xtensa_mask2,0,0,0)
                                  ^

ERROR: space required after that ',' (ctx:VxV)
#356: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:148:
+  XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
            ^

ERROR: space required after that ',' (ctx:VxV)
#356: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:148:
+  XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#356: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:148:
+  XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#356: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:148:
+  XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#356: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:148:
+  XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#356: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:148:
+  XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#356: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:148:
+  XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#357: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:149:
+            0,0,&xtensa_mask3,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#357: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:149:
+            0,0,&xtensa_mask3,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#357: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:149:
+            0,0,&xtensa_mask3,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#357: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:149:
+            0,0,&xtensa_mask3,0,0,0)
                              ^

ERROR: space required after that ',' (ctx:VxV)
#357: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:149:
+            0,0,&xtensa_mask3,0,0,0)
                                ^

ERROR: space required after that ',' (ctx:VxV)
#357: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:149:
+            0,0,&xtensa_mask3,0,0,0)
                                  ^

ERROR: space required after that ',' (ctx:VxV)
#358: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:150:
+  XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
            ^

ERROR: space required after that ',' (ctx:VxV)
#358: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:150:
+  XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#358: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:150:
+  XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#358: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:150:
+  XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#358: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:150:
+  XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#358: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:150:
+  XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#358: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:150:
+  XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#359: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:151:
+            0,0,&xtensa_mask4,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#359: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:151:
+            0,0,&xtensa_mask4,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#359: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:151:
+            0,0,&xtensa_mask4,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#359: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:151:
+            0,0,&xtensa_mask4,0,0,0)
                              ^

ERROR: space required after that ',' (ctx:VxV)
#359: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:151:
+            0,0,&xtensa_mask4,0,0,0)
                                ^

ERROR: space required after that ',' (ctx:VxV)
#359: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:151:
+            0,0,&xtensa_mask4,0,0,0)
                                  ^

ERROR: space required after that ',' (ctx:VxV)
#360: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:152:
+  XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
            ^

ERROR: space required after that ',' (ctx:VxV)
#360: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:152:
+  XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#360: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:152:
+  XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#360: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:152:
+  XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#360: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:152:
+  XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#360: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:152:
+  XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#360: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:152:
+  XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#361: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:153:
+            0,0,&xtensa_mask5,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#361: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:153:
+            0,0,&xtensa_mask5,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#361: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:153:
+            0,0,&xtensa_mask5,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#361: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:153:
+            0,0,&xtensa_mask5,0,0,0)
                              ^

ERROR: space required after that ',' (ctx:VxV)
#361: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:153:
+            0,0,&xtensa_mask5,0,0,0)
                                ^

ERROR: space required after that ',' (ctx:VxV)
#361: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:153:
+            0,0,&xtensa_mask5,0,0,0)
                                  ^

ERROR: space required after that ',' (ctx:VxV)
#362: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:154:
+  XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
            ^

ERROR: space required after that ',' (ctx:VxV)
#362: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:154:
+  XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#362: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:154:
+  XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#362: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:154:
+  XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#362: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:154:
+  XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#362: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:154:
+  XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#362: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:154:
+  XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#363: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:155:
+            0,0,&xtensa_mask6,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#363: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:155:
+            0,0,&xtensa_mask6,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#363: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:155:
+            0,0,&xtensa_mask6,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#363: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:155:
+            0,0,&xtensa_mask6,0,0,0)
                              ^

ERROR: space required after that ',' (ctx:VxV)
#363: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:155:
+            0,0,&xtensa_mask6,0,0,0)
                                ^

ERROR: space required after that ',' (ctx:VxV)
#363: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:155:
+            0,0,&xtensa_mask6,0,0,0)
                                  ^

ERROR: space required after that ',' (ctx:VxV)
#364: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:156:
+  XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
            ^

ERROR: space required after that ',' (ctx:VxV)
#364: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:156:
+  XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#364: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:156:
+  XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#364: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:156:
+  XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#364: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:156:
+  XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#364: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:156:
+  XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#364: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:156:
+  XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#365: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:157:
+            0,0,&xtensa_mask7,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#365: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:157:
+            0,0,&xtensa_mask7,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#365: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:157:
+            0,0,&xtensa_mask7,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#365: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:157:
+            0,0,&xtensa_mask7,0,0,0)
                              ^

ERROR: space required after that ',' (ctx:VxV)
#365: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:157:
+            0,0,&xtensa_mask7,0,0,0)
                                ^

ERROR: space required after that ',' (ctx:VxV)
#365: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:157:
+            0,0,&xtensa_mask7,0,0,0)
                                  ^

ERROR: space required after that ',' (ctx:VxV)
#366: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:158:
+  XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
            ^

ERROR: space required after that ',' (ctx:VxV)
#366: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:158:
+  XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#366: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:158:
+  XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#366: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:158:
+  XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#366: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:158:
+  XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#366: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:158:
+  XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#366: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:158:
+  XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#367: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:159:
+            0,0,&xtensa_mask8,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#367: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:159:
+            0,0,&xtensa_mask8,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#367: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:159:
+            0,0,&xtensa_mask8,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#367: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:159:
+            0,0,&xtensa_mask8,0,0,0)
                              ^

ERROR: space required after that ',' (ctx:VxV)
#367: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:159:
+            0,0,&xtensa_mask8,0,0,0)
                                ^

ERROR: space required after that ',' (ctx:VxV)
#367: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:159:
+            0,0,&xtensa_mask8,0,0,0)
                                  ^

ERROR: space required after that ',' (ctx:VxV)
#368: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:160:
+  XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
            ^

ERROR: space required after that ',' (ctx:VxV)
#368: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:160:
+  XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#368: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:160:
+  XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#368: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:160:
+  XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#368: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:160:
+  XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#368: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:160:
+  XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#368: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:160:
+  XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#369: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:161:
+            0,0,&xtensa_mask9,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#369: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:161:
+            0,0,&xtensa_mask9,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#369: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:161:
+            0,0,&xtensa_mask9,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#369: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:161:
+            0,0,&xtensa_mask9,0,0,0)
                              ^

ERROR: space required after that ',' (ctx:VxV)
#369: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:161:
+            0,0,&xtensa_mask9,0,0,0)
                                ^

ERROR: space required after that ',' (ctx:VxV)
#369: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:161:
+            0,0,&xtensa_mask9,0,0,0)
                                  ^

ERROR: space required after that ',' (ctx:VxV)
#370: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:162:
+  XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
            ^

ERROR: space required after that ',' (ctx:VxV)
#370: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:162:
+  XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#370: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:162:
+  XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#370: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:162:
+  XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#370: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:162:
+  XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#370: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:162:
+  XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#370: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:162:
+  XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#371: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:163:
+            0,0,&xtensa_mask10,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#371: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:163:
+            0,0,&xtensa_mask10,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#371: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:163:
+            0,0,&xtensa_mask10,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#371: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:163:
+            0,0,&xtensa_mask10,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#371: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:163:
+            0,0,&xtensa_mask10,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#371: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:163:
+            0,0,&xtensa_mask10,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#372: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:164:
+  XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
            ^

ERROR: space required after that ',' (ctx:VxV)
#372: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:164:
+  XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#372: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:164:
+  XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#372: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:164:
+  XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#372: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:164:
+  XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#372: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:164:
+  XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#372: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:164:
+  XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#373: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:165:
+            0,0,&xtensa_mask11,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#373: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:165:
+            0,0,&xtensa_mask11,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#373: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:165:
+            0,0,&xtensa_mask11,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#373: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:165:
+            0,0,&xtensa_mask11,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#373: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:165:
+            0,0,&xtensa_mask11,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#373: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:165:
+            0,0,&xtensa_mask11,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#374: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:166:
+  XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
            ^

ERROR: space required after that ',' (ctx:VxV)
#374: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:166:
+  XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#374: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:166:
+  XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#374: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:166:
+  XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#374: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:166:
+  XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#374: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:166:
+  XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#374: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:166:
+  XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#375: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:167:
+            0,0,&xtensa_mask12,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#375: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:167:
+            0,0,&xtensa_mask12,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#375: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:167:
+            0,0,&xtensa_mask12,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#375: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:167:
+            0,0,&xtensa_mask12,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#375: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:167:
+            0,0,&xtensa_mask12,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#375: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:167:
+            0,0,&xtensa_mask12,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#376: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:168:
+  XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
            ^

ERROR: space required after that ',' (ctx:VxV)
#376: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:168:
+  XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#376: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:168:
+  XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#376: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:168:
+  XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#376: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:168:
+  XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#376: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:168:
+  XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#376: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:168:
+  XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#377: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:169:
+            0,0,&xtensa_mask13,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#377: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:169:
+            0,0,&xtensa_mask13,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#377: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:169:
+            0,0,&xtensa_mask13,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#377: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:169:
+            0,0,&xtensa_mask13,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#377: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:169:
+            0,0,&xtensa_mask13,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#377: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:169:
+            0,0,&xtensa_mask13,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#378: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:170:
+  XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
            ^

ERROR: space required after that ',' (ctx:VxV)
#378: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:170:
+  XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#378: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:170:
+  XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#378: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:170:
+  XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#378: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:170:
+  XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#378: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:170:
+  XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#378: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:170:
+  XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#379: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:171:
+            0,0,&xtensa_mask14,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#379: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:171:
+            0,0,&xtensa_mask14,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#379: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:171:
+            0,0,&xtensa_mask14,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#379: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:171:
+            0,0,&xtensa_mask14,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#379: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:171:
+            0,0,&xtensa_mask14,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#379: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:171:
+            0,0,&xtensa_mask14,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#380: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:172:
+  XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
            ^

ERROR: space required after that ',' (ctx:VxV)
#380: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:172:
+  XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#380: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:172:
+  XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#380: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:172:
+  XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#380: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:172:
+  XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#380: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:172:
+  XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#380: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:172:
+  XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#381: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:173:
+            0,0,&xtensa_mask15,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#381: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:173:
+            0,0,&xtensa_mask15,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#381: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:173:
+            0,0,&xtensa_mask15,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#381: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:173:
+            0,0,&xtensa_mask15,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#381: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:173:
+            0,0,&xtensa_mask15,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#381: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:173:
+            0,0,&xtensa_mask15,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#382: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:174:
+  XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel,
            ^

ERROR: space required after that ',' (ctx:VxV)
#382: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:174:
+  XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#382: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:174:
+  XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#382: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:174:
+  XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#382: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:174:
+  XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#382: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:174:
+  XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#382: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:174:
+  XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#383: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:175:
+            0,0,&xtensa_mask16,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#383: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:175:
+            0,0,&xtensa_mask16,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#383: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:175:
+            0,0,&xtensa_mask16,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#383: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:175:
+            0,0,&xtensa_mask16,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#383: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:175:
+            0,0,&xtensa_mask16,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#383: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:175:
+            0,0,&xtensa_mask16,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#384: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:176:
+  XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum,
            ^

ERROR: space required after that ',' (ctx:VxV)
#384: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:176:
+  XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#384: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:176:
+  XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#384: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:176:
+  XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#384: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:176:
+  XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#384: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:176:
+  XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#384: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:176:
+  XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#385: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:177:
+            0,0,&xtensa_mask17,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#385: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:177:
+            0,0,&xtensa_mask17,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#385: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:177:
+            0,0,&xtensa_mask17,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#385: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:177:
+            0,0,&xtensa_mask17,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#385: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:177:
+            0,0,&xtensa_mask17,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#385: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:177:
+            0,0,&xtensa_mask17,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#386: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:178:
+  XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe,
            ^

ERROR: space required after that ',' (ctx:VxV)
#386: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:178:
+  XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#386: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:178:
+  XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#386: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:178:
+  XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#386: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:178:
+  XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#386: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:178:
+  XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#386: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:178:
+  XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#387: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:179:
+            0,0,&xtensa_mask18,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#387: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:179:
+            0,0,&xtensa_mask18,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#387: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:179:
+            0,0,&xtensa_mask18,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#387: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:179:
+            0,0,&xtensa_mask18,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#387: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:179:
+            0,0,&xtensa_mask18,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#387: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:179:
+            0,0,&xtensa_mask18,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#388: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:180:
+  XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring,
            ^

ERROR: space required after that ',' (ctx:VxV)
#388: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:180:
+  XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#388: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:180:
+  XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#388: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:180:
+  XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#388: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:180:
+  XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#388: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:180:
+  XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#388: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:180:
+  XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#389: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:181:
+            0,0,&xtensa_mask19,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#389: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:181:
+            0,0,&xtensa_mask19,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#389: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:181:
+            0,0,&xtensa_mask19,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#389: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:181:
+            0,0,&xtensa_mask19,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#389: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:181:
+            0,0,&xtensa_mask19,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#389: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:181:
+            0,0,&xtensa_mask19,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#390: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:182:
+  XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm,
            ^

ERROR: space required after that ',' (ctx:VxV)
#390: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:182:
+  XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#390: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:182:
+  XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#390: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:182:
+  XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#390: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:182:
+  XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#390: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:182:
+  XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#390: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:182:
+  XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#391: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:183:
+            0,0,&xtensa_mask20,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#391: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:183:
+            0,0,&xtensa_mask20,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#391: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:183:
+            0,0,&xtensa_mask20,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#391: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:183:
+            0,0,&xtensa_mask20,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#391: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:183:
+            0,0,&xtensa_mask20,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#391: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:183:
+            0,0,&xtensa_mask20,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#392: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:184:
+  XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc,
            ^

ERROR: space required after that ',' (ctx:VxV)
#392: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:184:
+  XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#392: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:184:
+  XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#392: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:184:
+  XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#392: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:184:
+  XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#392: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:184:
+  XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#392: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:184:
+  XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#393: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:185:
+            0,0,&xtensa_mask21,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#393: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:185:
+            0,0,&xtensa_mask21,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#393: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:185:
+            0,0,&xtensa_mask21,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#393: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:185:
+            0,0,&xtensa_mask21,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#393: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:185:
+            0,0,&xtensa_mask21,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#393: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:185:
+            0,0,&xtensa_mask21,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#394: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:186:
+  XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb,
            ^

ERROR: space required after that ',' (ctx:VxV)
#394: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:186:
+  XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#394: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:186:
+  XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#394: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:186:
+  XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#394: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:186:
+  XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#394: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:186:
+  XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#394: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:186:
+  XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#395: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:187:
+            0,0,&xtensa_mask22,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#395: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:187:
+            0,0,&xtensa_mask22,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#395: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:187:
+            0,0,&xtensa_mask22,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#395: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:187:
+            0,0,&xtensa_mask22,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#395: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:187:
+            0,0,&xtensa_mask22,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#395: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:187:
+            0,0,&xtensa_mask22,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#396: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:188:
+  XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr,
            ^

ERROR: space required after that ',' (ctx:VxV)
#396: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:188:
+  XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr,
                ^

ERROR: space required after that ',' (ctx:VxV)
#396: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:188:
+  XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#396: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:188:
+  XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#396: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:188:
+  XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#396: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:188:
+  XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#396: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:188:
+  XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#396: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:188:
+  XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#397: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:189:
+            0,0,&xtensa_mask23,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#397: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:189:
+            0,0,&xtensa_mask23,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#397: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:189:
+            0,0,&xtensa_mask23,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#397: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:189:
+            0,0,&xtensa_mask23,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#397: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:189:
+            0,0,&xtensa_mask23,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#397: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:189:
+            0,0,&xtensa_mask23,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#398: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:190:
+  XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben,
            ^

ERROR: space required after that ',' (ctx:VxV)
#398: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:190:
+  XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#398: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:190:
+  XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#398: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:190:
+  XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#398: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:190:
+  XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#398: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:190:
+  XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#398: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:190:
+  XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#399: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:191:
+            0,0,&xtensa_mask24,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#399: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:191:
+            0,0,&xtensa_mask24,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#399: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:191:
+            0,0,&xtensa_mask24,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#399: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:191:
+            0,0,&xtensa_mask24,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#399: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:191:
+            0,0,&xtensa_mask24,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#399: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:191:
+            0,0,&xtensa_mask24,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#400: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:192:
+  XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum,
            ^

ERROR: space required after that ',' (ctx:VxV)
#400: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:192:
+  XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#400: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:192:
+  XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#400: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:192:
+  XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#400: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:192:
+  XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#400: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:192:
+  XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#400: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:192:
+  XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#401: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:193:
+            0,0,&xtensa_mask25,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#401: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:193:
+            0,0,&xtensa_mask25,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#401: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:193:
+            0,0,&xtensa_mask25,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#401: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:193:
+            0,0,&xtensa_mask25,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#401: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:193:
+            0,0,&xtensa_mask25,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#401: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:193:
+            0,0,&xtensa_mask25,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#402: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:194:
+  XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3,
            ^

ERROR: space required after that ',' (ctx:VxV)
#402: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:194:
+  XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#402: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:194:
+  XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#402: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:194:
+  XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#402: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:194:
+  XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#402: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:194:
+  XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#402: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:194:
+  XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#403: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:195:
+            0,0,&xtensa_mask26,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#403: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:195:
+            0,0,&xtensa_mask26,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#403: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:195:
+            0,0,&xtensa_mask26,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#403: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:195:
+            0,0,&xtensa_mask26,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#403: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:195:
+            0,0,&xtensa_mask26,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#403: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:195:
+            0,0,&xtensa_mask26,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#404: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:196:
+  XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2,
            ^

ERROR: space required after that ',' (ctx:VxV)
#404: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:196:
+  XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#404: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:196:
+  XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#404: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:196:
+  XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#404: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:196:
+  XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#404: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:196:
+  XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#404: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:196:
+  XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#405: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:197:
+            0,0,&xtensa_mask27,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#405: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:197:
+            0,0,&xtensa_mask27,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#405: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:197:
+            0,0,&xtensa_mask27,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#405: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:197:
+            0,0,&xtensa_mask27,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#405: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:197:
+            0,0,&xtensa_mask27,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#405: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:197:
+            0,0,&xtensa_mask27,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#406: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:198:
+  XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1,
            ^

ERROR: space required after that ',' (ctx:VxV)
#406: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:198:
+  XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#406: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:198:
+  XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#406: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:198:
+  XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#406: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:198:
+  XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#406: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:198:
+  XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#406: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:198:
+  XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#407: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:199:
+            0,0,&xtensa_mask28,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#407: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:199:
+            0,0,&xtensa_mask28,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#407: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:199:
+            0,0,&xtensa_mask28,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#407: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:199:
+            0,0,&xtensa_mask28,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#407: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:199:
+            0,0,&xtensa_mask28,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#407: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:199:
+            0,0,&xtensa_mask28,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#408: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:200:
+  XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4,
            ^

ERROR: space required after that ',' (ctx:VxV)
#408: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:200:
+  XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#408: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:200:
+  XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#408: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:200:
+  XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#408: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:200:
+  XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#408: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:200:
+  XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#408: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:200:
+  XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#409: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:201:
+            0,0,&xtensa_mask29,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#409: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:201:
+            0,0,&xtensa_mask29,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#409: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:201:
+            0,0,&xtensa_mask29,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#409: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:201:
+            0,0,&xtensa_mask29,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#409: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:201:
+            0,0,&xtensa_mask29,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#409: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:201:
+            0,0,&xtensa_mask29,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#410: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:202:
+  XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4,
            ^

ERROR: space required after that ',' (ctx:VxV)
#410: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:202:
+  XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#410: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:202:
+  XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#410: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:202:
+  XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#410: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:202:
+  XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#410: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:202:
+  XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#410: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:202:
+  XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#411: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:203:
+            0,0,&xtensa_mask30,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#411: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:203:
+            0,0,&xtensa_mask30,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#411: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:203:
+            0,0,&xtensa_mask30,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#411: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:203:
+            0,0,&xtensa_mask30,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#411: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:203:
+            0,0,&xtensa_mask30,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#411: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:203:
+            0,0,&xtensa_mask30,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#412: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:204:
+  XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase,
            ^

ERROR: space required after that ',' (ctx:VxV)
#412: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:204:
+  XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase,
                ^

ERROR: space required after that ',' (ctx:VxV)
#412: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:204:
+  XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#412: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:204:
+  XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase,
                                ^

ERROR: space required after that ',' (ctx:VxO)
#412: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:204:
+  XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase,
                                       ^

ERROR: space required before that '-' (ctx:OxV)
#412: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:204:
+  XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase,
                                        ^

ERROR: space required after that ',' (ctx:VxV)
#412: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:204:
+  XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#412: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:204:
+  XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#413: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:205:
+            0,0,&xtensa_mask31,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#413: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:205:
+            0,0,&xtensa_mask31,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#413: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:205:
+            0,0,&xtensa_mask31,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#413: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:205:
+            0,0,&xtensa_mask31,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#413: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:205:
+            0,0,&xtensa_mask31,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#413: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:205:
+            0,0,&xtensa_mask31,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#414: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:206:
+  XTREG(139,556, 1, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_overflow,
            ^

ERROR: space required after that ',' (ctx:VxV)
#414: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:206:
+  XTREG(139,556, 1, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_overflow,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#414: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:206:
+  XTREG(139,556, 1, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_overflow,
                                ^

ERROR: space required after that ',' (ctx:VxV)
#414: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:206:
+  XTREG(139,556, 1, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_overflow,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#414: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:206:
+  XTREG(139,556, 1, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_overflow,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#415: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:207:
+            0,0,&xtensa_mask32,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#415: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:207:
+            0,0,&xtensa_mask32,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#415: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:207:
+            0,0,&xtensa_mask32,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#415: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:207:
+            0,0,&xtensa_mask32,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#415: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:207:
+            0,0,&xtensa_mask32,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#415: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:207:
+            0,0,&xtensa_mask32,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#416: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:208:
+  XTREG(140,560, 6, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_sar,
            ^

ERROR: space required after that ',' (ctx:VxV)
#416: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:208:
+  XTREG(140,560, 6, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_sar,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#416: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:208:
+  XTREG(140,560, 6, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_sar,
                                ^

ERROR: space required after that ',' (ctx:VxV)
#416: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:208:
+  XTREG(140,560, 6, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_sar,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#416: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:208:
+  XTREG(140,560, 6, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_sar,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#417: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:209:
+            0,0,&xtensa_mask33,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#417: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:209:
+            0,0,&xtensa_mask33,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#417: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:209:
+            0,0,&xtensa_mask33,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#417: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:209:
+            0,0,&xtensa_mask33,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#417: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:209:
+            0,0,&xtensa_mask33,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#417: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:209:
+            0,0,&xtensa_mask33,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#418: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:210:
+  XTREG(141,564, 4, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_bitptr,
            ^

ERROR: space required after that ',' (ctx:VxV)
#418: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:210:
+  XTREG(141,564, 4, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_bitptr,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#418: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:210:
+  XTREG(141,564, 4, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_bitptr,
                                ^

ERROR: space required after that ',' (ctx:VxV)
#418: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:210:
+  XTREG(141,564, 4, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_bitptr,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#418: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:210:
+  XTREG(141,564, 4, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_bitptr,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#419: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:211:
+            0,0,&xtensa_mask34,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#419: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:211:
+            0,0,&xtensa_mask34,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#419: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:211:
+            0,0,&xtensa_mask34,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#419: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:211:
+            0,0,&xtensa_mask34,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#419: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:211:
+            0,0,&xtensa_mask34,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#419: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:211:
+            0,0,&xtensa_mask34,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#420: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:212:
+  XTREG(142,568, 4, 4, 4,0x201d,0x0006, 1, 5,0x1010,ae_bitsused,
            ^

ERROR: space required after that ',' (ctx:VxV)
#420: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:212:
+  XTREG(142,568, 4, 4, 4,0x201d,0x0006, 1, 5,0x1010,ae_bitsused,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#420: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:212:
+  XTREG(142,568, 4, 4, 4,0x201d,0x0006, 1, 5,0x1010,ae_bitsused,
                                ^

ERROR: space required after that ',' (ctx:VxV)
#420: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:212:
+  XTREG(142,568, 4, 4, 4,0x201d,0x0006, 1, 5,0x1010,ae_bitsused,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#420: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:212:
+  XTREG(142,568, 4, 4, 4,0x201d,0x0006, 1, 5,0x1010,ae_bitsused,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#421: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:213:
+            0,0,&xtensa_mask35,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#421: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:213:
+            0,0,&xtensa_mask35,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#421: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:213:
+            0,0,&xtensa_mask35,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#421: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:213:
+            0,0,&xtensa_mask35,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#421: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:213:
+            0,0,&xtensa_mask35,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#421: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:213:
+            0,0,&xtensa_mask35,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#422: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:214:
+  XTREG(143,572, 4, 4, 4,0x201e,0x0006, 1, 5,0x1010,ae_tablesize,
            ^

ERROR: space required after that ',' (ctx:VxV)
#422: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:214:
+  XTREG(143,572, 4, 4, 4,0x201e,0x0006, 1, 5,0x1010,ae_tablesize,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#422: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:214:
+  XTREG(143,572, 4, 4, 4,0x201e,0x0006, 1, 5,0x1010,ae_tablesize,
                                ^

ERROR: space required after that ',' (ctx:VxV)
#422: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:214:
+  XTREG(143,572, 4, 4, 4,0x201e,0x0006, 1, 5,0x1010,ae_tablesize,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#422: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:214:
+  XTREG(143,572, 4, 4, 4,0x201e,0x0006, 1, 5,0x1010,ae_tablesize,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#423: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:215:
+            0,0,&xtensa_mask36,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#423: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:215:
+            0,0,&xtensa_mask36,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#423: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:215:
+            0,0,&xtensa_mask36,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#423: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:215:
+            0,0,&xtensa_mask36,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#423: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:215:
+            0,0,&xtensa_mask36,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#423: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:215:
+            0,0,&xtensa_mask36,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#424: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:216:
+  XTREG(144,576, 4, 4, 4,0x201f,0x0006, 1, 5,0x1010,ae_first_ts,
            ^

ERROR: space required after that ',' (ctx:VxV)
#424: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:216:
+  XTREG(144,576, 4, 4, 4,0x201f,0x0006, 1, 5,0x1010,ae_first_ts,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#424: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:216:
+  XTREG(144,576, 4, 4, 4,0x201f,0x0006, 1, 5,0x1010,ae_first_ts,
                                ^

ERROR: space required after that ',' (ctx:VxV)
#424: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:216:
+  XTREG(144,576, 4, 4, 4,0x201f,0x0006, 1, 5,0x1010,ae_first_ts,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#424: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:216:
+  XTREG(144,576, 4, 4, 4,0x201f,0x0006, 1, 5,0x1010,ae_first_ts,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#425: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:217:
+            0,0,&xtensa_mask37,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#425: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:217:
+            0,0,&xtensa_mask37,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#425: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:217:
+            0,0,&xtensa_mask37,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#425: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:217:
+            0,0,&xtensa_mask37,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#425: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:217:
+            0,0,&xtensa_mask37,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#425: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:217:
+            0,0,&xtensa_mask37,0,0,0)
                                   ^

ERROR: space required after that ',' (ctx:VxV)
#426: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:218:
+  XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset,
            ^

ERROR: space required after that ',' (ctx:VxV)
#426: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:218:
+  XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset,
                ^

ERROR: space required after that ',' (ctx:VxV)
#426: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:218:
+  XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset,
                         ^

ERROR: space required after that ',' (ctx:VxV)
#426: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:218:
+  XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset,
                                ^

ERROR: space required after that ',' (ctx:VxV)
#426: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:218:
+  XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset,
                                             ^

ERROR: space required after that ',' (ctx:VxV)
#426: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:218:
+  XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset,
                                                    ^

ERROR: space required after that ',' (ctx:VxV)
#427: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:219:
+            0,0,&xtensa_mask38,0,0,0)
              ^

ERROR: space required after that ',' (ctx:VxO)
#427: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:219:
+            0,0,&xtensa_mask38,0,0,0)
                ^

ERROR: space required before that '&' (ctx:OxV)
#427: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:219:
+            0,0,&xtensa_mask38,0,0,0)
                 ^

ERROR: space required after that ',' (ctx:VxV)
#427: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:219:
+            0,0,&xtensa_mask38,0,0,0)
                               ^

ERROR: space required after that ',' (ctx:VxV)
#427: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:219:
+            0,0,&xtensa_mask38,0,0,0)
                                 ^

ERROR: space required after that ',' (ctx:VxV)
#427: FILE: target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c:219:
+            0,0,&xtensa_mask38,0,0,0)
                                   ^

WARNING: Block comments use a trailing */ on a separate line
#469: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:22:
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */

ERROR: line over 90 characters
#798: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9492:
+  simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;

ERROR: that open brace { should be on the previous line
#853: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9547:
+  switch (ai4const_out_0)
+    {

ERROR: trailing statements should be on next line
#855: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9549:
+    case 0xffffffff: ai4const_in_0 = 0; break;

ERROR: trailing statements should be on next line
#856: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9550:
+    case 0x1: ai4const_in_0 = 0x1; break;

ERROR: trailing statements should be on next line
#857: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9551:
+    case 0x2: ai4const_in_0 = 0x2; break;

ERROR: trailing statements should be on next line
#858: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9552:
+    case 0x3: ai4const_in_0 = 0x3; break;

ERROR: trailing statements should be on next line
#859: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9553:
+    case 0x4: ai4const_in_0 = 0x4; break;

ERROR: trailing statements should be on next line
#860: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9554:
+    case 0x5: ai4const_in_0 = 0x5; break;

ERROR: trailing statements should be on next line
#861: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9555:
+    case 0x6: ai4const_in_0 = 0x6; break;

ERROR: trailing statements should be on next line
#862: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9556:
+    case 0x7: ai4const_in_0 = 0x7; break;

ERROR: trailing statements should be on next line
#863: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9557:
+    case 0x8: ai4const_in_0 = 0x8; break;

ERROR: trailing statements should be on next line
#864: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9558:
+    case 0x9: ai4const_in_0 = 0x9; break;

ERROR: trailing statements should be on next line
#865: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9559:
+    case 0xa: ai4const_in_0 = 0xa; break;

ERROR: trailing statements should be on next line
#866: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9560:
+    case 0xb: ai4const_in_0 = 0xb; break;

ERROR: trailing statements should be on next line
#867: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9561:
+    case 0xc: ai4const_in_0 = 0xc; break;

ERROR: trailing statements should be on next line
#868: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9562:
+    case 0xd: ai4const_in_0 = 0xd; break;

ERROR: trailing statements should be on next line
#869: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9563:
+    case 0xe: ai4const_in_0 = 0xe; break;

ERROR: trailing statements should be on next line
#870: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9564:
+    default: ai4const_in_0 = 0xf; break;

ERROR: that open brace { should be on the previous line
#893: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9587:
+  switch (b4const_out_0)
+    {

ERROR: trailing statements should be on next line
#895: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9589:
+    case 0xffffffff: b4const_in_0 = 0; break;

ERROR: trailing statements should be on next line
#896: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9590:
+    case 0x1: b4const_in_0 = 0x1; break;

ERROR: trailing statements should be on next line
#897: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9591:
+    case 0x2: b4const_in_0 = 0x2; break;

ERROR: trailing statements should be on next line
#898: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9592:
+    case 0x3: b4const_in_0 = 0x3; break;

ERROR: trailing statements should be on next line
#899: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9593:
+    case 0x4: b4const_in_0 = 0x4; break;

ERROR: trailing statements should be on next line
#900: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9594:
+    case 0x5: b4const_in_0 = 0x5; break;

ERROR: trailing statements should be on next line
#901: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9595:
+    case 0x6: b4const_in_0 = 0x6; break;

ERROR: trailing statements should be on next line
#902: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9596:
+    case 0x7: b4const_in_0 = 0x7; break;

ERROR: trailing statements should be on next line
#903: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9597:
+    case 0x8: b4const_in_0 = 0x8; break;

ERROR: trailing statements should be on next line
#904: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9598:
+    case 0xa: b4const_in_0 = 0x9; break;

ERROR: trailing statements should be on next line
#905: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9599:
+    case 0xc: b4const_in_0 = 0xa; break;

ERROR: trailing statements should be on next line
#906: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9600:
+    case 0x10: b4const_in_0 = 0xb; break;

ERROR: trailing statements should be on next line
#907: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9601:
+    case 0x20: b4const_in_0 = 0xc; break;

ERROR: trailing statements should be on next line
#908: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9602:
+    case 0x40: b4const_in_0 = 0xd; break;

ERROR: trailing statements should be on next line
#909: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9603:
+    case 0x80: b4const_in_0 = 0xe; break;

ERROR: trailing statements should be on next line
#910: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9604:
+    default: b4const_in_0 = 0xf; break;

ERROR: that open brace { should be on the previous line
#933: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9627:
+  switch (b4constu_out_0)
+    {

ERROR: trailing statements should be on next line
#935: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9629:
+    case 0x8000: b4constu_in_0 = 0; break;

ERROR: trailing statements should be on next line
#936: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9630:
+    case 0x10000: b4constu_in_0 = 0x1; break;

ERROR: trailing statements should be on next line
#937: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9631:
+    case 0x2: b4constu_in_0 = 0x2; break;

ERROR: trailing statements should be on next line
#938: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9632:
+    case 0x3: b4constu_in_0 = 0x3; break;

ERROR: trailing statements should be on next line
#939: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9633:
+    case 0x4: b4constu_in_0 = 0x4; break;

ERROR: trailing statements should be on next line
#940: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9634:
+    case 0x5: b4constu_in_0 = 0x5; break;

ERROR: trailing statements should be on next line
#941: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9635:
+    case 0x6: b4constu_in_0 = 0x6; break;

ERROR: trailing statements should be on next line
#942: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9636:
+    case 0x7: b4constu_in_0 = 0x7; break;

ERROR: trailing statements should be on next line
#943: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9637:
+    case 0x8: b4constu_in_0 = 0x8; break;

ERROR: trailing statements should be on next line
#944: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9638:
+    case 0xa: b4constu_in_0 = 0x9; break;

ERROR: trailing statements should be on next line
#945: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9639:
+    case 0xc: b4constu_in_0 = 0xa; break;

ERROR: trailing statements should be on next line
#946: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9640:
+    case 0x10: b4constu_in_0 = 0xb; break;

ERROR: trailing statements should be on next line
#947: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9641:
+    case 0x20: b4constu_in_0 = 0xc; break;

ERROR: trailing statements should be on next line
#948: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9642:
+    case 0x40: b4constu_in_0 = 0xd; break;

ERROR: trailing statements should be on next line
#949: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9643:
+    case 0x80: b4constu_in_0 = 0xe; break;

ERROR: trailing statements should be on next line
#950: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:9644:
+    default: b4constu_in_0 = 0xf; break;

ERROR: line over 90 characters
#1850: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:10290:
+  ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf));

WARNING: line over 80 characters
#2887: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:10667:
+    OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,

WARNING: line over 80 characters
#2916: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:10691:
+    OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode,

WARNING: line over 80 characters
#2921: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:10695:
+    OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode,

WARNING: line over 80 characters
#2926: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:10699:
+    OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode,

WARNING: Block comments use a leading /* on a separate line
#4873: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:17372:
+  { 0, 0 /* xt_iclass_simcall */,

ERROR: suspect code indent for conditional statements (2, 6)
#5096: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29403:
+  if (Field_op0_Slot_inst_get (insn) == 0)
     {

ERROR: suspect code indent for conditional statements (6, 10)
#5100: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29405:
+      if (Field_op1_Slot_inst_get (insn) == 0)
        {

ERROR: code indent should never use tabs
#5104: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29407:
+^I  if (Field_op2_Slot_inst_get (insn) == 0)$

ERROR: suspect code indent for conditional statements (10, 14)
#5104: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29407:
+         if (Field_op2_Slot_inst_get (insn) == 0)
            {

ERROR: code indent should never use tabs
#5108: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29409:
+^I      if (Field_r_Slot_inst_get (insn) == 0)$

ERROR: suspect code indent for conditional statements (14, 18)
#5108: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29409:
+             if (Field_r_Slot_inst_get (insn) == 0)
                {

ERROR: code indent should never use tabs
#5172: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29411:
+^I^I  if (Field_m_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#5173: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29412:
+^I^I      Field_s_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#5174: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29413:
+^I^I      Field_n_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#5175: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29414:
+^I^I    return OPCODE_ILL;$

ERROR: code indent should never use tabs
#5176: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29415:
+^I^I  if (Field_m_Slot_inst_get (insn) == 2)$

ERROR: suspect code indent for conditional statements (18, 22)
#5176: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29415:
+                 if (Field_m_Slot_inst_get (insn) == 2)
                    {

ERROR: code indent should never use tabs
#5193: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29417:
+^I^I      if (Field_n_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#5193: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29417:
+                     if (Field_n_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#5194: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29418:
+^I^I^Ireturn OPCODE_RET;$

ERROR: code indent should never use tabs
#5195: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29419:
+^I^I      if (Field_n_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#5195: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29419:
+                     if (Field_n_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#5196: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29420:
+^I^I^Ireturn OPCODE_RETW;$

ERROR: code indent should never use tabs
#5197: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29421:
+^I^I      if (Field_n_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#5197: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29421:
+                     if (Field_n_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#5198: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29422:
+^I^I^Ireturn OPCODE_JX;$

ERROR: code indent should never use tabs
#5205: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29424:
+^I^I  if (Field_m_Slot_inst_get (insn) == 3)$

ERROR: suspect code indent for conditional statements (18, 22)
#5205: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29424:
+                 if (Field_m_Slot_inst_get (insn) == 3)
                    {

ERROR: code indent should never use tabs
#5215: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29426:
+^I^I      if (Field_n_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#5215: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29426:
+                     if (Field_n_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#5216: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29427:
+^I^I^Ireturn OPCODE_CALLX0;$

ERROR: code indent should never use tabs
#5217: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29428:
+^I^I      if (Field_n_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#5217: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29428:
+                     if (Field_n_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#5218: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29429:
+^I^I^Ireturn OPCODE_CALLX4;$

ERROR: code indent should never use tabs
#5219: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29430:
+^I^I      if (Field_n_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#5219: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29430:
+                     if (Field_n_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#5220: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29431:
+^I^I^Ireturn OPCODE_CALLX8;$

ERROR: code indent should never use tabs
#5221: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29432:
+^I^I      if (Field_n_Slot_inst_get (insn) == 3)$

ERROR: braces {} are necessary for all arms of this statement
#5221: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29432:
+                     if (Field_n_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#5222: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29433:
+^I^I^Ireturn OPCODE_CALLX12;$

ERROR: code indent should never use tabs
#5249: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29436:
+^I      if (Field_r_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#5249: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29436:
+             if (Field_r_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#5250: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29437:
+^I^Ireturn OPCODE_MOVSP;$

ERROR: code indent should never use tabs
#5251: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29438:
+^I      if (Field_r_Slot_inst_get (insn) == 2)$

ERROR: suspect code indent for conditional statements (14, 18)
#5251: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29438:
+             if (Field_r_Slot_inst_get (insn) == 2)
                {

ERROR: that open brace { should be on the previous line
#5278: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29440:
                  if (Field_s_Slot_inst_get (insn) == 0)
+                   {

ERROR: suspect code indent for conditional statements (18, 22)
#5278: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29440:
                  if (Field_s_Slot_inst_get (insn) == 0)
+                   {

ERROR: code indent should never use tabs
#5285: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29441:
+^I^I    {$

ERROR: code indent should never use tabs
#5286: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29442:
+^I^I      if (Field_t_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#5286: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29442:
+                     if (Field_t_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#5287: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29443:
+^I^I^Ireturn OPCODE_ISYNC;$

ERROR: code indent should never use tabs
#5288: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29444:
+^I^I      if (Field_t_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#5288: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29444:
+                     if (Field_t_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#5289: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29445:
+^I^I^Ireturn OPCODE_RSYNC;$

ERROR: code indent should never use tabs
#5290: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29446:
+^I^I      if (Field_t_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#5290: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29446:
+                     if (Field_t_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#5291: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29447:
+^I^I^Ireturn OPCODE_ESYNC;$

ERROR: code indent should never use tabs
#5292: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29448:
+^I^I      if (Field_t_Slot_inst_get (insn) == 3)$

ERROR: braces {} are necessary for all arms of this statement
#5292: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29448:
+                     if (Field_t_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#5293: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29449:
+^I^I^Ireturn OPCODE_DSYNC;$

ERROR: code indent should never use tabs
#5294: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29450:
+^I^I      if (Field_t_Slot_inst_get (insn) == 8)$

ERROR: braces {} are necessary for all arms of this statement
#5294: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29450:
+                     if (Field_t_Slot_inst_get (insn) == 8)
[...]

ERROR: code indent should never use tabs
#5295: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29451:
+^I^I^Ireturn OPCODE_EXCW;$

ERROR: code indent should never use tabs
#5296: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29452:
+^I^I      if (Field_t_Slot_inst_get (insn) == 12)$

ERROR: braces {} are necessary for all arms of this statement
#5296: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29452:
+                     if (Field_t_Slot_inst_get (insn) == 12)
[...]

ERROR: code indent should never use tabs
#5297: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29453:
+^I^I^Ireturn OPCODE_MEMW;$

ERROR: code indent should never use tabs
#5298: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29454:
+^I^I      if (Field_t_Slot_inst_get (insn) == 13)$

ERROR: braces {} are necessary for all arms of this statement
#5298: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29454:
+                     if (Field_t_Slot_inst_get (insn) == 13)
[...]

ERROR: code indent should never use tabs
#5299: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29455:
+^I^I^Ireturn OPCODE_EXTW;$

ERROR: code indent should never use tabs
#5300: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29456:
+^I^I      if (Field_t_Slot_inst_get (insn) == 15)$

ERROR: braces {} are necessary for all arms of this statement
#5300: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29456:
+                     if (Field_t_Slot_inst_get (insn) == 15)
[...]

ERROR: code indent should never use tabs
#5301: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29457:
+^I^I^Ireturn OPCODE_NOP;$

ERROR: code indent should never use tabs
#5302: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29458:
+^I^I    }$

ERROR: code indent should never use tabs
#5307: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29460:
+^I      if (Field_r_Slot_inst_get (insn) == 3)$

ERROR: suspect code indent for conditional statements (14, 18)
#5307: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29460:
+             if (Field_r_Slot_inst_get (insn) == 3)
                {

ERROR: that open brace { should be on the previous line
#5328: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29462:
                  if (Field_t_Slot_inst_get (insn) == 0)
+                   {

ERROR: suspect code indent for conditional statements (18, 22)
#5328: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29462:
                  if (Field_t_Slot_inst_get (insn) == 0)
+                   {

ERROR: code indent should never use tabs
#5450: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29463:
+^I^I    {$

ERROR: code indent should never use tabs
#5451: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29464:
+^I^I      if (Field_s_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#5451: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29464:
+                     if (Field_s_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#5452: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29465:
+^I^I^Ireturn OPCODE_RFE;$

ERROR: code indent should never use tabs
#5453: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29466:
+^I^I      if (Field_s_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#5453: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29466:
+                     if (Field_s_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#5454: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29467:
+^I^I^Ireturn OPCODE_RFDE;$

ERROR: code indent should never use tabs
#5455: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29468:
+^I^I      if (Field_s_Slot_inst_get (insn) == 4)$

ERROR: braces {} are necessary for all arms of this statement
#5455: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29468:
+                     if (Field_s_Slot_inst_get (insn) == 4)
[...]

ERROR: code indent should never use tabs
#5456: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29469:
+^I^I^Ireturn OPCODE_RFWO;$

ERROR: code indent should never use tabs
#5457: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29470:
+^I^I      if (Field_s_Slot_inst_get (insn) == 5)$

ERROR: braces {} are necessary for all arms of this statement
#5457: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29470:
+                     if (Field_s_Slot_inst_get (insn) == 5)
[...]

ERROR: code indent should never use tabs
#5458: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29471:
+^I^I^Ireturn OPCODE_RFWU;$

ERROR: code indent should never use tabs
#5459: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29472:
+^I^I    }$

ERROR: code indent should never use tabs
#5460: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29473:
+^I^I  if (Field_t_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#5460: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29473:
+                 if (Field_t_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#5461: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29474:
+^I^I    return OPCODE_RFI;$

ERROR: code indent should never use tabs
#5484: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29476:
+^I      if (Field_r_Slot_inst_get (insn) == 4)$

ERROR: braces {} are necessary for all arms of this statement
#5484: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29476:
+             if (Field_r_Slot_inst_get (insn) == 4)
[...]

ERROR: code indent should never use tabs
#5485: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29477:
+^I^Ireturn OPCODE_BREAK;$

ERROR: code indent should never use tabs
#5486: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29478:
+^I      if (Field_r_Slot_inst_get (insn) == 5)$

ERROR: suspect code indent for conditional statements (14, 18)
#5486: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29478:
+             if (Field_r_Slot_inst_get (insn) == 5)
                {

ERROR: code indent should never use tabs
#5508: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29480:
+^I^I  if (Field_s_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#5509: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29481:
+^I^I      Field_t_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#5510: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29482:
+^I^I    return OPCODE_SYSCALL;$

ERROR: code indent should never use tabs
#5511: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29483:
+^I^I  if (Field_s_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#5512: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29484:
+^I^I      Field_t_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#5513: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29485:
+^I^I    return OPCODE_SIMCALL;$

ERROR: code indent should never use tabs
#5516: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29487:
+^I      if (Field_r_Slot_inst_get (insn) == 6)$

ERROR: braces {} are necessary for all arms of this statement
#5516: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29487:
+             if (Field_r_Slot_inst_get (insn) == 6)
[...]

ERROR: code indent should never use tabs
#5517: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29488:
+^I^Ireturn OPCODE_RSIL;$

ERROR: code indent should never use tabs
#5518: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29489:
+^I      if (Field_r_Slot_inst_get (insn) == 7 &&$

ERROR: code indent should never use tabs
#5519: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29490:
+^I^I  Field_t_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#5520: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29491:
+^I^Ireturn OPCODE_WAITI;$

ERROR: code indent should never use tabs
#5521: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29492:
+^I      if (Field_r_Slot_inst_get (insn) == 8)$

ERROR: braces {} are necessary for all arms of this statement
#5521: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29492:
+             if (Field_r_Slot_inst_get (insn) == 8)
[...]

ERROR: code indent should never use tabs
#5522: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29493:
+^I^Ireturn OPCODE_ANY4;$

ERROR: code indent should never use tabs
#5523: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29494:
+^I      if (Field_r_Slot_inst_get (insn) == 9)$

ERROR: braces {} are necessary for all arms of this statement
#5523: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29494:
+             if (Field_r_Slot_inst_get (insn) == 9)
[...]

ERROR: code indent should never use tabs
#5524: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29495:
+^I^Ireturn OPCODE_ALL4;$

ERROR: code indent should never use tabs
#5525: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29496:
+^I      if (Field_r_Slot_inst_get (insn) == 10)$

ERROR: braces {} are necessary for all arms of this statement
#5525: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29496:
+             if (Field_r_Slot_inst_get (insn) == 10)
[...]

ERROR: code indent should never use tabs
#5526: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29497:
+^I^Ireturn OPCODE_ANY8;$

ERROR: code indent should never use tabs
#5527: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29498:
+^I      if (Field_r_Slot_inst_get (insn) == 11)$

ERROR: braces {} are necessary for all arms of this statement
#5527: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29498:
+             if (Field_r_Slot_inst_get (insn) == 11)
[...]

ERROR: code indent should never use tabs
#5528: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29499:
+^I^Ireturn OPCODE_ALL8;$

ERROR: code indent should never use tabs
#5533: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29501:
+^I  if (Field_op2_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#5533: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29501:
+         if (Field_op2_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#5534: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29502:
+^I    return OPCODE_AND;$

ERROR: code indent should never use tabs
#5535: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29503:
+^I  if (Field_op2_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#5535: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29503:
+         if (Field_op2_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#5536: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29504:
+^I    return OPCODE_OR;$

ERROR: code indent should never use tabs
#5537: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29505:
+^I  if (Field_op2_Slot_inst_get (insn) == 3)$

ERROR: braces {} are necessary for all arms of this statement
#5537: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29505:
+         if (Field_op2_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#5538: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29506:
+^I    return OPCODE_XOR;$

ERROR: code indent should never use tabs
#5539: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29507:
+^I  if (Field_op2_Slot_inst_get (insn) == 4)$

ERROR: suspect code indent for conditional statements (10, 14)
#5539: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29507:
+         if (Field_op2_Slot_inst_get (insn) == 4)
            {

ERROR: code indent should never use tabs
#5553: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29509:
+^I      if (Field_r_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#5554: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29510:
+^I^I  Field_t_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#5555: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29511:
+^I^Ireturn OPCODE_SSR;$

ERROR: code indent should never use tabs
#5556: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29512:
+^I      if (Field_r_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#5557: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29513:
+^I^I  Field_t_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#5558: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29514:
+^I^Ireturn OPCODE_SSL;$

ERROR: code indent should never use tabs
#5559: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29515:
+^I      if (Field_r_Slot_inst_get (insn) == 2 &&$

ERROR: code indent should never use tabs
#5560: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29516:
+^I^I  Field_t_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#5561: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29517:
+^I^Ireturn OPCODE_SSA8L;$

ERROR: code indent should never use tabs
#5562: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29518:
+^I      if (Field_r_Slot_inst_get (insn) == 3 &&$

ERROR: code indent should never use tabs
#5563: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29519:
+^I^I  Field_t_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#5564: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29520:
+^I^Ireturn OPCODE_SSA8B;$

ERROR: code indent should never use tabs
#5565: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29521:
+^I      if (Field_r_Slot_inst_get (insn) == 4 &&$

ERROR: code indent should never use tabs
#5566: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29522:
+^I^I  Field_thi3_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#5567: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29523:
+^I^Ireturn OPCODE_SSAI;$

ERROR: code indent should never use tabs
#5568: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29524:
+^I      if (Field_r_Slot_inst_get (insn) == 6)$

ERROR: braces {} are necessary for all arms of this statement
#5568: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29524:
+             if (Field_r_Slot_inst_get (insn) == 6)
[...]

ERROR: code indent should never use tabs
#5569: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29525:
+^I^Ireturn OPCODE_RER;$

ERROR: code indent should never use tabs
#5570: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29526:
+^I      if (Field_r_Slot_inst_get (insn) == 7)$

ERROR: braces {} are necessary for all arms of this statement
#5570: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29526:
+             if (Field_r_Slot_inst_get (insn) == 7)
[...]

ERROR: code indent should never use tabs
#5571: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29527:
+^I^Ireturn OPCODE_WER;$

ERROR: code indent should never use tabs
#5572: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29528:
+^I      if (Field_r_Slot_inst_get (insn) == 8 &&$

ERROR: code indent should never use tabs
#5573: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29529:
+^I^I  Field_s_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#5574: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29530:
+^I^Ireturn OPCODE_ROTW;$

ERROR: code indent should never use tabs
#5575: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29531:
+^I      if (Field_r_Slot_inst_get (insn) == 14)$

ERROR: braces {} are necessary for all arms of this statement
#5575: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29531:
+             if (Field_r_Slot_inst_get (insn) == 14)
[...]

ERROR: code indent should never use tabs
#5576: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29532:
+^I^Ireturn OPCODE_NSA;$

ERROR: code indent should never use tabs
#5577: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29533:
+^I      if (Field_r_Slot_inst_get (insn) == 15)$

ERROR: braces {} are necessary for all arms of this statement
#5577: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29533:
+             if (Field_r_Slot_inst_get (insn) == 15)
[...]

ERROR: code indent should never use tabs
#5578: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29534:
+^I^Ireturn OPCODE_NSAU;$

ERROR: code indent should never use tabs
#5583: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29536:
+^I  if (Field_op2_Slot_inst_get (insn) == 5)$

ERROR: suspect code indent for conditional statements (10, 14)
#5583: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29536:
+         if (Field_op2_Slot_inst_get (insn) == 5)
            {

ERROR: code indent should never use tabs
#5803: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29538:
+^I      if (Field_r_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#5803: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29538:
+             if (Field_r_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#5804: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29539:
+^I^Ireturn OPCODE_HWWITLBA;$

ERROR: code indent should never use tabs
#5805: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29540:
+^I      if (Field_r_Slot_inst_get (insn) == 3)$

ERROR: braces {} are necessary for all arms of this statement
#5805: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29540:
+             if (Field_r_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#5806: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29541:
+^I^Ireturn OPCODE_RITLB0;$

ERROR: code indent should never use tabs
#5807: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29542:
+^I      if (Field_r_Slot_inst_get (insn) == 4 &&$

ERROR: code indent should never use tabs
#5808: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29543:
+^I^I  Field_t_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#5809: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29544:
+^I^Ireturn OPCODE_IITLB;$

ERROR: code indent should never use tabs
#5810: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29545:
+^I      if (Field_r_Slot_inst_get (insn) == 5)$

ERROR: braces {} are necessary for all arms of this statement
#5810: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29545:
+             if (Field_r_Slot_inst_get (insn) == 5)
[...]

ERROR: code indent should never use tabs
#5811: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29546:
+^I^Ireturn OPCODE_PITLB;$

ERROR: code indent should never use tabs
#5812: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29547:
+^I      if (Field_r_Slot_inst_get (insn) == 6)$

ERROR: braces {} are necessary for all arms of this statement
#5812: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29547:
+             if (Field_r_Slot_inst_get (insn) == 6)
[...]

ERROR: code indent should never use tabs
#5813: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29548:
+^I^Ireturn OPCODE_WITLB;$

ERROR: code indent should never use tabs
#5814: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29549:
+^I      if (Field_r_Slot_inst_get (insn) == 7)$

ERROR: braces {} are necessary for all arms of this statement
#5814: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29549:
+             if (Field_r_Slot_inst_get (insn) == 7)
[...]

ERROR: code indent should never use tabs
#5815: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29550:
+^I^Ireturn OPCODE_RITLB1;$

ERROR: code indent should never use tabs
#5816: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29551:
+^I      if (Field_r_Slot_inst_get (insn) == 9)$

ERROR: braces {} are necessary for all arms of this statement
#5816: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29551:
+             if (Field_r_Slot_inst_get (insn) == 9)
[...]

ERROR: code indent should never use tabs
#5817: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29552:
+^I^Ireturn OPCODE_HWWDTLBA;$

ERROR: code indent should never use tabs
#5818: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29553:
+^I      if (Field_r_Slot_inst_get (insn) == 11)$

ERROR: braces {} are necessary for all arms of this statement
#5818: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29553:
+             if (Field_r_Slot_inst_get (insn) == 11)
[...]

ERROR: code indent should never use tabs
#5819: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29554:
+^I^Ireturn OPCODE_RDTLB0;$

ERROR: code indent should never use tabs
#5820: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29555:
+^I      if (Field_r_Slot_inst_get (insn) == 12 &&$

ERROR: code indent should never use tabs
#5821: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29556:
+^I^I  Field_t_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#5822: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29557:
+^I^Ireturn OPCODE_IDTLB;$

ERROR: code indent should never use tabs
#5823: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29558:
+^I      if (Field_r_Slot_inst_get (insn) == 13)$

ERROR: braces {} are necessary for all arms of this statement
#5823: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29558:
+             if (Field_r_Slot_inst_get (insn) == 13)
[...]

ERROR: code indent should never use tabs
#5824: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29559:
+^I^Ireturn OPCODE_PDTLB;$

ERROR: code indent should never use tabs
#5825: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29560:
+^I      if (Field_r_Slot_inst_get (insn) == 14)$

ERROR: braces {} are necessary for all arms of this statement
#5825: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29560:
+             if (Field_r_Slot_inst_get (insn) == 14)
[...]

ERROR: code indent should never use tabs
#5826: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29561:
+^I^Ireturn OPCODE_WDTLB;$

ERROR: code indent should never use tabs
#5827: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29562:
+^I      if (Field_r_Slot_inst_get (insn) == 15)$

ERROR: braces {} are necessary for all arms of this statement
#5827: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29562:
+             if (Field_r_Slot_inst_get (insn) == 15)
[...]

ERROR: code indent should never use tabs
#5828: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29563:
+^I^Ireturn OPCODE_RDTLB1;$

ERROR: code indent should never use tabs
#5836: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29565:
+^I  if (Field_op2_Slot_inst_get (insn) == 6)$

ERROR: suspect code indent for conditional statements (10, 14)
#5836: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29565:
+         if (Field_op2_Slot_inst_get (insn) == 6)
            {

ERROR: code indent should never use tabs
#5842: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29567:
+^I      if (Field_s_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#5842: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29567:
+             if (Field_s_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#5843: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29568:
+^I^Ireturn OPCODE_NEG;$

ERROR: code indent should never use tabs
#5844: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29569:
+^I      if (Field_s_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#5844: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29569:
+             if (Field_s_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#5845: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29570:
+^I^Ireturn OPCODE_ABS;$

ERROR: code indent should never use tabs
#5848: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29572:
+^I  if (Field_op2_Slot_inst_get (insn) == 8)$

ERROR: braces {} are necessary for all arms of this statement
#5848: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29572:
+         if (Field_op2_Slot_inst_get (insn) == 8)
[...]

ERROR: code indent should never use tabs
#5849: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29573:
+^I    return OPCODE_ADD;$

ERROR: code indent should never use tabs
#5850: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29574:
+^I  if (Field_op2_Slot_inst_get (insn) == 9)$

ERROR: braces {} are necessary for all arms of this statement
#5850: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29574:
+         if (Field_op2_Slot_inst_get (insn) == 9)
[...]

ERROR: code indent should never use tabs
#5851: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29575:
+^I    return OPCODE_ADDX2;$

ERROR: code indent should never use tabs
#5852: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29576:
+^I  if (Field_op2_Slot_inst_get (insn) == 10)$

ERROR: braces {} are necessary for all arms of this statement
#5852: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29576:
+         if (Field_op2_Slot_inst_get (insn) == 10)
[...]

ERROR: code indent should never use tabs
#5853: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29577:
+^I    return OPCODE_ADDX4;$

ERROR: code indent should never use tabs
#5854: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29578:
+^I  if (Field_op2_Slot_inst_get (insn) == 11)$

ERROR: braces {} are necessary for all arms of this statement
#5854: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29578:
+         if (Field_op2_Slot_inst_get (insn) == 11)
[...]

ERROR: code indent should never use tabs
#5855: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29579:
+^I    return OPCODE_ADDX8;$

ERROR: code indent should never use tabs
#5856: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29580:
+^I  if (Field_op2_Slot_inst_get (insn) == 12)$

ERROR: braces {} are necessary for all arms of this statement
#5856: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29580:
+         if (Field_op2_Slot_inst_get (insn) == 12)
[...]

ERROR: code indent should never use tabs
#5857: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29581:
+^I    return OPCODE_SUB;$

ERROR: code indent should never use tabs
#5858: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29582:
+^I  if (Field_op2_Slot_inst_get (insn) == 13)$

ERROR: braces {} are necessary for all arms of this statement
#5858: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29582:
+         if (Field_op2_Slot_inst_get (insn) == 13)
[...]

ERROR: code indent should never use tabs
#5859: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29583:
+^I    return OPCODE_SUBX2;$

ERROR: code indent should never use tabs
#5860: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29584:
+^I  if (Field_op2_Slot_inst_get (insn) == 14)$

ERROR: braces {} are necessary for all arms of this statement
#5860: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29584:
+         if (Field_op2_Slot_inst_get (insn) == 14)
[...]

ERROR: code indent should never use tabs
#5861: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29585:
+^I    return OPCODE_SUBX4;$

ERROR: code indent should never use tabs
#5862: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29586:
+^I  if (Field_op2_Slot_inst_get (insn) == 15)$

ERROR: braces {} are necessary for all arms of this statement
#5862: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29586:
+         if (Field_op2_Slot_inst_get (insn) == 15)
[...]

ERROR: code indent should never use tabs
#5863: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29587:
+^I    return OPCODE_SUBX8;$

ERROR: suspect code indent for conditional statements (6, 10)
#5870: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29589:
+      if (Field_op1_Slot_inst_get (insn) == 1)
        {

ERROR: code indent should never use tabs
#5886: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29591:
+^I  if ((Field_op2_Slot_inst_get (insn) == 0 ||$

ERROR: code indent should never use tabs
#5887: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29592:
+^I       Field_op2_Slot_inst_get (insn) == 1))$

ERROR: code indent should never use tabs
#5888: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29593:
+^I    return OPCODE_SLLI;$

ERROR: code indent should never use tabs
#5889: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29594:
+^I  if ((Field_op2_Slot_inst_get (insn) == 2 ||$

ERROR: code indent should never use tabs
#5890: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29595:
+^I       Field_op2_Slot_inst_get (insn) == 3))$

ERROR: code indent should never use tabs
#5891: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29596:
+^I    return OPCODE_SRAI;$

ERROR: code indent should never use tabs
#5892: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29597:
+^I  if (Field_op2_Slot_inst_get (insn) == 4)$

ERROR: braces {} are necessary for all arms of this statement
#5892: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29597:
+         if (Field_op2_Slot_inst_get (insn) == 4)
[...]

ERROR: code indent should never use tabs
#5893: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29598:
+^I    return OPCODE_SRLI;$

ERROR: code indent should never use tabs
#5894: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29599:
+^I  if (Field_op2_Slot_inst_get (insn) == 6)$

ERROR: suspect code indent for conditional statements (10, 14)
#5894: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29599:
+         if (Field_op2_Slot_inst_get (insn) == 6)
            {

ERROR: code indent should never use tabs
#5927: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29601:
+^I      if (Field_sr_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#5927: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29601:
+             if (Field_sr_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#5928: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29602:
+^I^Ireturn OPCODE_XSR_LBEG;$

ERROR: code indent should never use tabs
#5929: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29603:
+^I      if (Field_sr_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#5929: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29603:
+             if (Field_sr_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#5930: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29604:
+^I^Ireturn OPCODE_XSR_LEND;$

ERROR: code indent should never use tabs
#5931: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29605:
+^I      if (Field_sr_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#5931: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29605:
+             if (Field_sr_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#5932: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29606:
+^I^Ireturn OPCODE_XSR_LCOUNT;$

ERROR: code indent should never use tabs
#5933: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29607:
+^I      if (Field_sr_Slot_inst_get (insn) == 3)$

ERROR: braces {} are necessary for all arms of this statement
#5933: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29607:
+             if (Field_sr_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#5934: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29608:
+^I^Ireturn OPCODE_XSR_SAR;$

ERROR: code indent should never use tabs
#5935: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29609:
+^I      if (Field_sr_Slot_inst_get (insn) == 4)$

ERROR: braces {} are necessary for all arms of this statement
#5935: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29609:
+             if (Field_sr_Slot_inst_get (insn) == 4)
[...]

ERROR: code indent should never use tabs
#5936: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29610:
+^I^Ireturn OPCODE_XSR_BR;$

ERROR: code indent should never use tabs
#5937: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29611:
+^I      if (Field_sr_Slot_inst_get (insn) == 5)$

ERROR: braces {} are necessary for all arms of this statement
#5937: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29611:
+             if (Field_sr_Slot_inst_get (insn) == 5)
[...]

ERROR: code indent should never use tabs
#5938: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29612:
+^I^Ireturn OPCODE_XSR_LITBASE;$

ERROR: code indent should never use tabs
#5939: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29613:
+^I      if (Field_sr_Slot_inst_get (insn) == 12)$

ERROR: braces {} are necessary for all arms of this statement
#5939: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29613:
+             if (Field_sr_Slot_inst_get (insn) == 12)
[...]

ERROR: code indent should never use tabs
#5940: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29614:
+^I^Ireturn OPCODE_XSR_SCOMPARE1;$

ERROR: code indent should never use tabs
#5941: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29615:
+^I      if (Field_sr_Slot_inst_get (insn) == 72)$

ERROR: braces {} are necessary for all arms of this statement
#5941: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29615:
+             if (Field_sr_Slot_inst_get (insn) == 72)
[...]

ERROR: code indent should never use tabs
#5942: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29616:
+^I^Ireturn OPCODE_XSR_WINDOWBASE;$

ERROR: code indent should never use tabs
#5943: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29617:
+^I      if (Field_sr_Slot_inst_get (insn) == 73)$

ERROR: braces {} are necessary for all arms of this statement
#5943: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29617:
+             if (Field_sr_Slot_inst_get (insn) == 73)
[...]

ERROR: code indent should never use tabs
#5944: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29618:
+^I^Ireturn OPCODE_XSR_WINDOWSTART;$

ERROR: code indent should never use tabs
#5945: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29619:
+^I      if (Field_sr_Slot_inst_get (insn) == 83)$

ERROR: braces {} are necessary for all arms of this statement
#5945: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29619:
+             if (Field_sr_Slot_inst_get (insn) == 83)
[...]

ERROR: code indent should never use tabs
#5946: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29620:
+^I^Ireturn OPCODE_XSR_PTEVADDR;$

ERROR: code indent should never use tabs
#5947: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29621:
+^I      if (Field_sr_Slot_inst_get (insn) == 90)$

ERROR: braces {} are necessary for all arms of this statement
#5947: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29621:
+             if (Field_sr_Slot_inst_get (insn) == 90)
[...]

ERROR: code indent should never use tabs
#5948: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29622:
+^I^Ireturn OPCODE_XSR_RASID;$

ERROR: code indent should never use tabs
#5949: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29623:
+^I      if (Field_sr_Slot_inst_get (insn) == 91)$

ERROR: braces {} are necessary for all arms of this statement
#5949: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29623:
+             if (Field_sr_Slot_inst_get (insn) == 91)
[...]

ERROR: code indent should never use tabs
#5950: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29624:
+^I^Ireturn OPCODE_XSR_ITLBCFG;$

ERROR: code indent should never use tabs
#5951: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29625:
+^I      if (Field_sr_Slot_inst_get (insn) == 92)$

ERROR: braces {} are necessary for all arms of this statement
#5951: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29625:
+             if (Field_sr_Slot_inst_get (insn) == 92)
[...]

ERROR: code indent should never use tabs
#5952: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29626:
+^I^Ireturn OPCODE_XSR_DTLBCFG;$

ERROR: code indent should never use tabs
#5953: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29627:
+^I      if (Field_sr_Slot_inst_get (insn) == 99)$

ERROR: braces {} are necessary for all arms of this statement
#5953: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29627:
+             if (Field_sr_Slot_inst_get (insn) == 99)
[...]

ERROR: code indent should never use tabs
#5954: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29628:
+^I^Ireturn OPCODE_XSR_ATOMCTL;$

ERROR: code indent should never use tabs
#5955: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29629:
+^I      if (Field_sr_Slot_inst_get (insn) == 104)$

ERROR: braces {} are necessary for all arms of this statement
#5955: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29629:
+             if (Field_sr_Slot_inst_get (insn) == 104)
[...]

ERROR: code indent should never use tabs
#5956: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29630:
+^I^Ireturn OPCODE_XSR_DDR;$

ERROR: code indent should never use tabs
#5957: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29631:
+^I      if (Field_sr_Slot_inst_get (insn) == 177)$

ERROR: braces {} are necessary for all arms of this statement
#5957: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29631:
+             if (Field_sr_Slot_inst_get (insn) == 177)
[...]

ERROR: code indent should never use tabs
#5958: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29632:
+^I^Ireturn OPCODE_XSR_EPC1;$

ERROR: code indent should never use tabs
#5959: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29633:
+^I      if (Field_sr_Slot_inst_get (insn) == 178)$

ERROR: braces {} are necessary for all arms of this statement
#5959: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29633:
+             if (Field_sr_Slot_inst_get (insn) == 178)
[...]

ERROR: code indent should never use tabs
#5960: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29634:
+^I^Ireturn OPCODE_XSR_EPC2;$

ERROR: code indent should never use tabs
#5961: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29635:
+^I      if (Field_sr_Slot_inst_get (insn) == 192)$

ERROR: braces {} are necessary for all arms of this statement
#5961: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29635:
+             if (Field_sr_Slot_inst_get (insn) == 192)
[...]

ERROR: code indent should never use tabs
#5962: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29636:
+^I^Ireturn OPCODE_XSR_DEPC;$

ERROR: code indent should never use tabs
#5963: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29637:
+^I      if (Field_sr_Slot_inst_get (insn) == 194)$

ERROR: braces {} are necessary for all arms of this statement
#5963: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29637:
+             if (Field_sr_Slot_inst_get (insn) == 194)
[...]

ERROR: code indent should never use tabs
#5964: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29638:
+^I^Ireturn OPCODE_XSR_EPS2;$

ERROR: code indent should never use tabs
#5965: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29639:
+^I      if (Field_sr_Slot_inst_get (insn) == 209)$

ERROR: braces {} are necessary for all arms of this statement
#5965: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29639:
+             if (Field_sr_Slot_inst_get (insn) == 209)
[...]

ERROR: code indent should never use tabs
#5966: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29640:
+^I^Ireturn OPCODE_XSR_EXCSAVE1;$

ERROR: code indent should never use tabs
#5967: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29641:
+^I      if (Field_sr_Slot_inst_get (insn) == 210)$

ERROR: braces {} are necessary for all arms of this statement
#5967: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29641:
+             if (Field_sr_Slot_inst_get (insn) == 210)
[...]

ERROR: code indent should never use tabs
#5968: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29642:
+^I^Ireturn OPCODE_XSR_EXCSAVE2;$

ERROR: code indent should never use tabs
#5969: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29643:
+^I      if (Field_sr_Slot_inst_get (insn) == 224)$

ERROR: braces {} are necessary for all arms of this statement
#5969: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29643:
+             if (Field_sr_Slot_inst_get (insn) == 224)
[...]

ERROR: code indent should never use tabs
#5970: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29644:
+^I^Ireturn OPCODE_XSR_CPENABLE;$

ERROR: code indent should never use tabs
#5971: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29645:
+^I      if (Field_sr_Slot_inst_get (insn) == 228)$

ERROR: braces {} are necessary for all arms of this statement
#5971: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29645:
+             if (Field_sr_Slot_inst_get (insn) == 228)
[...]

ERROR: code indent should never use tabs
#5972: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29646:
+^I^Ireturn OPCODE_XSR_INTENABLE;$

ERROR: code indent should never use tabs
#5973: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29647:
+^I      if (Field_sr_Slot_inst_get (insn) == 230)$

ERROR: braces {} are necessary for all arms of this statement
#5973: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29647:
+             if (Field_sr_Slot_inst_get (insn) == 230)
[...]

ERROR: code indent should never use tabs
#5974: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29648:
+^I^Ireturn OPCODE_XSR_PS;$

ERROR: code indent should never use tabs
#5975: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29649:
+^I      if (Field_sr_Slot_inst_get (insn) == 231)$

ERROR: braces {} are necessary for all arms of this statement
#5975: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29649:
+             if (Field_sr_Slot_inst_get (insn) == 231)
[...]

ERROR: code indent should never use tabs
#5976: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29650:
+^I^Ireturn OPCODE_XSR_VECBASE;$

ERROR: code indent should never use tabs
#5977: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29651:
+^I      if (Field_sr_Slot_inst_get (insn) == 232)$

ERROR: braces {} are necessary for all arms of this statement
#5977: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29651:
+             if (Field_sr_Slot_inst_get (insn) == 232)
[...]

ERROR: code indent should never use tabs
#5978: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29652:
+^I^Ireturn OPCODE_XSR_EXCCAUSE;$

ERROR: code indent should never use tabs
#5979: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29653:
+^I      if (Field_sr_Slot_inst_get (insn) == 233)$

ERROR: braces {} are necessary for all arms of this statement
#5979: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29653:
+             if (Field_sr_Slot_inst_get (insn) == 233)
[...]

ERROR: code indent should never use tabs
#5980: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29654:
+^I^Ireturn OPCODE_XSR_DEBUGCAUSE;$

ERROR: code indent should never use tabs
#5981: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29655:
+^I      if (Field_sr_Slot_inst_get (insn) == 234)$

ERROR: braces {} are necessary for all arms of this statement
#5981: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29655:
+             if (Field_sr_Slot_inst_get (insn) == 234)
[...]

ERROR: code indent should never use tabs
#5982: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29656:
+^I^Ireturn OPCODE_XSR_CCOUNT;$

ERROR: code indent should never use tabs
#5983: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29657:
+^I      if (Field_sr_Slot_inst_get (insn) == 236)$

ERROR: braces {} are necessary for all arms of this statement
#5983: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29657:
+             if (Field_sr_Slot_inst_get (insn) == 236)
[...]

ERROR: code indent should never use tabs
#5984: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29658:
+^I^Ireturn OPCODE_XSR_ICOUNT;$

ERROR: code indent should never use tabs
#5985: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29659:
+^I      if (Field_sr_Slot_inst_get (insn) == 237)$

ERROR: braces {} are necessary for all arms of this statement
#5985: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29659:
+             if (Field_sr_Slot_inst_get (insn) == 237)
[...]

ERROR: code indent should never use tabs
#5986: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29660:
+^I^Ireturn OPCODE_XSR_ICOUNTLEVEL;$

ERROR: code indent should never use tabs
#5987: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29661:
+^I      if (Field_sr_Slot_inst_get (insn) == 238)$

ERROR: braces {} are necessary for all arms of this statement
#5987: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29661:
+             if (Field_sr_Slot_inst_get (insn) == 238)
[...]

ERROR: code indent should never use tabs
#5988: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29662:
+^I^Ireturn OPCODE_XSR_EXCVADDR;$

ERROR: code indent should never use tabs
#5989: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29663:
+^I      if (Field_sr_Slot_inst_get (insn) == 240)$

ERROR: braces {} are necessary for all arms of this statement
#5989: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29663:
+             if (Field_sr_Slot_inst_get (insn) == 240)
[...]

ERROR: code indent should never use tabs
#5990: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29664:
+^I^Ireturn OPCODE_XSR_CCOMPARE0;$

ERROR: code indent should never use tabs
#5991: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29665:
+^I      if (Field_sr_Slot_inst_get (insn) == 241)$

ERROR: braces {} are necessary for all arms of this statement
#5991: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29665:
+             if (Field_sr_Slot_inst_get (insn) == 241)
[...]

ERROR: code indent should never use tabs
#5992: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29666:
+^I^Ireturn OPCODE_XSR_CCOMPARE1;$

ERROR: code indent should never use tabs
#5993: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29667:
+^I      if (Field_sr_Slot_inst_get (insn) == 244)$

ERROR: braces {} are necessary for all arms of this statement
#5993: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29667:
+             if (Field_sr_Slot_inst_get (insn) == 244)
[...]

ERROR: code indent should never use tabs
#5994: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29668:
+^I^Ireturn OPCODE_XSR_MISC0;$

ERROR: code indent should never use tabs
#5995: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29669:
+^I      if (Field_sr_Slot_inst_get (insn) == 245)$

ERROR: braces {} are necessary for all arms of this statement
#5995: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29669:
+             if (Field_sr_Slot_inst_get (insn) == 245)
[...]

ERROR: code indent should never use tabs
#5996: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29670:
+^I^Ireturn OPCODE_XSR_MISC1;$

ERROR: code indent should never use tabs
#5997: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29671:
+^I    }$

ERROR: code indent should never use tabs
#5998: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29672:
+^I  if (Field_op2_Slot_inst_get (insn) == 8)$

ERROR: braces {} are necessary for all arms of this statement
#5998: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29672:
+         if (Field_op2_Slot_inst_get (insn) == 8)
[...]

ERROR: code indent should never use tabs
#5999: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29673:
+^I    return OPCODE_SRC;$

ERROR: code indent should never use tabs
#6000: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29674:
+^I  if (Field_op2_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#6001: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29675:
+^I      Field_s_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#6002: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29676:
+^I    return OPCODE_SRL;$

ERROR: code indent should never use tabs
#6003: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29677:
+^I  if (Field_op2_Slot_inst_get (insn) == 10 &&$

ERROR: code indent should never use tabs
#6004: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29678:
+^I      Field_t_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#6005: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29679:
+^I    return OPCODE_SLL;$

ERROR: code indent should never use tabs
#6006: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29680:
+^I  if (Field_op2_Slot_inst_get (insn) == 11 &&$

ERROR: code indent should never use tabs
#6007: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29681:
+^I      Field_s_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#6008: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29682:
+^I    return OPCODE_SRA;$

ERROR: code indent should never use tabs
#6009: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29683:
+^I  if (Field_op2_Slot_inst_get (insn) == 12)$

ERROR: braces {} are necessary for all arms of this statement
#6009: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29683:
+         if (Field_op2_Slot_inst_get (insn) == 12)
[...]

ERROR: code indent should never use tabs
#6010: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29684:
+^I    return OPCODE_MUL16U;$

ERROR: code indent should never use tabs
#6011: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29685:
+^I  if (Field_op2_Slot_inst_get (insn) == 13)$

ERROR: braces {} are necessary for all arms of this statement
#6011: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29685:
+         if (Field_op2_Slot_inst_get (insn) == 13)
[...]

ERROR: code indent should never use tabs
#6012: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29686:
+^I    return OPCODE_MUL16S;$

ERROR: code indent should never use tabs
#6013: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29687:
+^I  if (Field_op2_Slot_inst_get (insn) == 15)$

ERROR: that open brace { should be on the previous line
#6013: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29687:
+         if (Field_op2_Slot_inst_get (insn) == 15)
+           {

ERROR: suspect code indent for conditional statements (10, 14)
#6013: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29687:
+         if (Field_op2_Slot_inst_get (insn) == 15)
+           {

ERROR: code indent should never use tabs
#6014: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29688:
+^I    {$

ERROR: code indent should never use tabs
#6015: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29689:
+^I      if (Field_r_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#6015: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29689:
+             if (Field_r_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#6016: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29690:
+^I^Ireturn OPCODE_LICT;$

ERROR: code indent should never use tabs
#6017: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29691:
+^I      if (Field_r_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#6017: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29691:
+             if (Field_r_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#6018: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29692:
+^I^Ireturn OPCODE_SICT;$

ERROR: code indent should never use tabs
#6019: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29693:
+^I      if (Field_r_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#6019: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29693:
+             if (Field_r_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#6020: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29694:
+^I^Ireturn OPCODE_LICW;$

ERROR: code indent should never use tabs
#6021: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29695:
+^I      if (Field_r_Slot_inst_get (insn) == 3)$

ERROR: braces {} are necessary for all arms of this statement
#6021: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29695:
+             if (Field_r_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#6022: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29696:
+^I^Ireturn OPCODE_SICW;$

ERROR: code indent should never use tabs
#6023: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29697:
+^I      if (Field_r_Slot_inst_get (insn) == 8)$

ERROR: braces {} are necessary for all arms of this statement
#6023: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29697:
+             if (Field_r_Slot_inst_get (insn) == 8)
[...]

ERROR: code indent should never use tabs
#6024: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29698:
+^I^Ireturn OPCODE_LDCT;$

ERROR: code indent should never use tabs
#6025: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29699:
+^I      if (Field_r_Slot_inst_get (insn) == 9)$

ERROR: braces {} are necessary for all arms of this statement
#6025: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29699:
+             if (Field_r_Slot_inst_get (insn) == 9)
[...]

ERROR: code indent should never use tabs
#6026: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29700:
+^I^Ireturn OPCODE_SDCT;$

ERROR: code indent should never use tabs
#6027: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29701:
+^I      if (Field_r_Slot_inst_get (insn) == 14 &&$

ERROR: code indent should never use tabs
#6028: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29702:
+^I^I  Field_t_Slot_inst_get (insn) == 0)$

ERROR: code indent should never use tabs
#6029: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29703:
+^I^Ireturn OPCODE_RFDO;$

ERROR: code indent should never use tabs
#6030: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29704:
+^I      if (Field_r_Slot_inst_get (insn) == 14 &&$

ERROR: code indent should never use tabs
#6031: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29705:
+^I^I  Field_t_Slot_inst_get (insn) == 1)$

ERROR: code indent should never use tabs
#6032: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29706:
+^I^Ireturn OPCODE_RFDD;$

ERROR: code indent should never use tabs
#6033: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29707:
+^I      if (Field_r_Slot_inst_get (insn) == 15)$

ERROR: braces {} are necessary for all arms of this statement
#6033: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29707:
+             if (Field_r_Slot_inst_get (insn) == 15)
[...]

ERROR: code indent should never use tabs
#6034: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29708:
+^I^Ireturn OPCODE_LDPTE;$

ERROR: suspect code indent for conditional statements (6, 10)
#6335: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29711:
+      if (Field_op1_Slot_inst_get (insn) == 2)
        {

ERROR: code indent should never use tabs
#6357: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29713:
+^I  if (Field_op2_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#6357: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29713:
+         if (Field_op2_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#6358: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29714:
+^I    return OPCODE_ANDB;$

ERROR: code indent should never use tabs
#6359: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29715:
+^I  if (Field_op2_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#6359: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29715:
+         if (Field_op2_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#6360: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29716:
+^I    return OPCODE_ANDBC;$

ERROR: code indent should never use tabs
#6361: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29717:
+^I  if (Field_op2_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#6361: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29717:
+         if (Field_op2_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#6362: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29718:
+^I    return OPCODE_ORB;$

ERROR: code indent should never use tabs
#6363: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29719:
+^I  if (Field_op2_Slot_inst_get (insn) == 3)$

ERROR: braces {} are necessary for all arms of this statement
#6363: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29719:
+         if (Field_op2_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#6364: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29720:
+^I    return OPCODE_ORBC;$

ERROR: code indent should never use tabs
#6365: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29721:
+^I  if (Field_op2_Slot_inst_get (insn) == 4)$

ERROR: braces {} are necessary for all arms of this statement
#6365: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29721:
+         if (Field_op2_Slot_inst_get (insn) == 4)
[...]

ERROR: code indent should never use tabs
#6366: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29722:
+^I    return OPCODE_XORB;$

ERROR: code indent should never use tabs
#6367: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29723:
+^I  if (Field_op2_Slot_inst_get (insn) == 8)$

ERROR: braces {} are necessary for all arms of this statement
#6367: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29723:
+         if (Field_op2_Slot_inst_get (insn) == 8)
[...]

ERROR: code indent should never use tabs
#6368: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29724:
+^I    return OPCODE_MULL;$

ERROR: suspect code indent for conditional statements (6, 10)
#6371: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29726:
+      if (Field_op1_Slot_inst_get (insn) == 3)
        {

ERROR: code indent should never use tabs
#6405: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29728:
+^I  if (Field_op2_Slot_inst_get (insn) == 0)$

ERROR: that open brace { should be on the previous line
#6405: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29728:
+         if (Field_op2_Slot_inst_get (insn) == 0)
+           {

ERROR: suspect code indent for conditional statements (10, 14)
#6405: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29728:
+         if (Field_op2_Slot_inst_get (insn) == 0)
+           {

ERROR: code indent should never use tabs
#6406: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29729:
+^I    {$

ERROR: code indent should never use tabs
#6407: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29730:
+^I      if (Field_sr_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#6407: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29730:
+             if (Field_sr_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#6408: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29731:
+^I^Ireturn OPCODE_RSR_LBEG;$

ERROR: code indent should never use tabs
#6409: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29732:
+^I      if (Field_sr_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#6409: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29732:
+             if (Field_sr_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#6410: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29733:
+^I^Ireturn OPCODE_RSR_LEND;$

ERROR: code indent should never use tabs
#6411: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29734:
+^I      if (Field_sr_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#6411: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29734:
+             if (Field_sr_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#6412: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29735:
+^I^Ireturn OPCODE_RSR_LCOUNT;$

ERROR: code indent should never use tabs
#6413: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29736:
+^I      if (Field_sr_Slot_inst_get (insn) == 3)$

ERROR: braces {} are necessary for all arms of this statement
#6413: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29736:
+             if (Field_sr_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#6414: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29737:
+^I^Ireturn OPCODE_RSR_SAR;$

ERROR: code indent should never use tabs
#6415: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29738:
+^I      if (Field_sr_Slot_inst_get (insn) == 4)$

ERROR: braces {} are necessary for all arms of this statement
#6415: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29738:
+             if (Field_sr_Slot_inst_get (insn) == 4)
[...]

ERROR: code indent should never use tabs
#6416: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29739:
+^I^Ireturn OPCODE_RSR_BR;$

ERROR: code indent should never use tabs
#6417: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29740:
+^I      if (Field_sr_Slot_inst_get (insn) == 5)$

ERROR: braces {} are necessary for all arms of this statement
#6417: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29740:
+             if (Field_sr_Slot_inst_get (insn) == 5)
[...]

ERROR: code indent should never use tabs
#6418: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29741:
+^I^Ireturn OPCODE_RSR_LITBASE;$

ERROR: code indent should never use tabs
#6419: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29742:
+^I      if (Field_sr_Slot_inst_get (insn) == 12)$

ERROR: braces {} are necessary for all arms of this statement
#6419: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29742:
+             if (Field_sr_Slot_inst_get (insn) == 12)
[...]

ERROR: code indent should never use tabs
#6420: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29743:
+^I^Ireturn OPCODE_RSR_SCOMPARE1;$

ERROR: code indent should never use tabs
#6421: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29744:
+^I      if (Field_sr_Slot_inst_get (insn) == 72)$

ERROR: braces {} are necessary for all arms of this statement
#6421: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29744:
+             if (Field_sr_Slot_inst_get (insn) == 72)
[...]

ERROR: code indent should never use tabs
#6422: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29745:
+^I^Ireturn OPCODE_RSR_WINDOWBASE;$

ERROR: code indent should never use tabs
#6423: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29746:
+^I      if (Field_sr_Slot_inst_get (insn) == 73)$

ERROR: braces {} are necessary for all arms of this statement
#6423: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29746:
+             if (Field_sr_Slot_inst_get (insn) == 73)
[...]

ERROR: code indent should never use tabs
#6424: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29747:
+^I^Ireturn OPCODE_RSR_WINDOWSTART;$

ERROR: code indent should never use tabs
#6425: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29748:
+^I      if (Field_sr_Slot_inst_get (insn) == 83)$

ERROR: braces {} are necessary for all arms of this statement
#6425: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29748:
+             if (Field_sr_Slot_inst_get (insn) == 83)
[...]

ERROR: code indent should never use tabs
#6426: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29749:
+^I^Ireturn OPCODE_RSR_PTEVADDR;$

ERROR: code indent should never use tabs
#6427: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29750:
+^I      if (Field_sr_Slot_inst_get (insn) == 90)$

ERROR: braces {} are necessary for all arms of this statement
#6427: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29750:
+             if (Field_sr_Slot_inst_get (insn) == 90)
[...]

ERROR: code indent should never use tabs
#6428: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29751:
+^I^Ireturn OPCODE_RSR_RASID;$

ERROR: code indent should never use tabs
#6429: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29752:
+^I      if (Field_sr_Slot_inst_get (insn) == 91)$

ERROR: braces {} are necessary for all arms of this statement
#6429: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29752:
+             if (Field_sr_Slot_inst_get (insn) == 91)
[...]

ERROR: code indent should never use tabs
#6430: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29753:
+^I^Ireturn OPCODE_RSR_ITLBCFG;$

ERROR: code indent should never use tabs
#6431: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29754:
+^I      if (Field_sr_Slot_inst_get (insn) == 92)$

ERROR: braces {} are necessary for all arms of this statement
#6431: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29754:
+             if (Field_sr_Slot_inst_get (insn) == 92)
[...]

ERROR: code indent should never use tabs
#6432: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29755:
+^I^Ireturn OPCODE_RSR_DTLBCFG;$

ERROR: code indent should never use tabs
#6433: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29756:
+^I      if (Field_sr_Slot_inst_get (insn) == 99)$

ERROR: braces {} are necessary for all arms of this statement
#6433: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29756:
+             if (Field_sr_Slot_inst_get (insn) == 99)
[...]

ERROR: code indent should never use tabs
#6434: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29757:
+^I^Ireturn OPCODE_RSR_ATOMCTL;$

ERROR: code indent should never use tabs
#6435: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29758:
+^I      if (Field_sr_Slot_inst_get (insn) == 104)$

ERROR: braces {} are necessary for all arms of this statement
#6435: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29758:
+             if (Field_sr_Slot_inst_get (insn) == 104)
[...]

ERROR: code indent should never use tabs
#6436: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29759:
+^I^Ireturn OPCODE_RSR_DDR;$

ERROR: code indent should never use tabs
#6437: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29760:
+^I      if (Field_sr_Slot_inst_get (insn) == 176)$

ERROR: braces {} are necessary for all arms of this statement
#6437: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29760:
+             if (Field_sr_Slot_inst_get (insn) == 176)
[...]

ERROR: code indent should never use tabs
#6438: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29761:
+^I^Ireturn OPCODE_RSR_CONFIGID0;$

ERROR: code indent should never use tabs
#6439: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29762:
+^I      if (Field_sr_Slot_inst_get (insn) == 177)$

ERROR: braces {} are necessary for all arms of this statement
#6439: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29762:
+             if (Field_sr_Slot_inst_get (insn) == 177)
[...]

ERROR: code indent should never use tabs
#6440: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29763:
+^I^Ireturn OPCODE_RSR_EPC1;$

ERROR: code indent should never use tabs
#6441: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29764:
+^I      if (Field_sr_Slot_inst_get (insn) == 178)$

ERROR: braces {} are necessary for all arms of this statement
#6441: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29764:
+             if (Field_sr_Slot_inst_get (insn) == 178)
[...]

ERROR: code indent should never use tabs
#6442: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29765:
+^I^Ireturn OPCODE_RSR_EPC2;$

ERROR: code indent should never use tabs
#6443: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29766:
+^I      if (Field_sr_Slot_inst_get (insn) == 192)$

ERROR: braces {} are necessary for all arms of this statement
#6443: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29766:
+             if (Field_sr_Slot_inst_get (insn) == 192)
[...]

ERROR: code indent should never use tabs
#6444: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29767:
+^I^Ireturn OPCODE_RSR_DEPC;$

ERROR: code indent should never use tabs
#6445: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29768:
+^I      if (Field_sr_Slot_inst_get (insn) == 194)$

ERROR: braces {} are necessary for all arms of this statement
#6445: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29768:
+             if (Field_sr_Slot_inst_get (insn) == 194)
[...]

ERROR: code indent should never use tabs
#6446: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29769:
+^I^Ireturn OPCODE_RSR_EPS2;$

ERROR: code indent should never use tabs
#6447: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29770:
+^I      if (Field_sr_Slot_inst_get (insn) == 208)$

ERROR: braces {} are necessary for all arms of this statement
#6447: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29770:
+             if (Field_sr_Slot_inst_get (insn) == 208)
[...]

ERROR: code indent should never use tabs
#6448: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29771:
+^I^Ireturn OPCODE_RSR_CONFIGID1;$

ERROR: code indent should never use tabs
#6449: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29772:
+^I      if (Field_sr_Slot_inst_get (insn) == 209)$

ERROR: braces {} are necessary for all arms of this statement
#6449: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29772:
+             if (Field_sr_Slot_inst_get (insn) == 209)
[...]

ERROR: code indent should never use tabs
#6450: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29773:
+^I^Ireturn OPCODE_RSR_EXCSAVE1;$

ERROR: code indent should never use tabs
#6451: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29774:
+^I      if (Field_sr_Slot_inst_get (insn) == 210)$

ERROR: braces {} are necessary for all arms of this statement
#6451: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29774:
+             if (Field_sr_Slot_inst_get (insn) == 210)
[...]

ERROR: code indent should never use tabs
#6452: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29775:
+^I^Ireturn OPCODE_RSR_EXCSAVE2;$

ERROR: code indent should never use tabs
#6453: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29776:
+^I      if (Field_sr_Slot_inst_get (insn) == 224)$

ERROR: braces {} are necessary for all arms of this statement
#6453: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29776:
+             if (Field_sr_Slot_inst_get (insn) == 224)
[...]

ERROR: code indent should never use tabs
#6454: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29777:
+^I^Ireturn OPCODE_RSR_CPENABLE;$

ERROR: code indent should never use tabs
#6455: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29778:
+^I      if (Field_sr_Slot_inst_get (insn) == 226)$

ERROR: braces {} are necessary for all arms of this statement
#6455: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29778:
+             if (Field_sr_Slot_inst_get (insn) == 226)
[...]

ERROR: code indent should never use tabs
#6456: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29779:
+^I^Ireturn OPCODE_RSR_INTERRUPT;$

ERROR: code indent should never use tabs
#6457: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29780:
+^I      if (Field_sr_Slot_inst_get (insn) == 228)$

ERROR: braces {} are necessary for all arms of this statement
#6457: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29780:
+             if (Field_sr_Slot_inst_get (insn) == 228)
[...]

ERROR: code indent should never use tabs
#6458: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29781:
+^I^Ireturn OPCODE_RSR_INTENABLE;$

ERROR: code indent should never use tabs
#6459: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29782:
+^I      if (Field_sr_Slot_inst_get (insn) == 230)$

ERROR: braces {} are necessary for all arms of this statement
#6459: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29782:
+             if (Field_sr_Slot_inst_get (insn) == 230)
[...]

ERROR: code indent should never use tabs
#6460: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29783:
+^I^Ireturn OPCODE_RSR_PS;$

ERROR: code indent should never use tabs
#6461: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29784:
+^I      if (Field_sr_Slot_inst_get (insn) == 231)$

ERROR: braces {} are necessary for all arms of this statement
#6461: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29784:
+             if (Field_sr_Slot_inst_get (insn) == 231)
[...]

ERROR: code indent should never use tabs
#6462: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29785:
+^I^Ireturn OPCODE_RSR_VECBASE;$

ERROR: code indent should never use tabs
#6463: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29786:
+^I      if (Field_sr_Slot_inst_get (insn) == 232)$

ERROR: braces {} are necessary for all arms of this statement
#6463: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29786:
+             if (Field_sr_Slot_inst_get (insn) == 232)
[...]

ERROR: code indent should never use tabs
#6464: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29787:
+^I^Ireturn OPCODE_RSR_EXCCAUSE;$

ERROR: code indent should never use tabs
#6465: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29788:
+^I      if (Field_sr_Slot_inst_get (insn) == 233)$

ERROR: braces {} are necessary for all arms of this statement
#6465: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29788:
+             if (Field_sr_Slot_inst_get (insn) == 233)
[...]

ERROR: code indent should never use tabs
#6466: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29789:
+^I^Ireturn OPCODE_RSR_DEBUGCAUSE;$

ERROR: code indent should never use tabs
#6467: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29790:
+^I      if (Field_sr_Slot_inst_get (insn) == 234)$

ERROR: braces {} are necessary for all arms of this statement
#6467: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29790:
+             if (Field_sr_Slot_inst_get (insn) == 234)
[...]

ERROR: code indent should never use tabs
#6468: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29791:
+^I^Ireturn OPCODE_RSR_CCOUNT;$

ERROR: code indent should never use tabs
#6469: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29792:
+^I      if (Field_sr_Slot_inst_get (insn) == 235)$

ERROR: braces {} are necessary for all arms of this statement
#6469: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29792:
+             if (Field_sr_Slot_inst_get (insn) == 235)
[...]

ERROR: code indent should never use tabs
#6470: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29793:
+^I^Ireturn OPCODE_RSR_PRID;$

ERROR: code indent should never use tabs
#6471: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29794:
+^I      if (Field_sr_Slot_inst_get (insn) == 236)$

ERROR: braces {} are necessary for all arms of this statement
#6471: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29794:
+             if (Field_sr_Slot_inst_get (insn) == 236)
[...]

ERROR: code indent should never use tabs
#6472: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29795:
+^I^Ireturn OPCODE_RSR_ICOUNT;$

ERROR: code indent should never use tabs
#6473: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29796:
+^I      if (Field_sr_Slot_inst_get (insn) == 237)$

ERROR: braces {} are necessary for all arms of this statement
#6473: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29796:
+             if (Field_sr_Slot_inst_get (insn) == 237)
[...]

ERROR: code indent should never use tabs
#6474: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29797:
+^I^Ireturn OPCODE_RSR_ICOUNTLEVEL;$

ERROR: code indent should never use tabs
#6475: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29798:
+^I      if (Field_sr_Slot_inst_get (insn) == 238)$

ERROR: braces {} are necessary for all arms of this statement
#6475: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29798:
+             if (Field_sr_Slot_inst_get (insn) == 238)
[...]

ERROR: code indent should never use tabs
#6476: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29799:
+^I^Ireturn OPCODE_RSR_EXCVADDR;$

ERROR: code indent should never use tabs
#6477: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29800:
+^I      if (Field_sr_Slot_inst_get (insn) == 240)$

ERROR: braces {} are necessary for all arms of this statement
#6477: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29800:
+             if (Field_sr_Slot_inst_get (insn) == 240)
[...]

ERROR: code indent should never use tabs
#6478: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29801:
+^I^Ireturn OPCODE_RSR_CCOMPARE0;$

ERROR: code indent should never use tabs
#6479: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29802:
+^I      if (Field_sr_Slot_inst_get (insn) == 241)$

ERROR: braces {} are necessary for all arms of this statement
#6479: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29802:
+             if (Field_sr_Slot_inst_get (insn) == 241)
[...]

ERROR: code indent should never use tabs
#6480: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29803:
+^I^Ireturn OPCODE_RSR_CCOMPARE1;$

ERROR: code indent should never use tabs
#6481: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29804:
+^I      if (Field_sr_Slot_inst_get (insn) == 244)$

ERROR: braces {} are necessary for all arms of this statement
#6481: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29804:
+             if (Field_sr_Slot_inst_get (insn) == 244)
[...]

ERROR: code indent should never use tabs
#6482: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29805:
+^I^Ireturn OPCODE_RSR_MISC0;$

ERROR: code indent should never use tabs
#6483: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29806:
+^I      if (Field_sr_Slot_inst_get (insn) == 245)$

ERROR: braces {} are necessary for all arms of this statement
#6483: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29806:
+             if (Field_sr_Slot_inst_get (insn) == 245)
[...]

ERROR: code indent should never use tabs
#6484: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29807:
+^I^Ireturn OPCODE_RSR_MISC1;$

ERROR: code indent should never use tabs
#6485: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29808:
+^I    }$

ERROR: code indent should never use tabs
#6486: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29809:
+^I  if (Field_op2_Slot_inst_get (insn) == 1)$

ERROR: that open brace { should be on the previous line
#6486: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29809:
+         if (Field_op2_Slot_inst_get (insn) == 1)
+           {

ERROR: suspect code indent for conditional statements (10, 14)
#6486: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29809:
+         if (Field_op2_Slot_inst_get (insn) == 1)
+           {

ERROR: code indent should never use tabs
#6487: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29810:
+^I    {$

ERROR: code indent should never use tabs
#6488: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29811:
+^I      if (Field_sr_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#6488: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29811:
+             if (Field_sr_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#6489: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29812:
+^I^Ireturn OPCODE_WSR_LBEG;$

ERROR: code indent should never use tabs
#6490: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29813:
+^I      if (Field_sr_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#6490: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29813:
+             if (Field_sr_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#6491: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29814:
+^I^Ireturn OPCODE_WSR_LEND;$

ERROR: code indent should never use tabs
#6492: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29815:
+^I      if (Field_sr_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#6492: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29815:
+             if (Field_sr_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#6493: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29816:
+^I^Ireturn OPCODE_WSR_LCOUNT;$

ERROR: code indent should never use tabs
#6494: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29817:
+^I      if (Field_sr_Slot_inst_get (insn) == 3)$

ERROR: braces {} are necessary for all arms of this statement
#6494: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29817:
+             if (Field_sr_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#6495: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29818:
+^I^Ireturn OPCODE_WSR_SAR;$

ERROR: code indent should never use tabs
#6496: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29819:
+^I      if (Field_sr_Slot_inst_get (insn) == 4)$

ERROR: braces {} are necessary for all arms of this statement
#6496: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29819:
+             if (Field_sr_Slot_inst_get (insn) == 4)
[...]

ERROR: code indent should never use tabs
#6497: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29820:
+^I^Ireturn OPCODE_WSR_BR;$

ERROR: code indent should never use tabs
#6498: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29821:
+^I      if (Field_sr_Slot_inst_get (insn) == 5)$

ERROR: braces {} are necessary for all arms of this statement
#6498: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29821:
+             if (Field_sr_Slot_inst_get (insn) == 5)
[...]

ERROR: code indent should never use tabs
#6499: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29822:
+^I^Ireturn OPCODE_WSR_LITBASE;$

ERROR: code indent should never use tabs
#6500: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29823:
+^I      if (Field_sr_Slot_inst_get (insn) == 12)$

ERROR: braces {} are necessary for all arms of this statement
#6500: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29823:
+             if (Field_sr_Slot_inst_get (insn) == 12)
[...]

ERROR: code indent should never use tabs
#6501: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29824:
+^I^Ireturn OPCODE_WSR_SCOMPARE1;$

ERROR: code indent should never use tabs
#6502: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29825:
+^I      if (Field_sr_Slot_inst_get (insn) == 72)$

ERROR: braces {} are necessary for all arms of this statement
#6502: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29825:
+             if (Field_sr_Slot_inst_get (insn) == 72)
[...]

ERROR: code indent should never use tabs
#6503: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29826:
+^I^Ireturn OPCODE_WSR_WINDOWBASE;$

ERROR: code indent should never use tabs
#6504: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29827:
+^I      if (Field_sr_Slot_inst_get (insn) == 73)$

ERROR: braces {} are necessary for all arms of this statement
#6504: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29827:
+             if (Field_sr_Slot_inst_get (insn) == 73)
[...]

ERROR: code indent should never use tabs
#6505: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29828:
+^I^Ireturn OPCODE_WSR_WINDOWSTART;$

ERROR: code indent should never use tabs
#6506: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29829:
+^I      if (Field_sr_Slot_inst_get (insn) == 83)$

ERROR: braces {} are necessary for all arms of this statement
#6506: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29829:
+             if (Field_sr_Slot_inst_get (insn) == 83)
[...]

ERROR: code indent should never use tabs
#6507: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29830:
+^I^Ireturn OPCODE_WSR_PTEVADDR;$

ERROR: code indent should never use tabs
#6508: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29831:
+^I      if (Field_sr_Slot_inst_get (insn) == 90)$

ERROR: braces {} are necessary for all arms of this statement
#6508: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29831:
+             if (Field_sr_Slot_inst_get (insn) == 90)
[...]

ERROR: code indent should never use tabs
#6509: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29832:
+^I^Ireturn OPCODE_WSR_RASID;$

ERROR: code indent should never use tabs
#6510: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29833:
+^I      if (Field_sr_Slot_inst_get (insn) == 91)$

ERROR: braces {} are necessary for all arms of this statement
#6510: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29833:
+             if (Field_sr_Slot_inst_get (insn) == 91)
[...]

ERROR: code indent should never use tabs
#6511: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29834:
+^I^Ireturn OPCODE_WSR_ITLBCFG;$

ERROR: code indent should never use tabs
#6512: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29835:
+^I      if (Field_sr_Slot_inst_get (insn) == 92)$

ERROR: braces {} are necessary for all arms of this statement
#6512: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29835:
+             if (Field_sr_Slot_inst_get (insn) == 92)
[...]

ERROR: code indent should never use tabs
#6513: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29836:
+^I^Ireturn OPCODE_WSR_DTLBCFG;$

ERROR: code indent should never use tabs
#6514: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29837:
+^I      if (Field_sr_Slot_inst_get (insn) == 99)$

ERROR: braces {} are necessary for all arms of this statement
#6514: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29837:
+             if (Field_sr_Slot_inst_get (insn) == 99)
[...]

ERROR: code indent should never use tabs
#6515: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29838:
+^I^Ireturn OPCODE_WSR_ATOMCTL;$

ERROR: code indent should never use tabs
#6516: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29839:
+^I      if (Field_sr_Slot_inst_get (insn) == 104)$

ERROR: braces {} are necessary for all arms of this statement
#6516: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29839:
+             if (Field_sr_Slot_inst_get (insn) == 104)
[...]

ERROR: code indent should never use tabs
#6517: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29840:
+^I^Ireturn OPCODE_WSR_DDR;$

ERROR: code indent should never use tabs
#6518: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29841:
+^I      if (Field_sr_Slot_inst_get (insn) == 176)$

ERROR: braces {} are necessary for all arms of this statement
#6518: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29841:
+             if (Field_sr_Slot_inst_get (insn) == 176)
[...]

ERROR: code indent should never use tabs
#6519: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29842:
+^I^Ireturn OPCODE_WSR_CONFIGID0;$

ERROR: code indent should never use tabs
#6520: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29843:
+^I      if (Field_sr_Slot_inst_get (insn) == 177)$

ERROR: braces {} are necessary for all arms of this statement
#6520: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29843:
+             if (Field_sr_Slot_inst_get (insn) == 177)
[...]

ERROR: code indent should never use tabs
#6521: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29844:
+^I^Ireturn OPCODE_WSR_EPC1;$

ERROR: code indent should never use tabs
#6522: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29845:
+^I      if (Field_sr_Slot_inst_get (insn) == 178)$

ERROR: braces {} are necessary for all arms of this statement
#6522: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29845:
+             if (Field_sr_Slot_inst_get (insn) == 178)
[...]

ERROR: code indent should never use tabs
#6523: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29846:
+^I^Ireturn OPCODE_WSR_EPC2;$

ERROR: code indent should never use tabs
#6524: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29847:
+^I      if (Field_sr_Slot_inst_get (insn) == 192)$

ERROR: braces {} are necessary for all arms of this statement
#6524: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29847:
+             if (Field_sr_Slot_inst_get (insn) == 192)
[...]

ERROR: code indent should never use tabs
#6525: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29848:
+^I^Ireturn OPCODE_WSR_DEPC;$

ERROR: code indent should never use tabs
#6526: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29849:
+^I      if (Field_sr_Slot_inst_get (insn) == 194)$

ERROR: braces {} are necessary for all arms of this statement
#6526: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29849:
+             if (Field_sr_Slot_inst_get (insn) == 194)
[...]

ERROR: code indent should never use tabs
#6527: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29850:
+^I^Ireturn OPCODE_WSR_EPS2;$

ERROR: code indent should never use tabs
#6528: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29851:
+^I      if (Field_sr_Slot_inst_get (insn) == 209)$

ERROR: braces {} are necessary for all arms of this statement
#6528: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29851:
+             if (Field_sr_Slot_inst_get (insn) == 209)
[...]

ERROR: code indent should never use tabs
#6529: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29852:
+^I^Ireturn OPCODE_WSR_EXCSAVE1;$

ERROR: code indent should never use tabs
#6530: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29853:
+^I      if (Field_sr_Slot_inst_get (insn) == 210)$

ERROR: braces {} are necessary for all arms of this statement
#6530: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29853:
+             if (Field_sr_Slot_inst_get (insn) == 210)
[...]

ERROR: code indent should never use tabs
#6531: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29854:
+^I^Ireturn OPCODE_WSR_EXCSAVE2;$

ERROR: code indent should never use tabs
#6532: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29855:
+^I      if (Field_sr_Slot_inst_get (insn) == 224)$

ERROR: braces {} are necessary for all arms of this statement
#6532: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29855:
+             if (Field_sr_Slot_inst_get (insn) == 224)
[...]

ERROR: code indent should never use tabs
#6533: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29856:
+^I^Ireturn OPCODE_WSR_CPENABLE;$

ERROR: code indent should never use tabs
#6534: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29857:
+^I      if (Field_sr_Slot_inst_get (insn) == 226)$

ERROR: braces {} are necessary for all arms of this statement
#6534: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29857:
+             if (Field_sr_Slot_inst_get (insn) == 226)
[...]

ERROR: code indent should never use tabs
#6535: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29858:
+^I^Ireturn OPCODE_WSR_INTSET;$

ERROR: code indent should never use tabs
#6536: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29859:
+^I      if (Field_sr_Slot_inst_get (insn) == 227)$

ERROR: braces {} are necessary for all arms of this statement
#6536: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29859:
+             if (Field_sr_Slot_inst_get (insn) == 227)
[...]

ERROR: code indent should never use tabs
#6537: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29860:
+^I^Ireturn OPCODE_WSR_INTCLEAR;$

ERROR: code indent should never use tabs
#6538: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29861:
+^I      if (Field_sr_Slot_inst_get (insn) == 228)$

ERROR: braces {} are necessary for all arms of this statement
#6538: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29861:
+             if (Field_sr_Slot_inst_get (insn) == 228)
[...]

ERROR: code indent should never use tabs
#6539: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29862:
+^I^Ireturn OPCODE_WSR_INTENABLE;$

ERROR: code indent should never use tabs
#6540: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29863:
+^I      if (Field_sr_Slot_inst_get (insn) == 230)$

ERROR: braces {} are necessary for all arms of this statement
#6540: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29863:
+             if (Field_sr_Slot_inst_get (insn) == 230)
[...]

ERROR: code indent should never use tabs
#6541: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29864:
+^I^Ireturn OPCODE_WSR_PS;$

ERROR: code indent should never use tabs
#6542: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29865:
+^I      if (Field_sr_Slot_inst_get (insn) == 231)$

ERROR: braces {} are necessary for all arms of this statement
#6542: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29865:
+             if (Field_sr_Slot_inst_get (insn) == 231)
[...]

ERROR: code indent should never use tabs
#6543: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29866:
+^I^Ireturn OPCODE_WSR_VECBASE;$

ERROR: code indent should never use tabs
#6544: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29867:
+^I      if (Field_sr_Slot_inst_get (insn) == 232)$

ERROR: braces {} are necessary for all arms of this statement
#6544: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29867:
+             if (Field_sr_Slot_inst_get (insn) == 232)
[...]

ERROR: code indent should never use tabs
#6545: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29868:
+^I^Ireturn OPCODE_WSR_EXCCAUSE;$

ERROR: code indent should never use tabs
#6546: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29869:
+^I      if (Field_sr_Slot_inst_get (insn) == 233)$

ERROR: braces {} are necessary for all arms of this statement
#6546: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29869:
+             if (Field_sr_Slot_inst_get (insn) == 233)
[...]

ERROR: code indent should never use tabs
#6547: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29870:
+^I^Ireturn OPCODE_WSR_DEBUGCAUSE;$

ERROR: code indent should never use tabs
#6548: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29871:
+^I      if (Field_sr_Slot_inst_get (insn) == 234)$

ERROR: braces {} are necessary for all arms of this statement
#6548: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29871:
+             if (Field_sr_Slot_inst_get (insn) == 234)
[...]

ERROR: code indent should never use tabs
#6549: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29872:
+^I^Ireturn OPCODE_WSR_CCOUNT;$

ERROR: code indent should never use tabs
#6550: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29873:
+^I      if (Field_sr_Slot_inst_get (insn) == 236)$

ERROR: braces {} are necessary for all arms of this statement
#6550: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29873:
+             if (Field_sr_Slot_inst_get (insn) == 236)
[...]

ERROR: code indent should never use tabs
#6551: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29874:
+^I^Ireturn OPCODE_WSR_ICOUNT;$

ERROR: code indent should never use tabs
#6552: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29875:
+^I      if (Field_sr_Slot_inst_get (insn) == 237)$

ERROR: braces {} are necessary for all arms of this statement
#6552: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29875:
+             if (Field_sr_Slot_inst_get (insn) == 237)
[...]

ERROR: code indent should never use tabs
#6553: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29876:
+^I^Ireturn OPCODE_WSR_ICOUNTLEVEL;$

ERROR: code indent should never use tabs
#6554: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29877:
+^I      if (Field_sr_Slot_inst_get (insn) == 238)$

ERROR: braces {} are necessary for all arms of this statement
#6554: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29877:
+             if (Field_sr_Slot_inst_get (insn) == 238)
[...]

ERROR: code indent should never use tabs
#6555: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29878:
+^I^Ireturn OPCODE_WSR_EXCVADDR;$

ERROR: code indent should never use tabs
#6556: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29879:
+^I      if (Field_sr_Slot_inst_get (insn) == 240)$

ERROR: braces {} are necessary for all arms of this statement
#6556: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29879:
+             if (Field_sr_Slot_inst_get (insn) == 240)
[...]

ERROR: code indent should never use tabs
#6557: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29880:
+^I^Ireturn OPCODE_WSR_CCOMPARE0;$

ERROR: code indent should never use tabs
#6558: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29881:
+^I      if (Field_sr_Slot_inst_get (insn) == 241)$

ERROR: braces {} are necessary for all arms of this statement
#6558: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29881:
+             if (Field_sr_Slot_inst_get (insn) == 241)
[...]

ERROR: code indent should never use tabs
#6559: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29882:
+^I^Ireturn OPCODE_WSR_CCOMPARE1;$

ERROR: code indent should never use tabs
#6560: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29883:
+^I      if (Field_sr_Slot_inst_get (insn) == 244)$

ERROR: braces {} are necessary for all arms of this statement
#6560: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29883:
+             if (Field_sr_Slot_inst_get (insn) == 244)
[...]

ERROR: code indent should never use tabs
#6561: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29884:
+^I^Ireturn OPCODE_WSR_MISC0;$

ERROR: code indent should never use tabs
#6562: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29885:
+^I      if (Field_sr_Slot_inst_get (insn) == 245)$

ERROR: braces {} are necessary for all arms of this statement
#6562: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29885:
+             if (Field_sr_Slot_inst_get (insn) == 245)
[...]

ERROR: code indent should never use tabs
#6563: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29886:
+^I^Ireturn OPCODE_WSR_MISC1;$

ERROR: code indent should never use tabs
#6564: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29887:
+^I    }$

ERROR: code indent should never use tabs
#6565: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29888:
+^I  if (Field_op2_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#6565: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29888:
+         if (Field_op2_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#6566: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29889:
+^I    return OPCODE_SEXT;$

ERROR: code indent should never use tabs
#6567: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29890:
+^I  if (Field_op2_Slot_inst_get (insn) == 3)$

ERROR: braces {} are necessary for all arms of this statement
#6567: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29890:
+         if (Field_op2_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#6568: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29891:
+^I    return OPCODE_CLAMPS;$

ERROR: code indent should never use tabs
#6569: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29892:
+^I  if (Field_op2_Slot_inst_get (insn) == 4)$

ERROR: braces {} are necessary for all arms of this statement
#6569: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29892:
+         if (Field_op2_Slot_inst_get (insn) == 4)
[...]

ERROR: code indent should never use tabs
#6570: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29893:
+^I    return OPCODE_MIN;$

ERROR: code indent should never use tabs
#6571: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29894:
+^I  if (Field_op2_Slot_inst_get (insn) == 5)$

ERROR: braces {} are necessary for all arms of this statement
#6571: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29894:
+         if (Field_op2_Slot_inst_get (insn) == 5)
[...]

ERROR: code indent should never use tabs
#6572: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29895:
+^I    return OPCODE_MAX;$

ERROR: code indent should never use tabs
#6573: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29896:
+^I  if (Field_op2_Slot_inst_get (insn) == 6)$

ERROR: braces {} are necessary for all arms of this statement
#6573: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29896:
+         if (Field_op2_Slot_inst_get (insn) == 6)
[...]

ERROR: code indent should never use tabs
#6574: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29897:
+^I    return OPCODE_MINU;$

ERROR: code indent should never use tabs
#6575: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29898:
+^I  if (Field_op2_Slot_inst_get (insn) == 7)$

ERROR: braces {} are necessary for all arms of this statement
#6575: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29898:
+         if (Field_op2_Slot_inst_get (insn) == 7)
[...]

ERROR: code indent should never use tabs
#6576: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29899:
+^I    return OPCODE_MAXU;$

ERROR: code indent should never use tabs
#6577: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29900:
+^I  if (Field_op2_Slot_inst_get (insn) == 8)$

ERROR: braces {} are necessary for all arms of this statement
#6577: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29900:
+         if (Field_op2_Slot_inst_get (insn) == 8)
[...]

ERROR: code indent should never use tabs
#6578: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29901:
+^I    return OPCODE_MOVEQZ;$

ERROR: code indent should never use tabs
#6579: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29902:
+^I  if (Field_op2_Slot_inst_get (insn) == 9)$

ERROR: braces {} are necessary for all arms of this statement
#6579: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29902:
+         if (Field_op2_Slot_inst_get (insn) == 9)
[...]

ERROR: code indent should never use tabs
#6580: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29903:
+^I    return OPCODE_MOVNEZ;$

ERROR: code indent should never use tabs
#6594: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29905:
+^I    return OPCODE_MOVLTZ;$

ERROR: code indent should never use tabs
#6595: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29906:
+^I  if (Field_op2_Slot_inst_get (insn) == 11)$

ERROR: braces {} are necessary for all arms of this statement
#6595: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29906:
+         if (Field_op2_Slot_inst_get (insn) == 11)
[...]

ERROR: code indent should never use tabs
#6596: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29907:
+^I    return OPCODE_MOVGEZ;$

ERROR: code indent should never use tabs
#6597: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29908:
+^I  if (Field_op2_Slot_inst_get (insn) == 12)$

ERROR: braces {} are necessary for all arms of this statement
#6597: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29908:
+         if (Field_op2_Slot_inst_get (insn) == 12)
[...]

ERROR: code indent should never use tabs
#6598: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29909:
+^I    return OPCODE_MOVF;$

ERROR: code indent should never use tabs
#6599: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29910:
+^I  if (Field_op2_Slot_inst_get (insn) == 13)$

ERROR: braces {} are necessary for all arms of this statement
#6599: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29910:
+         if (Field_op2_Slot_inst_get (insn) == 13)
[...]

ERROR: code indent should never use tabs
#6600: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29911:
+^I    return OPCODE_MOVT;$

ERROR: code indent should never use tabs
#6601: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29912:
+^I  if (Field_op2_Slot_inst_get (insn) == 14)$

ERROR: that open brace { should be on the previous line
#6601: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29912:
+         if (Field_op2_Slot_inst_get (insn) == 14)
+           {

ERROR: suspect code indent for conditional statements (10, 14)
#6601: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29912:
+         if (Field_op2_Slot_inst_get (insn) == 14)
+           {

ERROR: code indent should never use tabs
#6602: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29913:
+^I    {$

ERROR: code indent should never use tabs
#6603: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29914:
+^I      if (Field_st_Slot_inst_get (insn) == 231)$

ERROR: braces {} are necessary for all arms of this statement
#6603: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29914:
+             if (Field_st_Slot_inst_get (insn) == 231)
[...]

ERROR: code indent should never use tabs
#6604: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29915:
+^I^Ireturn OPCODE_RUR_THREADPTR;$

ERROR: code indent should never use tabs
#6605: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29916:
+^I      if (Field_st_Slot_inst_get (insn) == 240)$

ERROR: braces {} are necessary for all arms of this statement
#6605: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29916:
+             if (Field_st_Slot_inst_get (insn) == 240)
[...]

ERROR: code indent should never use tabs
#6606: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29917:
+^I^Ireturn OPCODE_RUR_AE_OVF_SAR;$

ERROR: code indent should never use tabs
#6607: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29918:
+^I      if (Field_st_Slot_inst_get (insn) == 241)$

ERROR: braces {} are necessary for all arms of this statement
#6607: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29918:
+             if (Field_st_Slot_inst_get (insn) == 241)
[...]

ERROR: code indent should never use tabs
#6608: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29919:
+^I^Ireturn OPCODE_RUR_AE_BITHEAD;$

ERROR: code indent should never use tabs
#6609: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29920:
+^I      if (Field_st_Slot_inst_get (insn) == 242)$

ERROR: braces {} are necessary for all arms of this statement
#6609: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29920:
+             if (Field_st_Slot_inst_get (insn) == 242)
[...]

ERROR: code indent should never use tabs
#6610: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29921:
+^I^Ireturn OPCODE_RUR_AE_TS_FTS_BU_BP;$

ERROR: code indent should never use tabs
#6611: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29922:
+^I      if (Field_st_Slot_inst_get (insn) == 243)$

ERROR: braces {} are necessary for all arms of this statement
#6611: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29922:
+             if (Field_st_Slot_inst_get (insn) == 243)
[...]

ERROR: code indent should never use tabs
#6612: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29923:
+^I^Ireturn OPCODE_RUR_AE_SD_NO;$

ERROR: code indent should never use tabs
#6613: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29924:
+^I    }$

ERROR: code indent should never use tabs
#6614: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29925:
+^I  if (Field_op2_Slot_inst_get (insn) == 15)$

ERROR: that open brace { should be on the previous line
#6614: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29925:
+         if (Field_op2_Slot_inst_get (insn) == 15)
+           {

ERROR: suspect code indent for conditional statements (10, 14)
#6614: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29925:
+         if (Field_op2_Slot_inst_get (insn) == 15)
+           {

ERROR: code indent should never use tabs
#6615: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29926:
+^I    {$

ERROR: code indent should never use tabs
#6616: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29927:
+^I      if (Field_sr_Slot_inst_get (insn) == 231)$

ERROR: braces {} are necessary for all arms of this statement
#6616: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29927:
+             if (Field_sr_Slot_inst_get (insn) == 231)
[...]

ERROR: code indent should never use tabs
#6617: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29928:
+^I^Ireturn OPCODE_WUR_THREADPTR;$

ERROR: code indent should never use tabs
#6618: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29929:
+^I      if (Field_sr_Slot_inst_get (insn) == 240)$

ERROR: braces {} are necessary for all arms of this statement
#6618: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29929:
+             if (Field_sr_Slot_inst_get (insn) == 240)
[...]

ERROR: code indent should never use tabs
#6619: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29930:
+^I^Ireturn OPCODE_WUR_AE_OVF_SAR;$

ERROR: code indent should never use tabs
#6620: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29931:
+^I      if (Field_sr_Slot_inst_get (insn) == 241)$

ERROR: braces {} are necessary for all arms of this statement
#6620: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29931:
+             if (Field_sr_Slot_inst_get (insn) == 241)
[...]

ERROR: code indent should never use tabs
#6621: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29932:
+^I^Ireturn OPCODE_WUR_AE_BITHEAD;$

ERROR: code indent should never use tabs
#6622: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29933:
+^I      if (Field_sr_Slot_inst_get (insn) == 242)$

ERROR: braces {} are necessary for all arms of this statement
#6622: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29933:
+             if (Field_sr_Slot_inst_get (insn) == 242)
[...]

ERROR: code indent should never use tabs
#6623: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29934:
+^I^Ireturn OPCODE_WUR_AE_TS_FTS_BU_BP;$

ERROR: code indent should never use tabs
#6624: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29935:
+^I      if (Field_sr_Slot_inst_get (insn) == 243)$

ERROR: braces {} are necessary for all arms of this statement
#6624: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29935:
+             if (Field_sr_Slot_inst_get (insn) == 243)
[...]

ERROR: code indent should never use tabs
#6625: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29936:
+^I^Ireturn OPCODE_WUR_AE_SD_NO;$

ERROR: code indent should never use tabs
#6626: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29937:
+^I    }$

ERROR: code indent should never use tabs
#6630: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29940:
+^I   Field_op1_Slot_inst_get (insn) == 5))$

ERROR: code indent should never use tabs
#6631: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29941:
+^Ireturn OPCODE_EXTUI;$

ERROR: suspect code indent for conditional statements (6, 10)
#6632: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29942:
+      if (Field_op1_Slot_inst_get (insn) == 9)
        {

ERROR: code indent should never use tabs
#6714: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29944:
+^I  if (Field_op2_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#6714: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29944:
+         if (Field_op2_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#6715: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29945:
+^I    return OPCODE_L32E;$

ERROR: code indent should never use tabs
#6716: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29946:
+^I  if (Field_op2_Slot_inst_get (insn) == 4)$

ERROR: braces {} are necessary for all arms of this statement
#6716: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29946:
+         if (Field_op2_Slot_inst_get (insn) == 4)
[...]

ERROR: code indent should never use tabs
#6717: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29947:
+^I    return OPCODE_S32E;$

ERROR: braces {} are necessary for all arms of this statement
#6721: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29950:
+  if (Field_op0_Slot_inst_get (insn) == 1)
[...]

ERROR: that open brace { should be on the previous line
#6723: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29952:
+  if (Field_op0_Slot_inst_get (insn) == 2)
+    {

ERROR: suspect code indent for conditional statements (2, 6)
#6723: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29952:
+  if (Field_op0_Slot_inst_get (insn) == 2)
+    {

ERROR: braces {} are necessary for all arms of this statement
#6725: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29954:
+      if (Field_r_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#6726: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29955:
+^Ireturn OPCODE_L8UI;$

ERROR: braces {} are necessary for all arms of this statement
#6727: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29956:
+      if (Field_r_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#6728: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29957:
+^Ireturn OPCODE_L16UI;$

ERROR: braces {} are necessary for all arms of this statement
#6729: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29958:
+      if (Field_r_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#6730: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29959:
+^Ireturn OPCODE_L32I;$

ERROR: braces {} are necessary for all arms of this statement
#6731: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29960:
+      if (Field_r_Slot_inst_get (insn) == 4)
[...]

ERROR: code indent should never use tabs
#6732: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29961:
+^Ireturn OPCODE_S8I;$

ERROR: braces {} are necessary for all arms of this statement
#6733: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29962:
+      if (Field_r_Slot_inst_get (insn) == 5)
[...]

ERROR: code indent should never use tabs
#6734: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29963:
+^Ireturn OPCODE_S16I;$

ERROR: braces {} are necessary for all arms of this statement
#6735: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29964:
+      if (Field_r_Slot_inst_get (insn) == 6)
[...]

ERROR: code indent should never use tabs
#6736: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29965:
+^Ireturn OPCODE_S32I;$

ERROR: suspect code indent for conditional statements (6, 10)
#6737: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29966:
+      if (Field_r_Slot_inst_get (insn) == 7)
        {

ERROR: code indent should never use tabs
#6820: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29968:
+^I  if (Field_t_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#6820: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29968:
+         if (Field_t_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#6821: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29969:
+^I    return OPCODE_DPFR;$

ERROR: code indent should never use tabs
#6822: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29970:
+^I  if (Field_t_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#6822: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29970:
+         if (Field_t_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#6823: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29971:
+^I    return OPCODE_DPFW;$

ERROR: code indent should never use tabs
#6824: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29972:
+^I  if (Field_t_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#6824: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29972:
+         if (Field_t_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#6825: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29973:
+^I    return OPCODE_DPFRO;$

ERROR: code indent should never use tabs
#6826: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29974:
+^I  if (Field_t_Slot_inst_get (insn) == 3)$

ERROR: braces {} are necessary for all arms of this statement
#6826: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29974:
+         if (Field_t_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#6827: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29975:
+^I    return OPCODE_DPFWO;$

ERROR: code indent should never use tabs
#6828: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29976:
+^I  if (Field_t_Slot_inst_get (insn) == 4)$

ERROR: braces {} are necessary for all arms of this statement
#6828: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29976:
+         if (Field_t_Slot_inst_get (insn) == 4)
[...]

ERROR: code indent should never use tabs
#6829: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29977:
+^I    return OPCODE_DHWB;$

ERROR: code indent should never use tabs
#6830: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29978:
+^I  if (Field_t_Slot_inst_get (insn) == 5)$

ERROR: braces {} are necessary for all arms of this statement
#6830: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29978:
+         if (Field_t_Slot_inst_get (insn) == 5)
[...]

ERROR: code indent should never use tabs
#6831: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29979:
+^I    return OPCODE_DHWBI;$

ERROR: code indent should never use tabs
#6832: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29980:
+^I  if (Field_t_Slot_inst_get (insn) == 6)$

ERROR: braces {} are necessary for all arms of this statement
#6832: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29980:
+         if (Field_t_Slot_inst_get (insn) == 6)
[...]

ERROR: code indent should never use tabs
#6833: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29981:
+^I    return OPCODE_DHI;$

ERROR: code indent should never use tabs
#6834: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29982:
+^I  if (Field_t_Slot_inst_get (insn) == 7)$

ERROR: braces {} are necessary for all arms of this statement
#6834: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29982:
+         if (Field_t_Slot_inst_get (insn) == 7)
[...]

ERROR: code indent should never use tabs
#6835: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29983:
+^I    return OPCODE_DII;$

ERROR: code indent should never use tabs
#6836: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29984:
+^I  if (Field_t_Slot_inst_get (insn) == 8)$

ERROR: that open brace { should be on the previous line
#6836: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29984:
+         if (Field_t_Slot_inst_get (insn) == 8)
+           {

ERROR: suspect code indent for conditional statements (10, 14)
#6836: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29984:
+         if (Field_t_Slot_inst_get (insn) == 8)
+           {

ERROR: code indent should never use tabs
#6837: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29985:
+^I    {$

ERROR: code indent should never use tabs
#6838: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29986:
+^I      if (Field_op1_Slot_inst_get (insn) == 4)$

ERROR: braces {} are necessary for all arms of this statement
#6838: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29986:
+             if (Field_op1_Slot_inst_get (insn) == 4)
[...]

ERROR: code indent should never use tabs
#6839: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29987:
+^I^Ireturn OPCODE_DIWB;$

ERROR: code indent should never use tabs
#6840: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29988:
+^I      if (Field_op1_Slot_inst_get (insn) == 5)$

ERROR: braces {} are necessary for all arms of this statement
#6840: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29988:
+             if (Field_op1_Slot_inst_get (insn) == 5)
[...]

ERROR: code indent should never use tabs
#6841: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29989:
+^I^Ireturn OPCODE_DIWBI;$

ERROR: code indent should never use tabs
#6842: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29990:
+^I    }$

ERROR: code indent should never use tabs
#6843: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29991:
+^I  if (Field_t_Slot_inst_get (insn) == 12)$

ERROR: braces {} are necessary for all arms of this statement
#6843: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29991:
+         if (Field_t_Slot_inst_get (insn) == 12)
[...]

ERROR: code indent should never use tabs
#6844: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29992:
+^I    return OPCODE_IPF;$

ERROR: code indent should never use tabs
#6845: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29993:
+^I  if (Field_t_Slot_inst_get (insn) == 14)$

ERROR: braces {} are necessary for all arms of this statement
#6845: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29993:
+         if (Field_t_Slot_inst_get (insn) == 14)
[...]

ERROR: code indent should never use tabs
#6846: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29994:
+^I    return OPCODE_IHI;$

ERROR: code indent should never use tabs
#6847: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29995:
+^I  if (Field_t_Slot_inst_get (insn) == 15)$

ERROR: braces {} are necessary for all arms of this statement
#6847: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29995:
+         if (Field_t_Slot_inst_get (insn) == 15)
[...]

ERROR: code indent should never use tabs
#6848: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29996:
+^I    return OPCODE_III;$

ERROR: braces {} are necessary for all arms of this statement
#6851: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29998:
+      if (Field_r_Slot_inst_get (insn) == 9)
[...]

ERROR: code indent should never use tabs
#6852: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:29999:
+^Ireturn OPCODE_L16SI;$

ERROR: braces {} are necessary for all arms of this statement
#6853: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30000:
+      if (Field_r_Slot_inst_get (insn) == 10)
[...]

ERROR: code indent should never use tabs
#6854: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30001:
+^Ireturn OPCODE_MOVI;$

ERROR: braces {} are necessary for all arms of this statement
#6855: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30002:
+      if (Field_r_Slot_inst_get (insn) == 11)
[...]

ERROR: code indent should never use tabs
#6856: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30003:
+^Ireturn OPCODE_L32AI;$

ERROR: braces {} are necessary for all arms of this statement
#6857: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30004:
+      if (Field_r_Slot_inst_get (insn) == 12)
[...]

ERROR: code indent should never use tabs
#6858: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30005:
+^Ireturn OPCODE_ADDI;$

ERROR: braces {} are necessary for all arms of this statement
#6859: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30006:
+      if (Field_r_Slot_inst_get (insn) == 13)
[...]

ERROR: code indent should never use tabs
#6860: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30007:
+^Ireturn OPCODE_ADDMI;$

ERROR: braces {} are necessary for all arms of this statement
#6861: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30008:
+      if (Field_r_Slot_inst_get (insn) == 14)
[...]

ERROR: code indent should never use tabs
#6862: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30009:
+^Ireturn OPCODE_S32C1I;$

ERROR: braces {} are necessary for all arms of this statement
#6863: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30010:
+      if (Field_r_Slot_inst_get (insn) == 15)
[...]

ERROR: code indent should never use tabs
#6864: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30011:
+^Ireturn OPCODE_S32RI;$

ERROR: that open brace { should be on the previous line
#6866: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30013:
+  if (Field_op0_Slot_inst_get (insn) == 4)
+    {

ERROR: suspect code indent for conditional statements (2, 6)
#6866: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30013:
+  if (Field_op0_Slot_inst_get (insn) == 4)
+    {

ERROR: code indent should never use tabs
#6869: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30016:
+^I  Field_op1_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#6870: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30017:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#6871: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30018:
+^Ireturn OPCODE_AE_LQ56_I;$

ERROR: code indent should never use tabs
#6873: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30020:
+^I  Field_op1_Slot_inst_get (insn) == 2 &&$

ERROR: code indent should never use tabs
#6874: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30021:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#6875: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30022:
+^Ireturn OPCODE_AE_LQ56_X;$

ERROR: code indent should never use tabs
#6877: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30024:
+^I  Field_op1_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#6878: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30025:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#6879: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30026:
+^Ireturn OPCODE_AE_LQ32F_I;$

ERROR: code indent should never use tabs
#6881: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30028:
+^I  Field_op1_Slot_inst_get (insn) == 2 &&$

ERROR: code indent should never use tabs
#6882: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30029:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#6883: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30030:
+^Ireturn OPCODE_AE_LQ32F_X;$

ERROR: code indent should never use tabs
#6885: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30032:
+^I  Field_op1_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#6886: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30033:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#6887: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30034:
+^Ireturn OPCODE_AE_LQ56_IU;$

ERROR: code indent should never use tabs
#6889: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30036:
+^I  Field_op1_Slot_inst_get (insn) == 2 &&$

ERROR: code indent should never use tabs
#6890: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30037:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#6891: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30038:
+^Ireturn OPCODE_AE_LQ56_XU;$

ERROR: code indent should never use tabs
#6893: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30040:
+^I  Field_op1_Slot_inst_get (insn) == 7 &&$

ERROR: code indent should never use tabs
#6894: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30041:
+^I  Field_t_Slot_inst_get (insn) == 3 &&$

ERROR: code indent should never use tabs
#6895: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30042:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#6896: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30043:
+^Ireturn OPCODE_AE_CVTQ48A32S;$

ERROR: code indent should never use tabs
#6898: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30045:
+^I  Field_op1_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#6899: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30046:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#6900: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30047:
+^Ireturn OPCODE_AE_LQ32F_IU;$

ERROR: code indent should never use tabs
#6902: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30049:
+^I  Field_op1_Slot_inst_get (insn) == 2 &&$

ERROR: code indent should never use tabs
#6903: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30050:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#6904: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30051:
+^Ireturn OPCODE_AE_LQ32F_XU;$

ERROR: code indent should never use tabs
#6906: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30053:
+^I  Field_op1_Slot_inst_get (insn) == 5 &&$

ERROR: code indent should never use tabs
#6907: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30054:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#6908: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30055:
+^Ireturn OPCODE_AE_LP16F_I;$

ERROR: code indent should never use tabs
#6910: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30057:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#6911: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30058:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#6912: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30059:
+^Ireturn OPCODE_AE_LP16F_IU;$

ERROR: code indent should never use tabs
#6914: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30061:
+^I  Field_op1_Slot_inst_get (insn) == 12 &&$

ERROR: code indent should never use tabs
#6915: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30062:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#6916: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30063:
+^Ireturn OPCODE_AE_LP16F_X;$

ERROR: code indent should never use tabs
#6918: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30065:
+^I  Field_op1_Slot_inst_get (insn) == 15 &&$

ERROR: code indent should never use tabs
#6919: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30066:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#6920: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30067:
+^Ireturn OPCODE_AE_LP16F_XU;$

ERROR: code indent should never use tabs
#6922: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30069:
+^I  Field_op1_Slot_inst_get (insn) == 6 &&$

ERROR: code indent should never use tabs
#6923: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30070:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#6924: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30071:
+^Ireturn OPCODE_AE_LP24F_I;$

ERROR: code indent should never use tabs
#6926: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30073:
+^I  Field_op1_Slot_inst_get (insn) == 10 &&$

ERROR: code indent should never use tabs
#6927: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30074:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#6928: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30075:
+^Ireturn OPCODE_AE_LP24F_IU;$

ERROR: code indent should never use tabs
#6930: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30077:
+^I  Field_op1_Slot_inst_get (insn) == 13 &&$

ERROR: code indent should never use tabs
#6931: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30078:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#6932: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30079:
+^Ireturn OPCODE_AE_LP24F_X;$

ERROR: code indent should never use tabs
#6934: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30081:
+^I  Field_op1_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#6935: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30082:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#6936: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30083:
+^Ireturn OPCODE_AE_LP24F_XU;$

ERROR: code indent should never use tabs
#6938: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30085:
+^I  Field_op1_Slot_inst_get (insn) == 7 &&$

ERROR: code indent should never use tabs
#6939: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30086:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#6940: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30087:
+^Ireturn OPCODE_AE_LP24X2F_I;$

ERROR: code indent should never use tabs
#6942: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30089:
+^I  Field_op1_Slot_inst_get (insn) == 11 &&$

ERROR: code indent should never use tabs
#6943: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30090:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#6944: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30091:
+^Ireturn OPCODE_AE_LP24X2F_IU;$

ERROR: code indent should never use tabs
#6946: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30093:
+^I  Field_op1_Slot_inst_get (insn) == 14 &&$

ERROR: code indent should never use tabs
#6947: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30094:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#6948: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30095:
+^Ireturn OPCODE_AE_LP24X2F_X;$

ERROR: code indent should never use tabs
#6950: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30097:
+^I  Field_op1_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#6951: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30098:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#6952: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30099:
+^Ireturn OPCODE_AE_LP24X2F_XU;$

ERROR: code indent should never use tabs
#6954: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30101:
+^I  Field_op1_Slot_inst_get (insn) == 2 &&$

ERROR: code indent should never use tabs
#6955: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30102:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#6956: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30103:
+^Ireturn OPCODE_AE_SP16X2F_I;$

ERROR: code indent should never use tabs
#6958: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30105:
+^I  Field_op1_Slot_inst_get (insn) == 5 &&$

ERROR: code indent should never use tabs
#6959: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30106:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#6960: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30107:
+^Ireturn OPCODE_AE_SP16X2F_IU;$

ERROR: code indent should never use tabs
#6962: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30109:
+^I  Field_op1_Slot_inst_get (insn) == 8 &&$

ERROR: code indent should never use tabs
#6963: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30110:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#6964: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30111:
+^Ireturn OPCODE_AE_SP16X2F_X;$

ERROR: code indent should never use tabs
#6966: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30113:
+^I  Field_op1_Slot_inst_get (insn) == 11 &&$

ERROR: code indent should never use tabs
#6967: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30114:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#6968: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30115:
+^Ireturn OPCODE_AE_SP16X2F_XU;$

ERROR: code indent should never use tabs
#6970: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30117:
+^I  Field_op1_Slot_inst_get (insn) == 3 &&$

ERROR: code indent should never use tabs
#6971: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30118:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#6972: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30119:
+^Ireturn OPCODE_AE_SP24X2F_I;$

ERROR: code indent should never use tabs
#6974: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30121:
+^I  Field_op1_Slot_inst_get (insn) == 6 &&$

ERROR: code indent should never use tabs
#6975: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30122:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#6976: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30123:
+^Ireturn OPCODE_AE_SP24X2F_IU;$

ERROR: code indent should never use tabs
#6978: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30125:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#6979: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30126:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#6980: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30127:
+^Ireturn OPCODE_AE_SP24X2F_X;$

ERROR: code indent should never use tabs
#6982: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30129:
+^I  Field_op1_Slot_inst_get (insn) == 12 &&$

ERROR: code indent should never use tabs
#6983: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30130:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#6984: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30131:
+^Ireturn OPCODE_AE_SP24X2F_XU;$

ERROR: code indent should never use tabs
#6986: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30133:
+^I  Field_op1_Slot_inst_get (insn) == 4 &&$

ERROR: code indent should never use tabs
#6987: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30134:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#6988: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30135:
+^Ireturn OPCODE_AE_SP24S_L_I;$

ERROR: code indent should never use tabs
#6990: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30137:
+^I  Field_op1_Slot_inst_get (insn) == 7 &&$

ERROR: code indent should never use tabs
#6991: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30138:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#6992: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30139:
+^Ireturn OPCODE_AE_SP24S_L_IU;$

ERROR: code indent should never use tabs
#6994: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30141:
+^I  Field_op1_Slot_inst_get (insn) == 10 &&$

ERROR: code indent should never use tabs
#6995: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30142:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#6996: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30143:
+^Ireturn OPCODE_AE_SP24S_L_X;$

ERROR: code indent should never use tabs
#6998: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30145:
+^I  Field_op1_Slot_inst_get (insn) == 13 &&$

ERROR: code indent should never use tabs
#6999: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30146:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7000: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30147:
+^Ireturn OPCODE_AE_SP24S_L_XU;$

ERROR: code indent should never use tabs
#7002: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30149:
+^I  Field_ae_s3_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7003: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30150:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7004: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30151:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7005: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30152:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7006: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30153:
+^Ireturn OPCODE_AE_MOVP48;$

ERROR: code indent should never use tabs
#7008: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30155:
+^I  Field_op1_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7009: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30156:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7010: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30157:
+^Ireturn OPCODE_AE_MOVPA24X2;$

ERROR: code indent should never use tabs
#7012: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30159:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7013: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30160:
+^I  Field_op1_Slot_inst_get (insn) == 11 &&$

ERROR: code indent should never use tabs
#7014: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30161:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7015: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30162:
+^Ireturn OPCODE_AE_CVTA32P24_L;$

ERROR: code indent should never use tabs
#7017: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30164:
+^I  Field_op1_Slot_inst_get (insn) == 14 &&$

ERROR: code indent should never use tabs
#7018: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30165:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7019: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30166:
+^Ireturn OPCODE_AE_CVTP24A16X2_LL;$

ERROR: code indent should never use tabs
#7021: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30168:
+^I  Field_op1_Slot_inst_get (insn) == 15 &&$

ERROR: code indent should never use tabs
#7022: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30169:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7023: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30170:
+^Ireturn OPCODE_AE_CVTP24A16X2_HL;$

ERROR: code indent should never use tabs
#7025: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30172:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7026: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30173:
+^I  Field_op1_Slot_inst_get (insn) == 7 &&$

ERROR: code indent should never use tabs
#7027: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30174:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7028: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30175:
+^Ireturn OPCODE_AE_MOVAP24S_L;$

ERROR: code indent should never use tabs
#7030: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30177:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7031: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30178:
+^I  Field_op1_Slot_inst_get (insn) == 8 &&$

ERROR: code indent should never use tabs
#7032: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30179:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7033: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30180:
+^Ireturn OPCODE_AE_TRUNCA16P24S_L;$

ERROR: code indent should never use tabs
#7035: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30182:
+^I  Field_op1_Slot_inst_get (insn) == 5 &&$

ERROR: code indent should never use tabs
#7036: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30183:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7037: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30184:
+^Ireturn OPCODE_AE_LP24_I;$

ERROR: code indent should never use tabs
#7039: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30186:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7040: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30187:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7041: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30188:
+^Ireturn OPCODE_AE_LP24_IU;$

ERROR: code indent should never use tabs
#7043: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30190:
+^I  Field_op1_Slot_inst_get (insn) == 12 &&$

ERROR: code indent should never use tabs
#7044: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30191:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7045: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30192:
+^Ireturn OPCODE_AE_LP24_X;$

ERROR: code indent should never use tabs
#7047: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30194:
+^I  Field_op1_Slot_inst_get (insn) == 15 &&$

ERROR: code indent should never use tabs
#7048: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30195:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7049: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30196:
+^Ireturn OPCODE_AE_LP24_XU;$

ERROR: code indent should never use tabs
#7051: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30198:
+^I  Field_op1_Slot_inst_get (insn) == 6 &&$

ERROR: code indent should never use tabs
#7052: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30199:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7053: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30200:
+^Ireturn OPCODE_AE_LP16X2F_I;$

ERROR: code indent should never use tabs
#7055: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30202:
+^I  Field_op1_Slot_inst_get (insn) == 10 &&$

ERROR: code indent should never use tabs
#7056: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30203:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7057: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30204:
+^Ireturn OPCODE_AE_LP16X2F_IU;$

ERROR: code indent should never use tabs
#7059: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30206:
+^I  Field_op1_Slot_inst_get (insn) == 13 &&$

ERROR: code indent should never use tabs
#7060: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30207:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7061: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30208:
+^Ireturn OPCODE_AE_LP16X2F_X;$

ERROR: code indent should never use tabs
#7063: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30210:
+^I  Field_op1_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7064: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30211:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7065: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30212:
+^Ireturn OPCODE_AE_LP16X2F_XU;$

ERROR: code indent should never use tabs
#7067: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30214:
+^I  Field_op1_Slot_inst_get (insn) == 7 &&$

ERROR: code indent should never use tabs
#7068: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30215:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7069: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30216:
+^Ireturn OPCODE_AE_LP24X2_I;$

ERROR: code indent should never use tabs
#7071: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30218:
+^I  Field_op1_Slot_inst_get (insn) == 11 &&$

ERROR: code indent should never use tabs
#7072: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30219:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7073: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30220:
+^Ireturn OPCODE_AE_LP24X2_IU;$

ERROR: code indent should never use tabs
#7075: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30222:
+^I  Field_op1_Slot_inst_get (insn) == 14 &&$

ERROR: code indent should never use tabs
#7076: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30223:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7077: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30224:
+^Ireturn OPCODE_AE_LP24X2_X;$

ERROR: code indent should never use tabs
#7079: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30226:
+^I  Field_op1_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7080: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30227:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7081: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30228:
+^Ireturn OPCODE_AE_LP24X2_XU;$

ERROR: code indent should never use tabs
#7083: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30230:
+^I  Field_op1_Slot_inst_get (insn) == 2 &&$

ERROR: code indent should never use tabs
#7084: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30231:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7085: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30232:
+^Ireturn OPCODE_AE_SP24X2S_I;$

ERROR: code indent should never use tabs
#7087: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30234:
+^I  Field_op1_Slot_inst_get (insn) == 5 &&$

ERROR: code indent should never use tabs
#7088: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30235:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7089: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30236:
+^Ireturn OPCODE_AE_SP24X2S_IU;$

ERROR: code indent should never use tabs
#7091: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30238:
+^I  Field_op1_Slot_inst_get (insn) == 8 &&$

ERROR: code indent should never use tabs
#7092: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30239:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7093: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30240:
+^Ireturn OPCODE_AE_SP24X2S_X;$

ERROR: code indent should never use tabs
#7095: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30242:
+^I  Field_op1_Slot_inst_get (insn) == 11 &&$

ERROR: code indent should never use tabs
#7096: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30243:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7097: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30244:
+^Ireturn OPCODE_AE_SP24X2S_XU;$

ERROR: code indent should never use tabs
#7099: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30246:
+^I  Field_op1_Slot_inst_get (insn) == 3 &&$

ERROR: code indent should never use tabs
#7100: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30247:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7101: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30248:
+^Ireturn OPCODE_AE_SP16F_L_I;$

ERROR: code indent should never use tabs
#7103: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30250:
+^I  Field_op1_Slot_inst_get (insn) == 6 &&$

ERROR: code indent should never use tabs
#7104: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30251:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7105: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30252:
+^Ireturn OPCODE_AE_SP16F_L_IU;$

ERROR: code indent should never use tabs
#7107: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30254:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7108: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30255:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7109: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30256:
+^Ireturn OPCODE_AE_SP16F_L_X;$

ERROR: code indent should never use tabs
#7111: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30258:
+^I  Field_op1_Slot_inst_get (insn) == 12 &&$

ERROR: code indent should never use tabs
#7112: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30259:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7113: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30260:
+^Ireturn OPCODE_AE_SP16F_L_XU;$

ERROR: code indent should never use tabs
#7115: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30262:
+^I  Field_op1_Slot_inst_get (insn) == 4 &&$

ERROR: code indent should never use tabs
#7116: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30263:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7117: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30264:
+^Ireturn OPCODE_AE_SP24F_L_I;$

ERROR: code indent should never use tabs
#7119: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30266:
+^I  Field_op1_Slot_inst_get (insn) == 7 &&$

ERROR: code indent should never use tabs
#7120: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30267:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7121: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30268:
+^Ireturn OPCODE_AE_SP24F_L_IU;$

ERROR: code indent should never use tabs
#7123: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30270:
+^I  Field_op1_Slot_inst_get (insn) == 10 &&$

ERROR: code indent should never use tabs
#7124: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30271:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7125: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30272:
+^Ireturn OPCODE_AE_SP24F_L_X;$

ERROR: code indent should never use tabs
#7127: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30274:
+^I  Field_op1_Slot_inst_get (insn) == 13 &&$

ERROR: code indent should never use tabs
#7128: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30275:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7129: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30276:
+^Ireturn OPCODE_AE_SP24F_L_XU;$

ERROR: code indent should never use tabs
#7131: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30278:
+^I  Field_op1_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7132: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30279:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7133: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30280:
+^Ireturn OPCODE_AE_TRUNCP24A32X2;$

ERROR: code indent should never use tabs
#7135: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30282:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7136: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30283:
+^I  Field_op1_Slot_inst_get (insn) == 11 &&$

ERROR: code indent should never use tabs
#7137: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30284:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7138: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30285:
+^Ireturn OPCODE_AE_CVTA32P24_H;$

ERROR: code indent should never use tabs
#7140: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30287:
+^I  Field_op1_Slot_inst_get (insn) == 14 &&$

ERROR: code indent should never use tabs
#7141: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30288:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7142: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30289:
+^Ireturn OPCODE_AE_CVTP24A16X2_LH;$

ERROR: code indent should never use tabs
#7144: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30291:
+^I  Field_op1_Slot_inst_get (insn) == 15 &&$

ERROR: code indent should never use tabs
#7145: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30292:
+^I  Field_op2_Slot_inst_get (insn) == 11)$

ERROR: code indent should never use tabs
#7146: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30293:
+^Ireturn OPCODE_AE_CVTP24A16X2_HH;$

ERROR: code indent should never use tabs
#7148: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30295:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7149: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30296:
+^I  Field_op1_Slot_inst_get (insn) == 7 &&$

ERROR: code indent should never use tabs
#7150: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30297:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7151: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30298:
+^Ireturn OPCODE_AE_MOVAP24S_H;$

ERROR: code indent should never use tabs
#7153: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30300:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7154: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30301:
+^I  Field_op1_Slot_inst_get (insn) == 8 &&$

ERROR: code indent should never use tabs
#7155: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30302:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7156: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30303:
+^Ireturn OPCODE_AE_TRUNCA16P24S_H;$

ERROR: code indent should never use tabs
#7158: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30305:
+^I  Field_op1_Slot_inst_get (insn) == 3 &&$

ERROR: code indent should never use tabs
#7159: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30306:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7160: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30307:
+^Ireturn OPCODE_AE_SQ56S_I;$

ERROR: code indent should never use tabs
#7162: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30309:
+^I  Field_op1_Slot_inst_get (insn) == 4 &&$

ERROR: code indent should never use tabs
#7163: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30310:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7164: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30311:
+^Ireturn OPCODE_AE_SQ56S_X;$

ERROR: code indent should never use tabs
#7166: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30313:
+^I  Field_op1_Slot_inst_get (insn) == 7 &&$

ERROR: code indent should never use tabs
#7167: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30314:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7168: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30315:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#7169: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30316:
+^Ireturn OPCODE_AE_TRUNCA32Q48;$

ERROR: code indent should never use tabs
#7171: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30318:
+^I  Field_op1_Slot_inst_get (insn) == 3 &&$

ERROR: code indent should never use tabs
#7172: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30319:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7173: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30320:
+^Ireturn OPCODE_AE_SQ32F_I;$

ERROR: code indent should never use tabs
#7175: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30322:
+^I  Field_op1_Slot_inst_get (insn) == 4 &&$

ERROR: code indent should never use tabs
#7176: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30323:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7177: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30324:
+^Ireturn OPCODE_AE_SQ32F_X;$

ERROR: code indent should never use tabs
#7179: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30326:
+^I  Field_op1_Slot_inst_get (insn) == 7 &&$

ERROR: code indent should never use tabs
#7180: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30327:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7181: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30328:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#7182: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30329:
+^Ireturn OPCODE_AE_NSAQ56S;$

ERROR: code indent should never use tabs
#7184: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30331:
+^I  Field_op1_Slot_inst_get (insn) == 3 &&$

ERROR: code indent should never use tabs
#7185: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30332:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7186: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30333:
+^Ireturn OPCODE_AE_SQ56S_IU;$

ERROR: code indent should never use tabs
#7188: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30335:
+^I  Field_op1_Slot_inst_get (insn) == 4 &&$

ERROR: code indent should never use tabs
#7189: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30336:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7190: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30337:
+^Ireturn OPCODE_AE_SQ56S_XU;$

ERROR: code indent should never use tabs
#7192: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30339:
+^I  Field_op1_Slot_inst_get (insn) == 3 &&$

ERROR: code indent should never use tabs
#7193: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30340:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7194: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30341:
+^Ireturn OPCODE_AE_SQ32F_IU;$

ERROR: code indent should never use tabs
#7196: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30343:
+^I  Field_op1_Slot_inst_get (insn) == 4 &&$

ERROR: code indent should never use tabs
#7197: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30344:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7198: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30345:
+^Ireturn OPCODE_AE_SQ32F_XU;$

ERROR: code indent should never use tabs
#7200: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30347:
+^I  Field_op1_Slot_inst_get (insn) == 5 &&$

ERROR: code indent should never use tabs
#7201: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30348:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7202: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30349:
+^Ireturn OPCODE_AE_SLLIQ56;$

ERROR: code indent should never use tabs
#7204: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30351:
+^I  Field_op1_Slot_inst_get (insn) == 5 &&$

ERROR: code indent should never use tabs
#7205: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30352:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7206: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30353:
+^Ireturn OPCODE_AE_SRLIQ56;$

ERROR: code indent should never use tabs
#7208: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30355:
+^I  Field_op1_Slot_inst_get (insn) == 5 &&$

ERROR: code indent should never use tabs
#7209: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30356:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7210: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30357:
+^Ireturn OPCODE_AE_SRAIQ56;$

ERROR: code indent should never use tabs
#7212: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30359:
+^I  Field_op1_Slot_inst_get (insn) == 5 &&$

ERROR: code indent should never use tabs
#7213: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30360:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7214: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30361:
+^Ireturn OPCODE_AE_SLLISQ56S;$

ERROR: code indent should never use tabs
#7216: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30363:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7217: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30364:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#7218: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30365:
+^Ireturn OPCODE_AE_SHA32;$

ERROR: code indent should never use tabs
#7220: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30367:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7221: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30368:
+^Ireturn OPCODE_AE_VLDL32T;$

ERROR: code indent should never use tabs
#7223: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30370:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7224: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30371:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#7225: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30372:
+^Ireturn OPCODE_AE_SLLAQ56;$

ERROR: code indent should never use tabs
#7227: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30374:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7228: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30375:
+^Ireturn OPCODE_AE_VLDL16T;$

ERROR: code indent should never use tabs
#7230: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30377:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7231: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30378:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#7232: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30379:
+^Ireturn OPCODE_AE_SRLAQ56;$

ERROR: code indent should never use tabs
#7234: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30381:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7235: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30382:
+^Ireturn OPCODE_AE_LBK;$

ERROR: code indent should never use tabs
#7237: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30384:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7238: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30385:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#7239: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30386:
+^Ireturn OPCODE_AE_SRAAQ56;$

ERROR: code indent should never use tabs
#7241: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30388:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7242: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30389:
+^Ireturn OPCODE_AE_VLEL32T;$

ERROR: code indent should never use tabs
#7244: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30391:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7245: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30392:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#7246: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30393:
+^Ireturn OPCODE_AE_SLLASQ56S;$

ERROR: code indent should never use tabs
#7248: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30395:
+^I  Field_op2_Slot_inst_get (insn) == 10)$

ERROR: code indent should never use tabs
#7249: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30396:
+^Ireturn OPCODE_AE_VLEL16T;$

ERROR: code indent should never use tabs
#7251: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30398:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7252: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30399:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#7253: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30400:
+^Ireturn OPCODE_AE_MOVTQ56;$

ERROR: code indent should never use tabs
#7255: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30402:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7256: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30403:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#7257: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30404:
+^Ireturn OPCODE_AE_MOVFQ56;$

ERROR: code indent should never use tabs
#7259: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30406:
+^I  Field_s_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7260: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30407:
+^I  Field_op1_Slot_inst_get (insn) == 10 &&$

ERROR: code indent should never use tabs
#7261: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30408:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7262: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30409:
+^Ireturn OPCODE_WUR_AE_OVERFLOW;$

ERROR: code indent should never use tabs
#7264: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30411:
+^I  Field_op2_Slot_inst_get (insn) == 15)$

ERROR: code indent should never use tabs
#7265: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30412:
+^Ireturn OPCODE_AE_SBI;$

ERROR: code indent should never use tabs
#7267: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30414:
+^I  Field_s_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7268: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30415:
+^I  Field_op1_Slot_inst_get (insn) == 10 &&$

ERROR: code indent should never use tabs
#7269: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30416:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7270: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30417:
+^Ireturn OPCODE_WUR_AE_SAR;$

ERROR: code indent should never use tabs
#7272: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30419:
+^I  Field_op1_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7273: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30420:
+^I  Field_op2_Slot_inst_get (insn) == 15)$

ERROR: code indent should never use tabs
#7274: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30421:
+^Ireturn OPCODE_AE_DB;$

ERROR: code indent should never use tabs
#7276: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30423:
+^I  Field_op1_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7277: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30424:
+^I  Field_op2_Slot_inst_get (insn) == 15)$

ERROR: code indent should never use tabs
#7278: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30425:
+^Ireturn OPCODE_AE_SB;$

ERROR: code indent should never use tabs
#7280: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30427:
+^I  Field_s_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7281: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30428:
+^I  Field_op1_Slot_inst_get (insn) == 10 &&$

ERROR: code indent should never use tabs
#7282: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30429:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7283: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30430:
+^Ireturn OPCODE_WUR_AE_BITPTR;$

ERROR: code indent should never use tabs
#7285: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30432:
+^I  Field_s_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7286: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30433:
+^I  Field_op1_Slot_inst_get (insn) == 10 &&$

ERROR: code indent should never use tabs
#7287: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30434:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7288: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30435:
+^Ireturn OPCODE_WUR_AE_BITSUSED;$

ERROR: code indent should never use tabs
#7290: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30437:
+^I  Field_s_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7291: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30438:
+^I  Field_op1_Slot_inst_get (insn) == 10 &&$

ERROR: code indent should never use tabs
#7292: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30439:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7293: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30440:
+^Ireturn OPCODE_WUR_AE_TABLESIZE;$

ERROR: code indent should never use tabs
#7295: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30442:
+^I  Field_s_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7296: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30443:
+^I  Field_op1_Slot_inst_get (insn) == 10 &&$

ERROR: code indent should never use tabs
#7297: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30444:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7298: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30445:
+^Ireturn OPCODE_WUR_AE_FIRST_TS;$

ERROR: code indent should never use tabs
#7300: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30447:
+^I  Field_s_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7301: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30448:
+^I  Field_op1_Slot_inst_get (insn) == 10 &&$

ERROR: code indent should never use tabs
#7302: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30449:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7303: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30450:
+^Ireturn OPCODE_WUR_AE_NEXTOFFSET;$

ERROR: code indent should never use tabs
#7305: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30452:
+^I  Field_s_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7306: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30453:
+^I  Field_op1_Slot_inst_get (insn) == 10 &&$

ERROR: code indent should never use tabs
#7307: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30454:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7308: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30455:
+^Ireturn OPCODE_WUR_AE_SEARCHDONE;$

ERROR: code indent should never use tabs
#7310: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30457:
+^I  Field_s_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7311: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30458:
+^I  Field_op1_Slot_inst_get (insn) == 10 &&$

ERROR: code indent should never use tabs
#7312: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30459:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7313: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30460:
+^Ireturn OPCODE_AE_VLDSHT;$

ERROR: code indent should never use tabs
#7315: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30462:
+^I  Field_op1_Slot_inst_get (insn) == 7 &&$

ERROR: code indent should never use tabs
#7316: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30463:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7317: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30464:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#7318: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30465:
+^Ireturn OPCODE_AE_VLES16C;$

ERROR: code indent should never use tabs
#7320: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30467:
+^I  Field_op1_Slot_inst_get (insn) == 7 &&$

ERROR: code indent should never use tabs
#7321: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30468:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7322: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30469:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#7323: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30470:
+^Ireturn OPCODE_AE_SBF;$

ERROR: code indent should never use tabs
#7325: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30472:
+^I  Field_op1_Slot_inst_get (insn) == 7 &&$

ERROR: code indent should never use tabs
#7326: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30473:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7327: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30474:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#7328: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30475:
+^Ireturn OPCODE_AE_VLDL16C;$

ERROR: code indent should never use tabs
#7330: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30477:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7331: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30478:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7332: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30479:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7333: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30480:
+^Ireturn OPCODE_AE_SLLSQ56;$

ERROR: code indent should never use tabs
#7335: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30482:
+^I  Field_op1_Slot_inst_get (insn) == 6 &&$

ERROR: code indent should never use tabs
#7336: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30483:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7337: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30484:
+^Ireturn OPCODE_AE_LB;$

ERROR: code indent should never use tabs
#7339: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30486:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7340: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30487:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7341: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30488:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7342: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30489:
+^Ireturn OPCODE_AE_SRLSQ56;$

ERROR: code indent should never use tabs
#7344: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30491:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7345: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30492:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7346: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30493:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7347: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30494:
+^Ireturn OPCODE_AE_SRASQ56;$

ERROR: code indent should never use tabs
#7349: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30496:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7350: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30497:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7351: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30498:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7352: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30499:
+^Ireturn OPCODE_AE_SLLSSQ56S;$

ERROR: code indent should never use tabs
#7354: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30501:
+^I  Field_t_Slot_inst_get (insn) == 1 &&$

ERROR: code indent should never use tabs
#7355: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30502:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7356: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30503:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7357: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30504:
+^Ireturn OPCODE_AE_MOVQ56;$

ERROR: code indent should never use tabs
#7359: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30506:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7360: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30507:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7361: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30508:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7362: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30509:
+^Ireturn OPCODE_RUR_AE_OVERFLOW;$

ERROR: code indent should never use tabs
#7364: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30511:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7365: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30512:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7366: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30513:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7367: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30514:
+^Ireturn OPCODE_RUR_AE_SAR;$

ERROR: code indent should never use tabs
#7369: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30516:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7370: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30517:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7371: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30518:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7372: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30519:
+^Ireturn OPCODE_RUR_AE_BITPTR;$

ERROR: code indent should never use tabs
#7374: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30521:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7375: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30522:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7376: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30523:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7377: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30524:
+^Ireturn OPCODE_RUR_AE_BITSUSED;$

ERROR: code indent should never use tabs
#7379: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30526:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7380: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30527:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7381: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30528:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7382: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30529:
+^Ireturn OPCODE_RUR_AE_TABLESIZE;$

ERROR: code indent should never use tabs
#7384: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30531:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7385: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30532:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7386: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30533:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7387: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30534:
+^Ireturn OPCODE_RUR_AE_FIRST_TS;$

ERROR: code indent should never use tabs
#7389: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30536:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7390: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30537:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7391: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30538:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7392: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30539:
+^Ireturn OPCODE_RUR_AE_NEXTOFFSET;$

ERROR: code indent should never use tabs
#7394: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30541:
+^I  Field_t_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7395: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30542:
+^I  Field_op1_Slot_inst_get (insn) == 9 &&$

ERROR: code indent should never use tabs
#7396: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30543:
+^I  Field_op2_Slot_inst_get (insn) == 12)$

ERROR: code indent should never use tabs
#7397: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30544:
+^Ireturn OPCODE_RUR_AE_SEARCHDONE;$

ERROR: code indent should never use tabs
#7399: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30546:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#7400: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30547:
+^Ireturn OPCODE_AE_LBKI;$

ERROR: code indent should never use tabs
#7402: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30549:
+^I  Field_r_Slot_inst_get (insn) == 2 &&$

ERROR: code indent should never use tabs
#7403: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30550:
+^I  Field_op2_Slot_inst_get (insn) == 15)$

ERROR: code indent should never use tabs
#7404: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30551:
+^Ireturn OPCODE_AE_DBI;$

ERROR: code indent should never use tabs
#7406: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30553:
+^I  Field_s_Slot_inst_get (insn) == 0 &&$

ERROR: code indent should never use tabs
#7407: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30554:
+^I  Field_op2_Slot_inst_get (insn) == 14)$

ERROR: code indent should never use tabs
#7408: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30555:
+^Ireturn OPCODE_AE_LBI;$

ERROR: that open brace { should be on the previous line
#7410: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30557:
+  if (Field_op0_Slot_inst_get (insn) == 5)
+    {

ERROR: suspect code indent for conditional statements (2, 6)
#7410: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30557:
+  if (Field_op0_Slot_inst_get (insn) == 5)
+    {

ERROR: braces {} are necessary for all arms of this statement
#7412: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30559:
+      if (Field_n_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#7413: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30560:
+^Ireturn OPCODE_CALL0;$

ERROR: braces {} are necessary for all arms of this statement
#7414: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30561:
+      if (Field_n_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#7415: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30562:
+^Ireturn OPCODE_CALL4;$

ERROR: braces {} are necessary for all arms of this statement
#7416: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30563:
+      if (Field_n_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#7417: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30564:
+^Ireturn OPCODE_CALL8;$

ERROR: braces {} are necessary for all arms of this statement
#7418: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30565:
+      if (Field_n_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#7419: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30566:
+^Ireturn OPCODE_CALL12;$

ERROR: that open brace { should be on the previous line
#7421: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30568:
+  if (Field_op0_Slot_inst_get (insn) == 6)
+    {

ERROR: suspect code indent for conditional statements (2, 6)
#7421: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30568:
+  if (Field_op0_Slot_inst_get (insn) == 6)
+    {

ERROR: braces {} are necessary for all arms of this statement
#7423: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30570:
+      if (Field_n_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#7424: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30571:
+^Ireturn OPCODE_J;$

ERROR: suspect code indent for conditional statements (6, 10)
#7425: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30572:
+      if (Field_n_Slot_inst_get (insn) == 1)
        {

ERROR: code indent should never use tabs
#7439: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30574:
+^I  if (Field_m_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#7439: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30574:
+         if (Field_m_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#7440: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30575:
+^I    return OPCODE_BEQZ;$

ERROR: code indent should never use tabs
#7441: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30576:
+^I  if (Field_m_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#7441: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30576:
+         if (Field_m_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#7442: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30577:
+^I    return OPCODE_BNEZ;$

ERROR: code indent should never use tabs
#7443: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30578:
+^I  if (Field_m_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#7443: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30578:
+         if (Field_m_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#7444: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30579:
+^I    return OPCODE_BLTZ;$

ERROR: code indent should never use tabs
#7445: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30580:
+^I  if (Field_m_Slot_inst_get (insn) == 3)$

ERROR: braces {} are necessary for all arms of this statement
#7445: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30580:
+         if (Field_m_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#7446: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30581:
+^I    return OPCODE_BGEZ;$

ERROR: suspect code indent for conditional statements (6, 10)
#7451: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30583:
+      if (Field_n_Slot_inst_get (insn) == 2)
        {

ERROR: code indent should never use tabs
#7461: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30585:
+^I  if (Field_m_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#7461: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30585:
+         if (Field_m_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#7462: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30586:
+^I    return OPCODE_BEQI;$

ERROR: code indent should never use tabs
#7463: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30587:
+^I  if (Field_m_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#7463: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30587:
+         if (Field_m_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#7464: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30588:
+^I    return OPCODE_BNEI;$

ERROR: code indent should never use tabs
#7465: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30589:
+^I  if (Field_m_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#7465: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30589:
+         if (Field_m_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#7466: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30590:
+^I    return OPCODE_BLTI;$

ERROR: code indent should never use tabs
#7467: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30591:
+^I  if (Field_m_Slot_inst_get (insn) == 3)$

ERROR: braces {} are necessary for all arms of this statement
#7467: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30591:
+         if (Field_m_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#7468: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30592:
+^I    return OPCODE_BGEI;$

ERROR: suspect code indent for conditional statements (6, 10)
#7473: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30594:
+      if (Field_n_Slot_inst_get (insn) == 3)
        {

ERROR: code indent should never use tabs
#7505: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30596:
+^I  if (Field_m_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#7505: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30596:
+         if (Field_m_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#7506: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30597:
+^I    return OPCODE_ENTRY;$

ERROR: code indent should never use tabs
#7507: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30598:
+^I  if (Field_m_Slot_inst_get (insn) == 1)$

ERROR: suspect code indent for conditional statements (10, 14)
#7507: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30598:
+         if (Field_m_Slot_inst_get (insn) == 1)
            {

ERROR: code indent should never use tabs
#7530: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30600:
+^I      if (Field_r_Slot_inst_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#7530: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30600:
+             if (Field_r_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#7531: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30601:
+^I^Ireturn OPCODE_BF;$

ERROR: code indent should never use tabs
#7532: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30602:
+^I      if (Field_r_Slot_inst_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#7532: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30602:
+             if (Field_r_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#7533: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30603:
+^I^Ireturn OPCODE_BT;$

ERROR: code indent should never use tabs
#7534: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30604:
+^I      if (Field_r_Slot_inst_get (insn) == 8)$

ERROR: braces {} are necessary for all arms of this statement
#7534: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30604:
+             if (Field_r_Slot_inst_get (insn) == 8)
[...]

ERROR: code indent should never use tabs
#7535: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30605:
+^I^Ireturn OPCODE_LOOP;$

ERROR: code indent should never use tabs
#7536: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30606:
+^I      if (Field_r_Slot_inst_get (insn) == 9)$

ERROR: braces {} are necessary for all arms of this statement
#7536: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30606:
+             if (Field_r_Slot_inst_get (insn) == 9)
[...]

ERROR: code indent should never use tabs
#7537: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30607:
+^I^Ireturn OPCODE_LOOPNEZ;$

ERROR: code indent should never use tabs
#7538: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30608:
+^I      if (Field_r_Slot_inst_get (insn) == 10)$

ERROR: braces {} are necessary for all arms of this statement
#7538: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30608:
+             if (Field_r_Slot_inst_get (insn) == 10)
[...]

ERROR: code indent should never use tabs
#7539: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30609:
+^I^Ireturn OPCODE_LOOPGTZ;$

ERROR: code indent should never use tabs
#7542: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30611:
+^I  if (Field_m_Slot_inst_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#7542: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30611:
+         if (Field_m_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#7543: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30612:
+^I    return OPCODE_BLTUI;$

ERROR: code indent should never use tabs
#7544: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30613:
+^I  if (Field_m_Slot_inst_get (insn) == 3)$

ERROR: braces {} are necessary for all arms of this statement
#7544: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30613:
+         if (Field_m_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#7545: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30614:
+^I    return OPCODE_BGEUI;$

ERROR: that open brace { should be on the previous line
#7584: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30617:
+  if (Field_op0_Slot_inst_get (insn) == 7)
+    {

ERROR: suspect code indent for conditional statements (2, 6)
#7584: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30617:
+  if (Field_op0_Slot_inst_get (insn) == 7)
+    {

ERROR: braces {} are necessary for all arms of this statement
#7586: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30619:
+      if (Field_r_Slot_inst_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#7587: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30620:
+^Ireturn OPCODE_BNONE;$

ERROR: braces {} are necessary for all arms of this statement
#7588: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30621:
+      if (Field_r_Slot_inst_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#7589: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30622:
+^Ireturn OPCODE_BEQ;$

ERROR: braces {} are necessary for all arms of this statement
#7590: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30623:
+      if (Field_r_Slot_inst_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#7591: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30624:
+^Ireturn OPCODE_BLT;$

ERROR: braces {} are necessary for all arms of this statement
#7592: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30625:
+      if (Field_r_Slot_inst_get (insn) == 3)
[...]

ERROR: code indent should never use tabs
#7593: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30626:
+^Ireturn OPCODE_BLTU;$

ERROR: braces {} are necessary for all arms of this statement
#7594: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30627:
+      if (Field_r_Slot_inst_get (insn) == 4)
[...]

ERROR: code indent should never use tabs
#7595: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30628:
+^Ireturn OPCODE_BALL;$

ERROR: braces {} are necessary for all arms of this statement
#7596: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30629:
+      if (Field_r_Slot_inst_get (insn) == 5)
[...]

ERROR: code indent should never use tabs
#7597: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30630:
+^Ireturn OPCODE_BBC;$

ERROR: code indent should never use tabs
#7599: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30632:
+^I   Field_r_Slot_inst_get (insn) == 7))$

ERROR: code indent should never use tabs
#7600: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30633:
+^Ireturn OPCODE_BBCI;$

ERROR: braces {} are necessary for all arms of this statement
#7601: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30634:
+      if (Field_r_Slot_inst_get (insn) == 8)
[...]

ERROR: code indent should never use tabs
#7602: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30635:
+^Ireturn OPCODE_BANY;$

ERROR: braces {} are necessary for all arms of this statement
#7603: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30636:
+      if (Field_r_Slot_inst_get (insn) == 9)
[...]

ERROR: code indent should never use tabs
#7604: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30637:
+^Ireturn OPCODE_BNE;$

ERROR: braces {} are necessary for all arms of this statement
#7605: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30638:
+      if (Field_r_Slot_inst_get (insn) == 10)
[...]

ERROR: code indent should never use tabs
#7606: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30639:
+^Ireturn OPCODE_BGE;$

ERROR: braces {} are necessary for all arms of this statement
#7607: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30640:
+      if (Field_r_Slot_inst_get (insn) == 11)
[...]

ERROR: code indent should never use tabs
#7608: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30641:
+^Ireturn OPCODE_BGEU;$

ERROR: braces {} are necessary for all arms of this statement
#7609: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30642:
+      if (Field_r_Slot_inst_get (insn) == 12)
[...]

ERROR: code indent should never use tabs
#7610: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30643:
+^Ireturn OPCODE_BNALL;$

ERROR: braces {} are necessary for all arms of this statement
#7611: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30644:
+      if (Field_r_Slot_inst_get (insn) == 13)
[...]

ERROR: code indent should never use tabs
#7612: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30645:
+^Ireturn OPCODE_BBS;$

ERROR: code indent should never use tabs
#7614: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30647:
+^I   Field_r_Slot_inst_get (insn) == 15))$

ERROR: code indent should never use tabs
#7615: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30648:
+^Ireturn OPCODE_BBSI;$

ERROR: suspect code indent for conditional statements (2, 6)
#7624: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30656:
+  if (Field_op0_Slot_inst16b_get (insn) == 12)
     {

ERROR: braces {} are necessary for all arms of this statement
#7628: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30658:
+      if (Field_i_Slot_inst16b_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#7629: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30659:
+^Ireturn OPCODE_MOVI_N;$

ERROR: suspect code indent for conditional statements (6, 10)
#7630: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30660:
+      if (Field_i_Slot_inst16b_get (insn) == 1)
        {

ERROR: code indent should never use tabs
#7643: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30662:
+^I  if (Field_z_Slot_inst16b_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#7643: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30662:
+         if (Field_z_Slot_inst16b_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#7644: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30663:
+^I    return OPCODE_BEQZ_N;$

ERROR: code indent should never use tabs
#7645: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30664:
+^I  if (Field_z_Slot_inst16b_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#7645: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30664:
+         if (Field_z_Slot_inst16b_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#7646: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30665:
+^I    return OPCODE_BNEZ_N;$

ERROR: that open brace { should be on the previous line
#7652: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30668:
+  if (Field_op0_Slot_inst16b_get (insn) == 13)
+    {

ERROR: suspect code indent for conditional statements (2, 6)
#7652: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30668:
+  if (Field_op0_Slot_inst16b_get (insn) == 13)
+    {

ERROR: braces {} are necessary for all arms of this statement
#7654: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30670:
+      if (Field_r_Slot_inst16b_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#7655: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30671:
+^Ireturn OPCODE_MOV_N;$

ERROR: suspect code indent for conditional statements (6, 10)
#7656: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30672:
+      if (Field_r_Slot_inst16b_get (insn) == 15)
        {

ERROR: code indent should never use tabs
#7679: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30674:
+^I  if (Field_t_Slot_inst16b_get (insn) == 0)$

ERROR: braces {} are necessary for all arms of this statement
#7679: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30674:
+         if (Field_t_Slot_inst16b_get (insn) == 0)
[...]

ERROR: code indent should never use tabs
#7680: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30675:
+^I    return OPCODE_RET_N;$

ERROR: code indent should never use tabs
#7681: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30676:
+^I  if (Field_t_Slot_inst16b_get (insn) == 1)$

ERROR: braces {} are necessary for all arms of this statement
#7681: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30676:
+         if (Field_t_Slot_inst16b_get (insn) == 1)
[...]

ERROR: code indent should never use tabs
#7682: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30677:
+^I    return OPCODE_RETW_N;$

ERROR: code indent should never use tabs
#7683: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30678:
+^I  if (Field_t_Slot_inst16b_get (insn) == 2)$

ERROR: braces {} are necessary for all arms of this statement
#7683: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30678:
+         if (Field_t_Slot_inst16b_get (insn) == 2)
[...]

ERROR: code indent should never use tabs
#7684: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30679:
+^I    return OPCODE_BREAK_N;$

ERROR: code indent should never use tabs
#7685: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30680:
+^I  if (Field_t_Slot_inst16b_get (insn) == 3 &&$

ERROR: code indent should never use tabs
#7686: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30681:
+^I      Field_s_Slot_inst16b_get (insn) == 0)$

ERROR: code indent should never use tabs
#7687: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30682:
+^I    return OPCODE_NOP_N;$

ERROR: code indent should never use tabs
#7688: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30683:
+^I  if (Field_t_Slot_inst16b_get (insn) == 6 &&$

ERROR: code indent should never use tabs
#7689: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30684:
+^I      Field_s_Slot_inst16b_get (insn) == 0)$

ERROR: code indent should never use tabs
#7690: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30685:
+^I    return OPCODE_ILL_N;$

ERROR: braces {} are necessary for all arms of this statement
#7711: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30694:
+  if (Field_op0_Slot_inst16a_get (insn) == 8)
[...]

ERROR: braces {} are necessary for all arms of this statement
#7713: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30696:
+  if (Field_op0_Slot_inst16a_get (insn) == 9)
[...]

ERROR: braces {} are necessary for all arms of this statement
#7715: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30698:
+  if (Field_op0_Slot_inst16a_get (insn) == 10)
[...]

ERROR: braces {} are necessary for all arms of this statement
#7717: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:30700:
+  if (Field_op0_Slot_inst16a_get (insn) == 11)
[...]

WARNING: Block comments use a leading /* on a separate line
#8989: FILE: target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c:36377:
+  389 /* num_fields */,

total: 2002 errors, 18 warnings, 8722 lines checked

Commit b98c8247dfc3 (target/xtensa: regenerate and re-import test_mmuhifi_c3 core) has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/[e-mail]/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to [e-mail]

Patch

diff --git a/target/xtensa/core-test_mmuhifi_c3.c b/target/xtensa/core-test_mmuhifi_c3.c
index 3a59fefa941e..089ed7da5d37 100644
--- a/target/xtensa/core-test_mmuhifi_c3.c
+++ b/target/xtensa/core-test_mmuhifi_c3.c
@@ -27,8 +27,8 @@ 
 
 #include "qemu/osdep.h"
 #include "cpu.h"
-#include "exec/exec-all.h"
 #include "exec/gdbstub.h"
+#include "qemu-common.h"
 #include "qemu/host-utils.h"
 
 #include "core-test_mmuhifi_c3/core-isa.h"
@@ -39,7 +39,6 @@ 
 
 static XtensaConfig test_mmuhifi_c3 __attribute__((unused)) = {
     .name = "test_mmuhifi_c3",
-    .options = XTENSA_OPTIONS,
     .gdb_regmap = {
         .reg = {
 #include "core-test_mmuhifi_c3/gdb-config.inc.c"
diff --git a/target/xtensa/core-test_mmuhifi_c3/core-isa.h b/target/xtensa/core-test_mmuhifi_c3/core-isa.h
index 704a31f7c89f..838b1b09dab7 100644
--- a/target/xtensa/core-test_mmuhifi_c3/core-isa.h
+++ b/target/xtensa/core-test_mmuhifi_c3/core-isa.h
@@ -1,15 +1,37 @@ 
 /*
- * Xtensa processor core configuration information.
+ * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
+ *				processor CORE configuration
  *
- * This file is subject to the terms and conditions of version 2.1 of the GNU
- * Lesser General Public License as published by the Free Software Foundation.
- *
- * Copyright (c) 1999-2009 Tensilica Inc.
+ *  See <xtensa/config/core.h>, which includes this file, for more details.
  */
 
+/* Xtensa processor core configuration information.
+
+   Copyright (c) 1999-2019 Tensilica Inc.
+
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
+
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
+
 #ifndef XTENSA_CORE_TEST_MMUHIFI_C3_CORE_ISA_H
 #define XTENSA_CORE_TEST_MMUHIFI_C3_CORE_ISA_H
 
+
 /****************************************************************************
 	    Parameters Useful for Any Code, USER or PRIVILEGED
  ****************************************************************************/
@@ -32,6 +54,7 @@ 
 #define XCHAL_HAVE_DEBUG		1	/* debug option */
 #define XCHAL_HAVE_DENSITY		1	/* 16-bit instructions */
 #define XCHAL_HAVE_LOOPS		1	/* zero-overhead loops */
+#define XCHAL_LOOP_BUFFER_SIZE		0	/* zero-ov. loop instr buffer size */
 #define XCHAL_HAVE_NSA			1	/* NSA/NSAU instructions */
 #define XCHAL_HAVE_MINMAX		1	/* MIN/MAX instructions */
 #define XCHAL_HAVE_SEXT			1	/* SEXT instruction */
@@ -59,44 +82,73 @@ 
 #define XCHAL_HAVE_TAP_MASTER		0	/* JTAG TAP control instr's */
 #define XCHAL_HAVE_PRID			1	/* processor ID register */
 #define XCHAL_HAVE_EXTERN_REGS		1	/* WER/RER instructions */
+#define XCHAL_HAVE_MX			1	/* MX core (Tensilica internal) */
 #define XCHAL_HAVE_MP_INTERRUPTS	1	/* interrupt distributor port */
 #define XCHAL_HAVE_MP_RUNSTALL		1	/* core RunStall control port */
+#define XCHAL_HAVE_PSO			0	/* Power Shut-Off */
+#define XCHAL_HAVE_PSO_CDM		0	/* core/debug/mem pwr domains */
+#define XCHAL_HAVE_PSO_FULL_RETENTION	0	/* all regs preserved on PSO */
 #define XCHAL_HAVE_THREADPTR		1	/* THREADPTR register */
 #define XCHAL_HAVE_BOOLEANS		1	/* boolean registers */
 #define XCHAL_HAVE_CP			1	/* CPENABLE reg (coprocessor) */
 #define XCHAL_CP_MAXCFG			2	/* max allowed cp id plus one */
 #define XCHAL_HAVE_MAC16		0	/* MAC16 package */
 #define XCHAL_HAVE_VECTORFPU2005	0	/* vector floating-point pkg */
-#define XCHAL_HAVE_FP			0	/* floating point pkg */
+#define XCHAL_HAVE_FP			0	/* single prec floating point */
+#define XCHAL_HAVE_FP_DIV		0	/* FP with DIV instructions */
+#define XCHAL_HAVE_FP_RECIP		0	/* FP with RECIP instructions */
+#define XCHAL_HAVE_FP_SQRT		0	/* FP with SQRT instructions */
+#define XCHAL_HAVE_FP_RSQRT		0	/* FP with RSQRT instructions */
 #define XCHAL_HAVE_DFP			0	/* double precision FP pkg */
+#define XCHAL_HAVE_DFP_DIV		0	/* DFP with DIV instructions */
+#define XCHAL_HAVE_DFP_RECIP		0	/* DFP with RECIP instructions*/
+#define XCHAL_HAVE_DFP_SQRT		0	/* DFP with SQRT instructions */
+#define XCHAL_HAVE_DFP_RSQRT		0	/* DFP with RSQRT instructions*/
 #define XCHAL_HAVE_DFP_accel		0	/* double precision FP acceleration pkg */
 #define XCHAL_HAVE_VECTRA1		0	/* Vectra I  pkg */
 #define XCHAL_HAVE_VECTRALX		0	/* Vectra LX pkg */
 #define XCHAL_HAVE_HIFIPRO		0	/* HiFiPro Audio Engine pkg */
+#define XCHAL_HAVE_HIFI3		0	/* HiFi3 Audio Engine pkg */
 #define XCHAL_HAVE_HIFI2		1	/* HiFi2 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI2EP		0	/* HiFi2EP */
+#define XCHAL_HAVE_HIFI_MINI		0	
 #define XCHAL_HAVE_CONNXD2		0	/* ConnX D2 pkg */
+#define XCHAL_HAVE_BBE16		0	/* ConnX BBE16 pkg */
+#define XCHAL_HAVE_BBE16_RSQRT		0	/* BBE16 & vector recip sqrt */
+#define XCHAL_HAVE_BBE16_VECDIV		0	/* BBE16 & vector divide */
+#define XCHAL_HAVE_BBE16_DESPREAD	0	/* BBE16 & despread */
+#define XCHAL_HAVE_BBENEP		0	/* ConnX BBENEP pkgs */
+#define XCHAL_HAVE_BSP3			0	/* ConnX BSP3 pkg */
+#define XCHAL_HAVE_BSP3_TRANSPOSE	0	/* BSP3 & transpose32x32 */
+#define XCHAL_HAVE_SSP16		0	/* ConnX SSP16 pkg */
+#define XCHAL_HAVE_SSP16_VITERBI	0	/* SSP16 & viterbi */
+#define XCHAL_HAVE_TURBO16		0	/* ConnX Turbo16 pkg */
+#define XCHAL_HAVE_BBP16		0	/* ConnX BBP16 pkg */
+#define XCHAL_HAVE_FLIX3		0	/* basic 3-way FLIX option */
 
 
 /*----------------------------------------------------------------------
 				MISC
   ----------------------------------------------------------------------*/
 
+#define XCHAL_NUM_LOADSTORE_UNITS	1	/* load/store units */
 #define XCHAL_NUM_WRITEBUFFER_ENTRIES	8	/* size of write buffer */
 #define XCHAL_INST_FETCH_WIDTH		8	/* instr-fetch width in bytes */
 #define XCHAL_DATA_WIDTH		8	/* data width in bytes */
+#define XCHAL_DATA_PIPE_DELAY		1	/* d-side pipeline delay
+						   (1 = 5-stage, 2 = 7-stage) */
 /*  In T1050, applies to selected core load and store instructions (see ISA): */
 #define XCHAL_UNALIGNED_LOAD_EXCEPTION	1	/* unaligned loads cause exc. */
 #define XCHAL_UNALIGNED_STORE_EXCEPTION	1	/* unaligned stores cause exc.*/
 #define XCHAL_UNALIGNED_LOAD_HW		0	/* unaligned loads work in hw */
 #define XCHAL_UNALIGNED_STORE_HW	0	/* unaligned stores work in hw*/
 
-#define XCHAL_SW_VERSION		800000	/* sw version of this header */
+#define XCHAL_SW_VERSION		1000006	/* sw version of this header */
 
 #define XCHAL_CORE_ID			"test_mmuhifi_c3"	/* alphanum core name
 						   (CoreID) set in the Xtensa
 						   Processor Generator */
 
-#define XCHAL_CORE_DESCRIPTION		"test_mmuhifi_c3"
 #define XCHAL_BUILD_UNIQUE_ID		0x00005A6A	/* 22-bit sw build ID */
 
 /*
@@ -136,6 +188,10 @@ 
 #define XCHAL_DCACHE_IS_WRITEBACK	1	/* writeback feature */
 #define XCHAL_DCACHE_IS_COHERENT	1	/* MP coherence feature */
 
+#define XCHAL_HAVE_PREFETCH		0	/* PREFCTL register */
+#define XCHAL_HAVE_PREFETCH_L1		0	/* prefetch to L1 dcache */
+#define XCHAL_PREFETCH_CASTOUT_LINES	0	/* dcache pref. castout bufsz */
+
 
 
 
@@ -172,6 +228,8 @@ 
 #define XCHAL_ICACHE_ACCESS_SIZE	8
 #define XCHAL_DCACHE_ACCESS_SIZE	8
 
+#define XCHAL_DCACHE_BANKS		1	/* number of banks */
+
 /*  Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits):  */
 #define XCHAL_CA_BITS			4
 
@@ -187,6 +245,8 @@ 
 #define XCHAL_NUM_URAM			0	/* number of core unified RAMs*/
 #define XCHAL_NUM_XLMI			0	/* number of core XLMI ports */
 
+#define XCHAL_HAVE_IMEM_LOADSTORE	1	/* can load/store to IROM/IRAM*/
+
 
 /*----------------------------------------------------------------------
 			INTERRUPTS and TIMERS
@@ -261,6 +321,7 @@ 
 #define XCHAL_INTTYPE_MASK_TIMER	0x00000140
 #define XCHAL_INTTYPE_MASK_NMI		0x00000000
 #define XCHAL_INTTYPE_MASK_WRITE_ERROR	0x00000000
+#define XCHAL_INTTYPE_MASK_PROFILING	0x00000000
 
 /*  Interrupt numbers assigned to specific interrupt sources:  */
 #define XCHAL_TIMER0_INTERRUPT		6	/* CCOMPARE0 */
@@ -273,7 +334,7 @@ 
 
 
 /*
- *  External interrupt vectors/levels.
+ *  External interrupt mapping.
  *  These macros describe how Xtensa processor interrupt numbers
  *  (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
  *  map to external BInterrupt<n> pins, for those interrupts
@@ -281,7 +342,7 @@ 
  *  See the Xtensa processor databook for more details.
  */
 
-/*  Core interrupt numbers mapped to each EXTERNAL interrupt number:  */
+/*  Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number:  */
 #define XCHAL_EXTINT0_NUM		0	/* (intlevel 1) */
 #define XCHAL_EXTINT1_NUM		1	/* (intlevel 1) */
 #define XCHAL_EXTINT2_NUM		2	/* (intlevel 1) */
@@ -291,6 +352,16 @@ 
 #define XCHAL_EXTINT6_NUM		9	/* (intlevel 1) */
 #define XCHAL_EXTINT7_NUM		10	/* (intlevel 1) */
 #define XCHAL_EXTINT8_NUM		11	/* (intlevel 1) */
+/*  EXTERNAL BInterrupt pin numbers mapped to each core interrupt number:  */
+#define XCHAL_INT0_EXTNUM		0	/* (intlevel 1) */
+#define XCHAL_INT1_EXTNUM		1	/* (intlevel 1) */
+#define XCHAL_INT2_EXTNUM		2	/* (intlevel 1) */
+#define XCHAL_INT3_EXTNUM		3	/* (intlevel 1) */
+#define XCHAL_INT4_EXTNUM		4	/* (intlevel 1) */
+#define XCHAL_INT5_EXTNUM		5	/* (intlevel 1) */
+#define XCHAL_INT9_EXTNUM		6	/* (intlevel 1) */
+#define XCHAL_INT10_EXTNUM		7	/* (intlevel 1) */
+#define XCHAL_INT11_EXTNUM		8	/* (intlevel 1) */
 
 
 /*----------------------------------------------------------------------
@@ -300,11 +371,13 @@ 
 #define XCHAL_XEA_VERSION		2	/* Xtensa Exception Architecture
 						   number: 1 == XEA1 (old)
 							   2 == XEA2 (new)
-							   0 == XEAX (extern) */
+							   0 == XEAX (extern) or TX */
 #define XCHAL_HAVE_XEA1			0	/* Exception Architecture 1 */
 #define XCHAL_HAVE_XEA2			1	/* Exception Architecture 2 */
 #define XCHAL_HAVE_XEAX			0	/* External Exception Arch. */
 #define XCHAL_HAVE_EXCEPTIONS		1	/* exception option */
+#define XCHAL_HAVE_HALT			0	/* halt architecture option */
+#define XCHAL_HAVE_BOOTLOADER		0	/* boot loader (for TX) */
 #define XCHAL_HAVE_MEM_ECC_PARITY	0	/* local memory ECC/parity */
 #define XCHAL_HAVE_VECTOR_SELECT	1	/* relocatable vectors */
 #define XCHAL_HAVE_VECBASE		1	/* relocatable vectors */
@@ -344,13 +417,30 @@ 
 
 
 /*----------------------------------------------------------------------
-				DEBUG
+				DEBUG MODULE
   ----------------------------------------------------------------------*/
 
+/*  Misc  */
+#define XCHAL_HAVE_DEBUG_ERI		0	/* ERI to debug module */
+#define XCHAL_HAVE_DEBUG_APB		0	/* APB to debug module */
+#define XCHAL_HAVE_DEBUG_JTAG		0	/* JTAG to debug module */
+
+/*  On-Chip Debug (OCD)  */
 #define XCHAL_HAVE_OCD			1	/* OnChipDebug option */
 #define XCHAL_NUM_IBREAK		0	/* number of IBREAKn regs */
 #define XCHAL_NUM_DBREAK		0	/* number of DBREAKn regs */
-#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option */
+#define XCHAL_HAVE_OCD_DIR_ARRAY	0	/* faster OCD option (to LX4) */
+#define XCHAL_HAVE_OCD_LS32DDR		0	/* L32DDR/S32DDR (faster OCD) */
+
+/*  TRAX (in core)  */
+#define XCHAL_HAVE_TRAX			0	/* TRAX in debug module */
+#define XCHAL_TRAX_MEM_SIZE		0	/* TRAX memory size in bytes */
+#define XCHAL_TRAX_MEM_SHAREABLE	0	/* start/end regs; ready sig. */
+#define XCHAL_TRAX_ATB_WIDTH		0	/* ATB width (bits), 0=no ATB */
+#define XCHAL_TRAX_TIME_WIDTH		0	/* timestamp bitwidth, 0=none */
+
+/*  Perf counters  */
+#define XCHAL_NUM_PERF_COUNTERS		0	/* performance counters */
 
 
 /*----------------------------------------------------------------------
diff --git a/target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c b/target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c
index 618d30dffa4a..0bca70b5afb9 100644
--- a/target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c
+++ b/target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c
@@ -1,23 +1,25 @@ 
 /* Configuration for the Xtensa architecture for GDB, the GNU debugger.
 
-   Copyright (C) 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
+   Copyright (c) 2003-2019 Tensilica Inc.
 
-   This file is part of GDB.
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
 
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3 of the License, or
-   (at your option) any later version.
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
 
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
-
-  /*    idx ofs bi sz al targno  flags cp typ group name  */
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
   XTREG(  0,  0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc,          0,0,0,0,0,0)
   XTREG(  1,  4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0,         0,0,0,0,0,0)
   XTREG(  2,  8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1,         0,0,0,0,0,0)
@@ -58,8 +60,8 @@ 
   XTREG( 37,148,32, 4, 4,0x0205,0x0006,-2, 2,0x1100,litbase,     0,0,0,0,0,0)
   XTREG( 38,152, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase,  0,0,0,0,0,0)
   XTREG( 39,156, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
-  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,sr176,       0,0,0,0,0,0)
-  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,sr208,       0,0,0,0,0,0)
+  XTREG( 40,160,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0,   0,0,0,0,0,0)
+  XTREG( 41,164,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1,   0,0,0,0,0,0)
   XTREG( 42,168,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps,          0,0,0,0,0,0)
   XTREG( 43,172,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr,   0,0,0,0,0,0)
   XTREG( 44,176,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br,          0,0,0,0,0,0)
@@ -137,4 +139,82 @@ 
   XTREG(104,464,32, 4, 4,0x000d,0x0006,-2, 8,0x0100,a13,         0,0,0,0,0,0)
   XTREG(105,468,32, 4, 4,0x000e,0x0006,-2, 8,0x0100,a14,         0,0,0,0,0,0)
   XTREG(106,472,32, 4, 4,0x000f,0x0006,-2, 8,0x0100,a15,         0,0,0,0,0,0)
+  XTREG(107,476, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
+            0,0,&xtensa_mask0,0,0,0)
+  XTREG(108,477, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
+            0,0,&xtensa_mask1,0,0,0)
+  XTREG(109,478, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
+            0,0,&xtensa_mask2,0,0,0)
+  XTREG(110,479, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
+            0,0,&xtensa_mask3,0,0,0)
+  XTREG(111,480, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
+            0,0,&xtensa_mask4,0,0,0)
+  XTREG(112,481, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
+            0,0,&xtensa_mask5,0,0,0)
+  XTREG(113,482, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
+            0,0,&xtensa_mask6,0,0,0)
+  XTREG(114,483, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
+            0,0,&xtensa_mask7,0,0,0)
+  XTREG(115,484, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
+            0,0,&xtensa_mask8,0,0,0)
+  XTREG(116,485, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
+            0,0,&xtensa_mask9,0,0,0)
+  XTREG(117,486, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
+            0,0,&xtensa_mask10,0,0,0)
+  XTREG(118,487, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
+            0,0,&xtensa_mask11,0,0,0)
+  XTREG(119,488, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
+            0,0,&xtensa_mask12,0,0,0)
+  XTREG(120,489, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
+            0,0,&xtensa_mask13,0,0,0)
+  XTREG(121,490, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
+            0,0,&xtensa_mask14,0,0,0)
+  XTREG(122,491, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
+            0,0,&xtensa_mask15,0,0,0)
+  XTREG(123,492, 4, 4, 4,0x2003,0x0006,-2, 6,0x1010,psintlevel,
+            0,0,&xtensa_mask16,0,0,0)
+  XTREG(124,496, 1, 4, 4,0x2004,0x0006,-2, 6,0x1010,psum,
+            0,0,&xtensa_mask17,0,0,0)
+  XTREG(125,500, 1, 4, 4,0x2005,0x0006,-2, 6,0x1010,pswoe,
+            0,0,&xtensa_mask18,0,0,0)
+  XTREG(126,504, 2, 4, 4,0x2006,0x0006,-2, 6,0x1010,psring,
+            0,0,&xtensa_mask19,0,0,0)
+  XTREG(127,508, 1, 4, 4,0x2007,0x0006,-2, 6,0x1010,psexcm,
+            0,0,&xtensa_mask20,0,0,0)
+  XTREG(128,512, 2, 4, 4,0x2008,0x0006,-2, 6,0x1010,pscallinc,
+            0,0,&xtensa_mask21,0,0,0)
+  XTREG(129,516, 4, 4, 4,0x2009,0x0006,-2, 6,0x1010,psowb,
+            0,0,&xtensa_mask22,0,0,0)
+  XTREG(130,520,20, 4, 4,0x200a,0x0006,-2, 6,0x1010,litbaddr,
+            0,0,&xtensa_mask23,0,0,0)
+  XTREG(131,524, 1, 4, 4,0x200b,0x0006,-2, 6,0x1010,litben,
+            0,0,&xtensa_mask24,0,0,0)
+  XTREG(132,528, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,dbnum,
+            0,0,&xtensa_mask25,0,0,0)
+  XTREG(133,532, 8, 4, 4,0x200f,0x0006,-2, 6,0x1010,asid3,
+            0,0,&xtensa_mask26,0,0,0)
+  XTREG(134,536, 8, 4, 4,0x2010,0x0006,-2, 6,0x1010,asid2,
+            0,0,&xtensa_mask27,0,0,0)
+  XTREG(135,540, 8, 4, 4,0x2011,0x0006,-2, 6,0x1010,asid1,
+            0,0,&xtensa_mask28,0,0,0)
+  XTREG(136,544, 2, 4, 4,0x2012,0x0006,-2, 6,0x1010,instpgszid4,
+            0,0,&xtensa_mask29,0,0,0)
+  XTREG(137,548, 2, 4, 4,0x2013,0x0006,-2, 6,0x1010,datapgszid4,
+            0,0,&xtensa_mask30,0,0,0)
+  XTREG(138,552,10, 4, 4,0x2014,0x0006,-2, 6,0x1010,ptbase,
+            0,0,&xtensa_mask31,0,0,0)
+  XTREG(139,556, 1, 4, 4,0x201a,0x0006, 1, 5,0x1010,ae_overflow,
+            0,0,&xtensa_mask32,0,0,0)
+  XTREG(140,560, 6, 4, 4,0x201b,0x0006, 1, 5,0x1010,ae_sar,
+            0,0,&xtensa_mask33,0,0,0)
+  XTREG(141,564, 4, 4, 4,0x201c,0x0006, 1, 5,0x1010,ae_bitptr,
+            0,0,&xtensa_mask34,0,0,0)
+  XTREG(142,568, 4, 4, 4,0x201d,0x0006, 1, 5,0x1010,ae_bitsused,
+            0,0,&xtensa_mask35,0,0,0)
+  XTREG(143,572, 4, 4, 4,0x201e,0x0006, 1, 5,0x1010,ae_tablesize,
+            0,0,&xtensa_mask36,0,0,0)
+  XTREG(144,576, 4, 4, 4,0x201f,0x0006, 1, 5,0x1010,ae_first_ts,
+            0,0,&xtensa_mask37,0,0,0)
+  XTREG(145,580,27, 4, 4,0x2020,0x0006, 1, 5,0x1010,ae_nextoffset,
+            0,0,&xtensa_mask38,0,0,0)
   XTREG_END
diff --git a/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c b/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c
index 687631b8fb2f..28561147fce7 100644
--- a/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c
+++ b/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c
@@ -1,24 +1,26 @@ 
 /* Xtensa configuration-specific ISA information.
-   Copyright 2003, 2004, 2005, 2007, 2008 Free Software Foundation, Inc.
 
-   This file is part of BFD, the Binary File Descriptor library.
+   Copyright (c) 2003-2019 Tensilica Inc.
 
-   This program is free software; you can redistribute it and/or
-   modify it under the terms of the GNU General Public License as
-   published by the Free Software Foundation; either version 3 of the
-   License, or (at your option) any later version.
+   Permission is hereby granted, free of charge, to any person obtaining
+   a copy of this software and associated documentation files (the
+   "Software"), to deal in the Software without restriction, including
+   without limitation the rights to use, copy, modify, merge, publish,
+   distribute, sublicense, and/or sell copies of the Software, and to
+   permit persons to whom the Software is furnished to do so, subject to
+   the following conditions:
 
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-   General Public License for more details.
+   The above copyright notice and this permission notice shall be included
+   in all copies or substantial portions of the Software.
 
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
-   02110-1301, USA.  */
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+   EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+   MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+   IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+   CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+   TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+   SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.  */
 
-#include "qemu/osdep.h"
 #include "xtensa-isa.h"
 #include "xtensa-isa-internal.h"
 
@@ -32,8 +34,8 @@  static xtensa_sysreg_internal sysregs[] = {
   { "BR", 4, 0 },
   { "PTEVADDR", 83, 0 },
   { "DDR", 104, 0 },
-  { "176", 176, 0 },
-  { "208", 208, 0 },
+  { "CONFIGID0", 176, 0 },
+  { "CONFIGID1", 208, 0 },
   { "INTERRUPT", 226, 0 },
   { "INTCLEAR", 227, 0 },
   { "CCOUNT", 234, 0 },
@@ -8633,6 +8635,38 @@  Field_ae_s20_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
   insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
 }
 
+static unsigned
+Field_ae_fld_ohba_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+  return tie_t;
+}
+
+static void
+Field_ae_fld_ohba_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
+static unsigned
+Field_ae_fld_ohba2_Slot_inst_get (const xtensa_insnbuf insn)
+{
+  unsigned tie_t = 0;
+  tie_t = (tie_t << 4) | ((insn[0] << 12) >> 28);
+  return tie_t;
+}
+
+static void
+Field_ae_fld_ohba2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
+{
+  uint32 tie_t;
+  tie_t = (val << 28) >> 28;
+  insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
+}
+
 static unsigned
 Field_ftsf12_Slot_inst_get (const xtensa_insnbuf insn)
 {
@@ -8794,6 +8828,8 @@  enum xtensa_field_id {
   FIELD_ae_r20,
   FIELD_ae_r10,
   FIELD_ae_s20,
+  FIELD_ae_fld_ohba,
+  FIELD_ae_fld_ohba2,
   FIELD_op0_s3,
   FIELD_ftsf12,
   FIELD_ftsf13,
@@ -9184,7 +9220,7 @@  enum xtensa_interface_id {
   INTERFACE_RMPINT_In
 };
 
-
+
 /* Constant tables.  */
 
 /* constant table ai4c */
@@ -9254,596 +9290,1044 @@  static const unsigned CONST_TBL_b4cu_0[] = {
 /* Instruction operands.  */
 
 static int
-Operand_soffsetx4_decode (uint32 *valp)
+OperandSem_opnd_sem_soffsetx4_decode (uint32 *valp)
 {
-  unsigned soffsetx4_0, offset_0;
-  offset_0 = *valp & 0x3ffff;
-  soffsetx4_0 = 0x4 + ((((int) offset_0 << 14) >> 14) << 2);
-  *valp = soffsetx4_0;
+  unsigned soffsetx4_out_0;
+  unsigned soffsetx4_in_0;
+  soffsetx4_in_0 = *valp & 0x3ffff;
+  soffsetx4_out_0 = 0x4 + ((((int) soffsetx4_in_0 << 14) >> 14) << 2);
+  *valp = soffsetx4_out_0;
   return 0;
 }
 
 static int
-Operand_soffsetx4_encode (uint32 *valp)
+OperandSem_opnd_sem_soffsetx4_encode (uint32 *valp)
 {
-  unsigned offset_0, soffsetx4_0;
-  soffsetx4_0 = *valp;
-  offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
-  *valp = offset_0;
+  unsigned soffsetx4_in_0;
+  unsigned soffsetx4_out_0;
+  soffsetx4_out_0 = *valp;
+  soffsetx4_in_0 = ((soffsetx4_out_0 - 0x4) >> 2) & 0x3ffff;
+  *valp = soffsetx4_in_0;
   return 0;
 }
 
 static int
-Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
+OperandSem_opnd_sem_uimm12x8_decode (uint32 *valp)
 {
-  *valp -= (pc & ~0x3);
+  unsigned uimm12x8_out_0;
+  unsigned uimm12x8_in_0;
+  uimm12x8_in_0 = *valp & 0xfff;
+  uimm12x8_out_0 = uimm12x8_in_0 << 3;
+  *valp = uimm12x8_out_0;
   return 0;
 }
 
 static int
-Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
+OperandSem_opnd_sem_uimm12x8_encode (uint32 *valp)
 {
-  *valp += (pc & ~0x3);
+  unsigned uimm12x8_in_0;
+  unsigned uimm12x8_out_0;
+  uimm12x8_out_0 = *valp;
+  uimm12x8_in_0 = ((uimm12x8_out_0 >> 3) & 0xfff);
+  *valp = uimm12x8_in_0;
   return 0;
 }
 
 static int
-Operand_uimm12x8_decode (uint32 *valp)
+OperandSem_opnd_sem_simm4_decode (uint32 *valp)
 {
-  unsigned uimm12x8_0, imm12_0;
-  imm12_0 = *valp & 0xfff;
-  uimm12x8_0 = imm12_0 << 3;
-  *valp = uimm12x8_0;
+  unsigned simm4_out_0;
+  unsigned simm4_in_0;
+  simm4_in_0 = *valp & 0xf;
+  simm4_out_0 = ((int) simm4_in_0 << 28) >> 28;
+  *valp = simm4_out_0;
   return 0;
 }
 
 static int
-Operand_uimm12x8_encode (uint32 *valp)
+OperandSem_opnd_sem_simm4_encode (uint32 *valp)
 {
-  unsigned imm12_0, uimm12x8_0;
-  uimm12x8_0 = *valp;
-  imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
-  *valp = imm12_0;
+  unsigned simm4_in_0;
+  unsigned simm4_out_0;
+  simm4_out_0 = *valp;
+  simm4_in_0 = (simm4_out_0 & 0xf);
+  *valp = simm4_in_0;
   return 0;
 }
 
 static int
-Operand_simm4_decode (uint32 *valp)
+OperandSem_opnd_sem_AR_decode (uint32 *valp ATTRIBUTE_UNUSED)
 {
-  unsigned simm4_0, mn_0;
-  mn_0 = *valp & 0xf;
-  simm4_0 = ((int) mn_0 << 28) >> 28;
-  *valp = simm4_0;
   return 0;
 }
 
 static int
-Operand_simm4_encode (uint32 *valp)
+OperandSem_opnd_sem_AR_encode (uint32 *valp)
 {
-  unsigned mn_0, simm4_0;
-  simm4_0 = *valp;
-  mn_0 = (simm4_0 & 0xf);
-  *valp = mn_0;
-  return 0;
+  int error;
+  error = (*valp >= 32);
+  return error;
 }
 
 static int
-Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
+OperandSem_opnd_sem_AR_0_decode (uint32 *valp ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 static int
-Operand_arr_encode (uint32 *valp)
+OperandSem_opnd_sem_AR_0_encode (uint32 *valp)
 {
   int error;
-  error = (*valp & ~0xf) != 0;
+  error = (*valp >= 32);
   return error;
 }
 
 static int
-Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
+OperandSem_opnd_sem_AR_1_decode (uint32 *valp ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 static int
-Operand_ars_encode (uint32 *valp)
+OperandSem_opnd_sem_AR_1_encode (uint32 *valp)
 {
   int error;
-  error = (*valp & ~0xf) != 0;
+  error = (*valp >= 32);
   return error;
 }
 
 static int
-Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
+OperandSem_opnd_sem_AR_2_decode (uint32 *valp ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 static int
-Operand_art_encode (uint32 *valp)
+OperandSem_opnd_sem_AR_2_encode (uint32 *valp)
 {
   int error;
-  error = (*valp & ~0xf) != 0;
+  error = (*valp >= 32);
   return error;
 }
 
 static int
-Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
+OperandSem_opnd_sem_AR_3_decode (uint32 *valp ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 static int
-Operand_ar0_encode (uint32 *valp)
+OperandSem_opnd_sem_AR_3_encode (uint32 *valp)
 {
   int error;
-  error = (*valp & ~0x1f) != 0;
+  error = (*valp >= 32);
   return error;
 }
 
 static int
-Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
+OperandSem_opnd_sem_AR_4_decode (uint32 *valp ATTRIBUTE_UNUSED)
 {
   return 0;
 }
 
 static int
-Operand_ar4_encode (uint32 *valp)
+OperandSem_opnd_sem_AR_4_encode (uint32 *valp)
 {
   int error;
-  error = (*valp & ~0x1f) != 0;
+  error = (*valp >= 32);
   return error;
 }
 
 static int
-Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
+OperandSem_opnd_sem_immrx4_decode (uint32 *valp)
 {
+  unsigned immrx4_out_0;
+  unsigned immrx4_in_0;
+  immrx4_in_0 = *valp & 0xf;
+  immrx4_out_0 = (((0xfffffff) << 4) | immrx4_in_0) << 2;
+  *valp = immrx4_out_0;
   return 0;
 }
 
 static int
-Operand_ar8_encode (uint32 *valp)
+OperandSem_opnd_sem_immrx4_encode (uint32 *valp)
+{
+  unsigned immrx4_in_0;
+  unsigned immrx4_out_0;
+  immrx4_out_0 = *valp;
+  immrx4_in_0 = ((immrx4_out_0 >> 2) & 0xf);
+  *valp = immrx4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_decode (uint32 *valp)
+{
+  unsigned lsi4x4_out_0;
+  unsigned lsi4x4_in_0;
+  lsi4x4_in_0 = *valp & 0xf;
+  lsi4x4_out_0 = lsi4x4_in_0 << 2;
+  *valp = lsi4x4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_lsi4x4_encode (uint32 *valp)
+{
+  unsigned lsi4x4_in_0;
+  unsigned lsi4x4_out_0;
+  lsi4x4_out_0 = *valp;
+  lsi4x4_in_0 = ((lsi4x4_out_0 >> 2) & 0xf);
+  *valp = lsi4x4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_decode (uint32 *valp)
+{
+  unsigned simm7_out_0;
+  unsigned simm7_in_0;
+  simm7_in_0 = *valp & 0x7f;
+  simm7_out_0 = ((((-((((simm7_in_0 >> 6) & 1)) & (((simm7_in_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | simm7_in_0;
+  *valp = simm7_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm7_encode (uint32 *valp)
+{
+  unsigned simm7_in_0;
+  unsigned simm7_out_0;
+  simm7_out_0 = *valp;
+  simm7_in_0 = (simm7_out_0 & 0x7f);
+  *valp = simm7_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_decode (uint32 *valp)
+{
+  unsigned uimm6_out_0;
+  unsigned uimm6_in_0;
+  uimm6_in_0 = *valp & 0x3f;
+  uimm6_out_0 = 0x4 + (((0) << 6) | uimm6_in_0);
+  *valp = uimm6_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm6_encode (uint32 *valp)
+{
+  unsigned uimm6_in_0;
+  unsigned uimm6_out_0;
+  uimm6_out_0 = *valp;
+  uimm6_in_0 = (uimm6_out_0 - 0x4) & 0x3f;
+  *valp = uimm6_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_decode (uint32 *valp)
+{
+  unsigned ai4const_out_0;
+  unsigned ai4const_in_0;
+  ai4const_in_0 = *valp & 0xf;
+  ai4const_out_0 = CONST_TBL_ai4c_0[ai4const_in_0 & 0xf];
+  *valp = ai4const_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_ai4const_encode (uint32 *valp)
+{
+  unsigned ai4const_in_0;
+  unsigned ai4const_out_0;
+  ai4const_out_0 = *valp;
+  switch (ai4const_out_0)
+    {
+    case 0xffffffff: ai4const_in_0 = 0; break;
+    case 0x1: ai4const_in_0 = 0x1; break;
+    case 0x2: ai4const_in_0 = 0x2; break;
+    case 0x3: ai4const_in_0 = 0x3; break;
+    case 0x4: ai4const_in_0 = 0x4; break;
+    case 0x5: ai4const_in_0 = 0x5; break;
+    case 0x6: ai4const_in_0 = 0x6; break;
+    case 0x7: ai4const_in_0 = 0x7; break;
+    case 0x8: ai4const_in_0 = 0x8; break;
+    case 0x9: ai4const_in_0 = 0x9; break;
+    case 0xa: ai4const_in_0 = 0xa; break;
+    case 0xb: ai4const_in_0 = 0xb; break;
+    case 0xc: ai4const_in_0 = 0xc; break;
+    case 0xd: ai4const_in_0 = 0xd; break;
+    case 0xe: ai4const_in_0 = 0xe; break;
+    default: ai4const_in_0 = 0xf; break;
+    }
+  *valp = ai4const_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_decode (uint32 *valp)
+{
+  unsigned b4const_out_0;
+  unsigned b4const_in_0;
+  b4const_in_0 = *valp & 0xf;
+  b4const_out_0 = CONST_TBL_b4c_0[b4const_in_0 & 0xf];
+  *valp = b4const_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4const_encode (uint32 *valp)
+{
+  unsigned b4const_in_0;
+  unsigned b4const_out_0;
+  b4const_out_0 = *valp;
+  switch (b4const_out_0)
+    {
+    case 0xffffffff: b4const_in_0 = 0; break;
+    case 0x1: b4const_in_0 = 0x1; break;
+    case 0x2: b4const_in_0 = 0x2; break;
+    case 0x3: b4const_in_0 = 0x3; break;
+    case 0x4: b4const_in_0 = 0x4; break;
+    case 0x5: b4const_in_0 = 0x5; break;
+    case 0x6: b4const_in_0 = 0x6; break;
+    case 0x7: b4const_in_0 = 0x7; break;
+    case 0x8: b4const_in_0 = 0x8; break;
+    case 0xa: b4const_in_0 = 0x9; break;
+    case 0xc: b4const_in_0 = 0xa; break;
+    case 0x10: b4const_in_0 = 0xb; break;
+    case 0x20: b4const_in_0 = 0xc; break;
+    case 0x40: b4const_in_0 = 0xd; break;
+    case 0x80: b4const_in_0 = 0xe; break;
+    default: b4const_in_0 = 0xf; break;
+    }
+  *valp = b4const_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_decode (uint32 *valp)
+{
+  unsigned b4constu_out_0;
+  unsigned b4constu_in_0;
+  b4constu_in_0 = *valp & 0xf;
+  b4constu_out_0 = CONST_TBL_b4cu_0[b4constu_in_0 & 0xf];
+  *valp = b4constu_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_b4constu_encode (uint32 *valp)
+{
+  unsigned b4constu_in_0;
+  unsigned b4constu_out_0;
+  b4constu_out_0 = *valp;
+  switch (b4constu_out_0)
+    {
+    case 0x8000: b4constu_in_0 = 0; break;
+    case 0x10000: b4constu_in_0 = 0x1; break;
+    case 0x2: b4constu_in_0 = 0x2; break;
+    case 0x3: b4constu_in_0 = 0x3; break;
+    case 0x4: b4constu_in_0 = 0x4; break;
+    case 0x5: b4constu_in_0 = 0x5; break;
+    case 0x6: b4constu_in_0 = 0x6; break;
+    case 0x7: b4constu_in_0 = 0x7; break;
+    case 0x8: b4constu_in_0 = 0x8; break;
+    case 0xa: b4constu_in_0 = 0x9; break;
+    case 0xc: b4constu_in_0 = 0xa; break;
+    case 0x10: b4constu_in_0 = 0xb; break;
+    case 0x20: b4constu_in_0 = 0xc; break;
+    case 0x40: b4constu_in_0 = 0xd; break;
+    case 0x80: b4constu_in_0 = 0xe; break;
+    default: b4constu_in_0 = 0xf; break;
+    }
+  *valp = b4constu_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_decode (uint32 *valp)
+{
+  unsigned uimm8_out_0;
+  unsigned uimm8_in_0;
+  uimm8_in_0 = *valp & 0xff;
+  uimm8_out_0 = uimm8_in_0;
+  *valp = uimm8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8_encode (uint32 *valp)
+{
+  unsigned uimm8_in_0;
+  unsigned uimm8_out_0;
+  uimm8_out_0 = *valp;
+  uimm8_in_0 = (uimm8_out_0 & 0xff);
+  *valp = uimm8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_decode (uint32 *valp)
+{
+  unsigned uimm8x2_out_0;
+  unsigned uimm8x2_in_0;
+  uimm8x2_in_0 = *valp & 0xff;
+  uimm8x2_out_0 = uimm8x2_in_0 << 1;
+  *valp = uimm8x2_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x2_encode (uint32 *valp)
+{
+  unsigned uimm8x2_in_0;
+  unsigned uimm8x2_out_0;
+  uimm8x2_out_0 = *valp;
+  uimm8x2_in_0 = ((uimm8x2_out_0 >> 1) & 0xff);
+  *valp = uimm8x2_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_decode (uint32 *valp)
+{
+  unsigned uimm8x4_out_0;
+  unsigned uimm8x4_in_0;
+  uimm8x4_in_0 = *valp & 0xff;
+  uimm8x4_out_0 = uimm8x4_in_0 << 2;
+  *valp = uimm8x4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm8x4_encode (uint32 *valp)
+{
+  unsigned uimm8x4_in_0;
+  unsigned uimm8x4_out_0;
+  uimm8x4_out_0 = *valp;
+  uimm8x4_in_0 = ((uimm8x4_out_0 >> 2) & 0xff);
+  *valp = uimm8x4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_decode (uint32 *valp)
+{
+  unsigned uimm4x16_out_0;
+  unsigned uimm4x16_in_0;
+  uimm4x16_in_0 = *valp & 0xf;
+  uimm4x16_out_0 = uimm4x16_in_0 << 4;
+  *valp = uimm4x16_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm4x16_encode (uint32 *valp)
+{
+  unsigned uimm4x16_in_0;
+  unsigned uimm4x16_out_0;
+  uimm4x16_out_0 = *valp;
+  uimm4x16_in_0 = ((uimm4x16_out_0 >> 4) & 0xf);
+  *valp = uimm4x16_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_decode (uint32 *valp)
+{
+  unsigned simm8_out_0;
+  unsigned simm8_in_0;
+  simm8_in_0 = *valp & 0xff;
+  simm8_out_0 = ((int) simm8_in_0 << 24) >> 24;
+  *valp = simm8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8_encode (uint32 *valp)
+{
+  unsigned simm8_in_0;
+  unsigned simm8_out_0;
+  simm8_out_0 = *valp;
+  simm8_in_0 = (simm8_out_0 & 0xff);
+  *valp = simm8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_decode (uint32 *valp)
+{
+  unsigned simm8x256_out_0;
+  unsigned simm8x256_in_0;
+  simm8x256_in_0 = *valp & 0xff;
+  simm8x256_out_0 = (((int) simm8x256_in_0 << 24) >> 24) << 8;
+  *valp = simm8x256_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm8x256_encode (uint32 *valp)
+{
+  unsigned simm8x256_in_0;
+  unsigned simm8x256_out_0;
+  simm8x256_out_0 = *valp;
+  simm8x256_in_0 = ((simm8x256_out_0 >> 8) & 0xff);
+  *valp = simm8x256_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_decode (uint32 *valp)
+{
+  unsigned simm12b_out_0;
+  unsigned simm12b_in_0;
+  simm12b_in_0 = *valp & 0xfff;
+  simm12b_out_0 = ((int) simm12b_in_0 << 20) >> 20;
+  *valp = simm12b_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_simm12b_encode (uint32 *valp)
+{
+  unsigned simm12b_in_0;
+  unsigned simm12b_out_0;
+  simm12b_out_0 = *valp;
+  simm12b_in_0 = (simm12b_out_0 & 0xfff);
+  *valp = simm12b_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_decode (uint32 *valp)
+{
+  unsigned msalp32_out_0;
+  unsigned msalp32_in_0;
+  msalp32_in_0 = *valp & 0x1f;
+  msalp32_out_0 = 0x20 - msalp32_in_0;
+  *valp = msalp32_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_msalp32_encode (uint32 *valp)
+{
+  unsigned msalp32_in_0;
+  unsigned msalp32_out_0;
+  msalp32_out_0 = *valp;
+  msalp32_in_0 = (0x20 - msalp32_out_0) & 0x1f;
+  *valp = msalp32_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_decode (uint32 *valp)
+{
+  unsigned op2p1_out_0;
+  unsigned op2p1_in_0;
+  op2p1_in_0 = *valp & 0xf;
+  op2p1_out_0 = op2p1_in_0 + 0x1;
+  *valp = op2p1_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_op2p1_encode (uint32 *valp)
+{
+  unsigned op2p1_in_0;
+  unsigned op2p1_out_0;
+  op2p1_out_0 = *valp;
+  op2p1_in_0 = (op2p1_out_0 - 0x1) & 0xf;
+  *valp = op2p1_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_decode (uint32 *valp)
+{
+  unsigned label8_out_0;
+  unsigned label8_in_0;
+  label8_in_0 = *valp & 0xff;
+  label8_out_0 = 0x4 + (((int) label8_in_0 << 24) >> 24);
+  *valp = label8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label8_encode (uint32 *valp)
+{
+  unsigned label8_in_0;
+  unsigned label8_out_0;
+  label8_out_0 = *valp;
+  label8_in_0 = (label8_out_0 - 0x4) & 0xff;
+  *valp = label8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_ulabel8_decode (uint32 *valp)
+{
+  unsigned ulabel8_out_0;
+  unsigned ulabel8_in_0;
+  ulabel8_in_0 = *valp & 0xff;
+  ulabel8_out_0 = 0x4 + (((0) << 8) | ulabel8_in_0);
+  *valp = ulabel8_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_ulabel8_encode (uint32 *valp)
+{
+  unsigned ulabel8_in_0;
+  unsigned ulabel8_out_0;
+  ulabel8_out_0 = *valp;
+  ulabel8_in_0 = (ulabel8_out_0 - 0x4) & 0xff;
+  *valp = ulabel8_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_decode (uint32 *valp)
+{
+  unsigned label12_out_0;
+  unsigned label12_in_0;
+  label12_in_0 = *valp & 0xfff;
+  label12_out_0 = 0x4 + (((int) label12_in_0 << 20) >> 20);
+  *valp = label12_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_label12_encode (uint32 *valp)
+{
+  unsigned label12_in_0;
+  unsigned label12_out_0;
+  label12_out_0 = *valp;
+  label12_in_0 = (label12_out_0 - 0x4) & 0xfff;
+  *valp = label12_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_decode (uint32 *valp)
+{
+  unsigned soffset_out_0;
+  unsigned soffset_in_0;
+  soffset_in_0 = *valp & 0x3ffff;
+  soffset_out_0 = 0x4 + (((int) soffset_in_0 << 14) >> 14);
+  *valp = soffset_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_soffset_encode (uint32 *valp)
+{
+  unsigned soffset_in_0;
+  unsigned soffset_out_0;
+  soffset_out_0 = *valp;
+  soffset_in_0 = (soffset_out_0 - 0x4) & 0x3ffff;
+  *valp = soffset_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_decode (uint32 *valp)
+{
+  unsigned uimm16x4_out_0;
+  unsigned uimm16x4_in_0;
+  uimm16x4_in_0 = *valp & 0xffff;
+  uimm16x4_out_0 = (((0xffff) << 16) | uimm16x4_in_0) << 2;
+  *valp = uimm16x4_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_uimm16x4_encode (uint32 *valp)
+{
+  unsigned uimm16x4_in_0;
+  unsigned uimm16x4_out_0;
+  uimm16x4_out_0 = *valp;
+  uimm16x4_in_0 = (uimm16x4_out_0 >> 2) & 0xffff;
+  *valp = uimm16x4_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_decode (uint32 *valp)
+{
+  unsigned bbi_out_0;
+  unsigned bbi_in_0;
+  bbi_in_0 = *valp & 0x1f;
+  bbi_out_0 = (0 << 5) | bbi_in_0;
+  *valp = bbi_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_bbi_encode (uint32 *valp)
+{
+  unsigned bbi_in_0;
+  unsigned bbi_out_0;
+  bbi_out_0 = *valp;
+  bbi_in_0 = (bbi_out_0 & 0x1f);
+  *valp = bbi_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_decode (uint32 *valp)
+{
+  unsigned s_out_0;
+  unsigned s_in_0;
+  s_in_0 = *valp & 0xf;
+  s_out_0 = (0 << 4) | s_in_0;
+  *valp = s_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_s_encode (uint32 *valp)
+{
+  unsigned s_in_0;
+  unsigned s_out_0;
+  s_out_0 = *valp;
+  s_in_0 = (s_out_0 & 0xf);
+  *valp = s_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_decode (uint32 *valp)
+{
+  unsigned immt_out_0;
+  unsigned immt_in_0;
+  immt_in_0 = *valp & 0xf;
+  immt_out_0 = immt_in_0;
+  *valp = immt_out_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_immt_encode (uint32 *valp)
+{
+  unsigned immt_in_0;
+  unsigned immt_out_0;
+  immt_out_0 = *valp;
+  immt_in_0 = immt_out_0 & 0xf;
+  *valp = immt_in_0;
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR_decode (uint32 *valp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+static int
+OperandSem_opnd_sem_BR_encode (uint32 *valp)
 {
   int error;
-  error = (*valp & ~0x1f) != 0;
+  error = (*valp >= 16);
   return error;
 }
 
 static int
-Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
+OperandSem_opnd_sem_BR2_decode (uint32 *valp)
 {
+  *valp = *valp << 1;
   return 0;
 }
 
 static int
-Operand_ar12_encode (uint32 *valp)
+OperandSem_opnd_sem_BR2_encode (uint32 *valp)
 {
   int error;
-  error = (*valp & ~0x1f) != 0;
+  error = (*valp >= 16) || ((*valp & 1) != 0);
+  *valp = *valp >> 1;
   return error;
 }
 
 static int
-Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
+OperandSem_opnd_sem_BR4_decode (uint32 *valp)
 {
+  *valp = *valp << 2;
   return 0;
 }
 
 static int
-Operand_ars_entry_encode (uint32 *valp)
+OperandSem_opnd_sem_BR4_encode (uint32 *valp)
 {
   int error;
-  error = (*valp & ~0x1f) != 0;
+  error = (*valp >= 16) || ((*valp & 3) != 0);
+  *valp = *valp >> 2;
   return error;
 }
 
 static int
-Operand_immrx4_decode (uint32 *valp)
+OperandSem_opnd_sem_BR8_decode (uint32 *valp)
 {
-  unsigned immrx4_0, r_0;
-  r_0 = *valp & 0xf;
-  immrx4_0 = (((0xfffffff) << 4) | r_0) << 2;
-  *valp = immrx4_0;
+  *valp = *valp << 3;
   return 0;
 }
 
 static int
-Operand_immrx4_encode (uint32 *valp)
+OperandSem_opnd_sem_BR8_encode (uint32 *valp)
 {
-  unsigned r_0, immrx4_0;
-  immrx4_0 = *valp;
-  r_0 = ((immrx4_0 >> 2) & 0xf);
-  *valp = r_0;
-  return 0;
+  int error;
+  error = (*valp >= 16) || ((*valp & 7) != 0);
+  *valp = *valp >> 3;
+  return error;
 }
 
 static int
-Operand_lsi4x4_decode (uint32 *valp)
+OperandSem_opnd_sem_BR16_decode (uint32 *valp)
 {
-  unsigned lsi4x4_0, r_0;
-  r_0 = *valp & 0xf;
-  lsi4x4_0 = r_0 << 2;
-  *valp = lsi4x4_0;
+  *valp = *valp << 4;
   return 0;
 }
 
 static int
-Operand_lsi4x4_encode (uint32 *valp)
+OperandSem_opnd_sem_BR16_encode (uint32 *valp)
 {
-  unsigned r_0, lsi4x4_0;
-  lsi4x4_0 = *valp;
-  r_0 = ((lsi4x4_0 >> 2) & 0xf);
-  *valp = r_0;
-  return 0;
+  int error;
+  error = (*valp >= 16) || ((*valp & 15) != 0);
+  *valp = *valp >> 4;
+  return error;
 }
 
 static int
-Operand_simm7_decode (uint32 *valp)
+OperandSem_opnd_sem_tp7_decode (uint32 *valp)
 {
-  unsigned simm7_0, imm7_0;
-  imm7_0 = *valp & 0x7f;
-  simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
-  *valp = simm7_0;
+  unsigned tp7_out_0;
+  unsigned tp7_in_0;
+  tp7_in_0 = *valp & 0xf;
+  tp7_out_0 = tp7_in_0 + 0x7;
+  *valp = tp7_out_0;
   return 0;
 }
 
 static int
-Operand_simm7_encode (uint32 *valp)
+OperandSem_opnd_sem_tp7_encode (uint32 *valp)
 {
-  unsigned imm7_0, simm7_0;
-  simm7_0 = *valp;
-  imm7_0 = (simm7_0 & 0x7f);
-  *valp = imm7_0;
+  unsigned tp7_in_0;
+  unsigned tp7_out_0;
+  tp7_out_0 = *valp;
+  tp7_in_0 = (tp7_out_0 - 0x7) & 0xf;
+  *valp = tp7_in_0;
   return 0;
 }
 
 static int
-Operand_uimm6_decode (uint32 *valp)
+OperandSem_opnd_sem_xt_wbr15_label_decode (uint32 *valp)
 {
-  unsigned uimm6_0, imm6_0;
-  imm6_0 = *valp & 0x3f;
-  uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
-  *valp = uimm6_0;
+  unsigned xt_wbr15_label_out_0;
+  unsigned xt_wbr15_label_in_0;
+  xt_wbr15_label_in_0 = *valp & 0x7fff;
+  xt_wbr15_label_out_0 = 0x4 + (((int) xt_wbr15_label_in_0 << 17) >> 17);
+  *valp = xt_wbr15_label_out_0;
   return 0;
 }
 
 static int
-Operand_uimm6_encode (uint32 *valp)
+OperandSem_opnd_sem_xt_wbr15_label_encode (uint32 *valp)
 {
-  unsigned imm6_0, uimm6_0;
-  uimm6_0 = *valp;
-  imm6_0 = (uimm6_0 - 0x4) & 0x3f;
-  *valp = imm6_0;
+  unsigned xt_wbr15_label_in_0;
+  unsigned xt_wbr15_label_out_0;
+  xt_wbr15_label_out_0 = *valp;
+  xt_wbr15_label_in_0 = (xt_wbr15_label_out_0 - 0x4) & 0x7fff;
+  *valp = xt_wbr15_label_in_0;
   return 0;
 }
 
 static int
-Operand_uimm6_ator (uint32 *valp, uint32 pc)
+OperandSem_opnd_sem_ae_samt32_decode (uint32 *valp)
 {
-  *valp -= pc;
+  unsigned ae_samt32_out_0;
+  unsigned ae_samt32_in_0;
+  ae_samt32_in_0 = *valp & 0x1f;
+  ae_samt32_out_0 = (0 << 5) | ae_samt32_in_0;
+  *valp = ae_samt32_out_0;
   return 0;
 }
 
 static int
-Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
+OperandSem_opnd_sem_ae_samt32_encode (uint32 *valp)
 {
-  *valp += pc;
+  unsigned ae_samt32_in_0;
+  unsigned ae_samt32_out_0;
+  ae_samt32_out_0 = *valp;
+  ae_samt32_in_0 = (ae_samt32_out_0 & 0x1f);
+  *valp = ae_samt32_in_0;
   return 0;
 }
 
 static int
-Operand_ai4const_decode (uint32 *valp)
+OperandSem_opnd_sem_AE_PR_decode (uint32 *valp ATTRIBUTE_UNUSED)
 {
-  unsigned ai4const_0, t_0;
-  t_0 = *valp & 0xf;
-  ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
-  *valp = ai4const_0;
   return 0;
 }
 
 static int
-Operand_ai4const_encode (uint32 *valp)
+OperandSem_opnd_sem_AE_PR_encode (uint32 *valp)
 {
-  unsigned t_0, ai4const_0;
-  ai4const_0 = *valp;
-  switch (ai4const_0)
-    {
-    case 0xffffffff: t_0 = 0; break;
-    case 0x1: t_0 = 0x1; break;
-    case 0x2: t_0 = 0x2; break;
-    case 0x3: t_0 = 0x3; break;
-    case 0x4: t_0 = 0x4; break;
-    case 0x5: t_0 = 0x5; break;
-    case 0x6: t_0 = 0x6; break;
-    case 0x7: t_0 = 0x7; break;
-    case 0x8: t_0 = 0x8; break;
-    case 0x9: t_0 = 0x9; break;
-    case 0xa: t_0 = 0xa; break;
-    case 0xb: t_0 = 0xb; break;
-    case 0xc: t_0 = 0xc; break;
-    case 0xd: t_0 = 0xd; break;
-    case 0xe: t_0 = 0xe; break;
-    default: t_0 = 0xf; break;
-    }
-  *valp = t_0;
-  return 0;
-}
-
-static int
-Operand_b4const_decode (uint32 *valp)
-{
-  unsigned b4const_0, r_0;
-  r_0 = *valp & 0xf;
-  b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
-  *valp = b4const_0;
-  return 0;
-}
-
-static int
-Operand_b4const_encode (uint32 *valp)
-{
-  unsigned r_0, b4const_0;
-  b4const_0 = *valp;
-  switch (b4const_0)
-    {
-    case 0xffffffff: r_0 = 0; break;
-    case 0x1: r_0 = 0x1; break;
-    case 0x2: r_0 = 0x2; break;
-    case 0x3: r_0 = 0x3; break;
-    case 0x4: r_0 = 0x4; break;
-    case 0x5: r_0 = 0x5; break;
-    case 0x6: r_0 = 0x6; break;
-    case 0x7: r_0 = 0x7; break;
-    case 0x8: r_0 = 0x8; break;
-    case 0xa: r_0 = 0x9; break;
-    case 0xc: r_0 = 0xa; break;
-    case 0x10: r_0 = 0xb; break;
-    case 0x20: r_0 = 0xc; break;
-    case 0x40: r_0 = 0xd; break;
-    case 0x80: r_0 = 0xe; break;
-    default: r_0 = 0xf; break;
-    }
-  *valp = r_0;
-  return 0;
-}
-
-static int
-Operand_b4constu_decode (uint32 *valp)
-{
-  unsigned b4constu_0, r_0;
-  r_0 = *valp & 0xf;
-  b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
-  *valp = b4constu_0;
-  return 0;
-}
-
-static int
-Operand_b4constu_encode (uint32 *valp)
-{
-  unsigned r_0, b4constu_0;
-  b4constu_0 = *valp;
-  switch (b4constu_0)
-    {
-    case 0x8000: r_0 = 0; break;
-    case 0x10000: r_0 = 0x1; break;
-    case 0x2: r_0 = 0x2; break;
-    case 0x3: r_0 = 0x3; break;
-    case 0x4: r_0 = 0x4; break;
-    case 0x5: r_0 = 0x5; break;
-    case 0x6: r_0 = 0x6; break;
-    case 0x7: r_0 = 0x7; break;
-    case 0x8: r_0 = 0x8; break;
-    case 0xa: r_0 = 0x9; break;
-    case 0xc: r_0 = 0xa; break;
-    case 0x10: r_0 = 0xb; break;
-    case 0x20: r_0 = 0xc; break;
-    case 0x40: r_0 = 0xd; break;
-    case 0x80: r_0 = 0xe; break;
-    default: r_0 = 0xf; break;
-    }
-  *valp = r_0;
-  return 0;
-}
-
-static int
-Operand_uimm8_decode (uint32 *valp)
-{
-  unsigned uimm8_0, imm8_0;
-  imm8_0 = *valp & 0xff;
-  uimm8_0 = imm8_0;
-  *valp = uimm8_0;
-  return 0;
-}
-
-static int
-Operand_uimm8_encode (uint32 *valp)
-{
-  unsigned imm8_0, uimm8_0;
-  uimm8_0 = *valp;
-  imm8_0 = (uimm8_0 & 0xff);
-  *valp = imm8_0;
-  return 0;
-}
-
-static int
-Operand_uimm8x2_decode (uint32 *valp)
-{
-  unsigned uimm8x2_0, imm8_0;
-  imm8_0 = *valp & 0xff;
-  uimm8x2_0 = imm8_0 << 1;
-  *valp = uimm8x2_0;
-  return 0;
-}
-
-static int
-Operand_uimm8x2_encode (uint32 *valp)
-{
-  unsigned imm8_0, uimm8x2_0;
-  uimm8x2_0 = *valp;
-  imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
-  *valp = imm8_0;
-  return 0;
+  int error;
+  error = (*valp >= 8);
+  return error;
 }
 
 static int
-Operand_uimm8x4_decode (uint32 *valp)
+OperandSem_opnd_sem_AE_QR_decode (uint32 *valp ATTRIBUTE_UNUSED)
 {
-  unsigned uimm8x4_0, imm8_0;
-  imm8_0 = *valp & 0xff;
-  uimm8x4_0 = imm8_0 << 2;
-  *valp = uimm8x4_0;
   return 0;
 }
 
 static int
-Operand_uimm8x4_encode (uint32 *valp)
+OperandSem_opnd_sem_AE_QR_encode (uint32 *valp)
 {
-  unsigned imm8_0, uimm8x4_0;
-  uimm8x4_0 = *valp;
-  imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
-  *valp = imm8_0;
-  return 0;
+  int error;
+  error = (*valp >= 4);
+  return error;
 }
 
 static int
-Operand_uimm4x16_decode (uint32 *valp)
+OperandSem_opnd_sem_ae_lsimm16_decode (uint32 *valp)
 {
-  unsigned uimm4x16_0, op2_0;
-  op2_0 = *valp & 0xf;
-  uimm4x16_0 = op2_0 << 4;
-  *valp = uimm4x16_0;
+  unsigned ae_lsimm16_out_0;
+  unsigned ae_lsimm16_in_0;
+  ae_lsimm16_in_0 = *valp & 0xf;
+  ae_lsimm16_out_0 = (((int) ae_lsimm16_in_0 << 28) >> 28) << 1;
+  *valp = ae_lsimm16_out_0;
   return 0;
 }
 
 static int
-Operand_uimm4x16_encode (uint32 *valp)
+OperandSem_opnd_sem_ae_lsimm16_encode (uint32 *valp)
 {
-  unsigned op2_0, uimm4x16_0;
-  uimm4x16_0 = *valp;
-  op2_0 = ((uimm4x16_0 >> 4) & 0xf);
-  *valp = op2_0;
+  unsigned ae_lsimm16_in_0;
+  unsigned ae_lsimm16_out_0;
+  ae_lsimm16_out_0 = *valp;
+  ae_lsimm16_in_0 = ((ae_lsimm16_out_0 >> 1) & 0xf);
+  *valp = ae_lsimm16_in_0;
   return 0;
 }
 
 static int
-Operand_simm8_decode (uint32 *valp)
+OperandSem_opnd_sem_ae_lsimm32_decode (uint32 *valp)
 {
-  unsigned simm8_0, imm8_0;
-  imm8_0 = *valp & 0xff;
-  simm8_0 = ((int) imm8_0 << 24) >> 24;
-  *valp = simm8_0;
+  unsigned ae_lsimm32_out_0;
+  unsigned ae_lsimm32_in_0;
+  ae_lsimm32_in_0 = *valp & 0xf;
+  ae_lsimm32_out_0 = (((int) ae_lsimm32_in_0 << 28) >> 28) << 2;
+  *valp = ae_lsimm32_out_0;
   return 0;
 }
 
 static int
-Operand_simm8_encode (uint32 *valp)
+OperandSem_opnd_sem_ae_lsimm32_encode (uint32 *valp)
 {
-  unsigned imm8_0, simm8_0;
-  simm8_0 = *valp;
-  imm8_0 = (simm8_0 & 0xff);
-  *valp = imm8_0;
+  unsigned ae_lsimm32_in_0;
+  unsigned ae_lsimm32_out_0;
+  ae_lsimm32_out_0 = *valp;
+  ae_lsimm32_in_0 = ((ae_lsimm32_out_0 >> 2) & 0xf);
+  *valp = ae_lsimm32_in_0;
   return 0;
 }
 
 static int
-Operand_simm8x256_decode (uint32 *valp)
+OperandSem_opnd_sem_ae_lsimm64_decode (uint32 *valp)
 {
-  unsigned simm8x256_0, imm8_0;
-  imm8_0 = *valp & 0xff;
-  simm8x256_0 = (((int) imm8_0 << 24) >> 24) << 8;
-  *valp = simm8x256_0;
+  unsigned ae_lsimm64_out_0;
+  unsigned ae_lsimm64_in_0;
+  ae_lsimm64_in_0 = *valp & 0xf;
+  ae_lsimm64_out_0 = (((int) ae_lsimm64_in_0 << 28) >> 28) << 3;
+  *valp = ae_lsimm64_out_0;
   return 0;
 }
 
 static int
-Operand_simm8x256_encode (uint32 *valp)
+OperandSem_opnd_sem_ae_lsimm64_encode (uint32 *valp)
 {
-  unsigned imm8_0, simm8x256_0;
-  simm8x256_0 = *valp;
-  imm8_0 = ((simm8x256_0 >> 8) & 0xff);
-  *valp = imm8_0;
+  unsigned ae_lsimm64_in_0;
+  unsigned ae_lsimm64_out_0;
+  ae_lsimm64_out_0 = *valp;
+  ae_lsimm64_in_0 = ((ae_lsimm64_out_0 >> 3) & 0xf);
+  *valp = ae_lsimm64_in_0;
   return 0;
 }
 
 static int
-Operand_simm12b_decode (uint32 *valp)
+OperandSem_opnd_sem_ae_samt64_decode (uint32 *valp)
 {
-  unsigned simm12b_0, imm12b_0;
-  imm12b_0 = *valp & 0xfff;
-  simm12b_0 = ((int) imm12b_0 << 20) >> 20;
-  *valp = simm12b_0;
+  unsigned ae_samt64_out_0;
+  unsigned ae_samt64_in_0;
+  ae_samt64_in_0 = *valp & 0x3f;
+  ae_samt64_out_0 = (0 << 6) | ae_samt64_in_0;
+  *valp = ae_samt64_out_0;
   return 0;
 }
 
 static int
-Operand_simm12b_encode (uint32 *valp)
+OperandSem_opnd_sem_ae_samt64_encode (uint32 *valp)
 {
-  unsigned imm12b_0, simm12b_0;
-  simm12b_0 = *valp;
-  imm12b_0 = (simm12b_0 & 0xfff);
-  *valp = imm12b_0;
+  unsigned ae_samt64_in_0;
+  unsigned ae_samt64_out_0;
+  ae_samt64_out_0 = *valp;
+  ae_samt64_in_0 = (ae_samt64_out_0 & 0x3f);
+  *valp = ae_samt64_in_0;
   return 0;
 }
 
 static int
-Operand_msalp32_decode (uint32 *valp)
+OperandSem_opnd_sem_ae_ohba_decode (uint32 *valp)
 {
-  unsigned msalp32_0, sal_0;
-  sal_0 = *valp & 0x1f;
-  msalp32_0 = 0x20 - sal_0;
-  *valp = msalp32_0;
+  unsigned ae_ohba_out_0;
+  unsigned ae_ohba_in_0;
+  ae_ohba_in_0 = *valp & 0xf;
+  ae_ohba_out_0 = (0 << 5) | (((((ae_ohba_in_0 & 0xf))) == 0) << 4) | ((ae_ohba_in_0 & 0xf));
+  *valp = ae_ohba_out_0;
   return 0;
 }
 
 static int
-Operand_msalp32_encode (uint32 *valp)
+OperandSem_opnd_sem_ae_ohba_encode (uint32 *valp)
 {
-  unsigned sal_0, msalp32_0;
-  msalp32_0 = *valp;
-  sal_0 = (0x20 - msalp32_0) & 0x1f;
-  *valp = sal_0;
+  unsigned ae_ohba_in_0;
+  unsigned ae_ohba_out_0;
+  ae_ohba_out_0 = *valp;
+  ae_ohba_in_0 = (ae_ohba_out_0 & 0xf);
+  *valp = ae_ohba_in_0;
   return 0;
 }
 
 static int
-Operand_op2p1_decode (uint32 *valp)
+Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
 {
-  unsigned op2p1_0, op2_0;
-  op2_0 = *valp & 0xf;
-  op2p1_0 = op2_0 + 0x1;
-  *valp = op2p1_0;
+  *valp -= (pc & ~0x3);
   return 0;
 }
 
 static int
-Operand_op2p1_encode (uint32 *valp)
+Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
 {
-  unsigned op2_0, op2p1_0;
-  op2p1_0 = *valp;
-  op2_0 = (op2p1_0 - 0x1) & 0xf;
-  *valp = op2_0;
+  *valp += (pc & ~0x3);
   return 0;
 }
 
 static int
-Operand_label8_decode (uint32 *valp)
+Operand_uimm6_ator (uint32 *valp, uint32 pc)
 {
-  unsigned label8_0, imm8_0;
-  imm8_0 = *valp & 0xff;
-  label8_0 = 0x4 + (((int) imm8_0 << 24) >> 24);
-  *valp = label8_0;
+  *valp -= pc;
   return 0;
 }
 
 static int
-Operand_label8_encode (uint32 *valp)
+Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
 {
-  unsigned imm8_0, label8_0;
-  label8_0 = *valp;
-  imm8_0 = (label8_0 - 0x4) & 0xff;
-  *valp = imm8_0;
+  *valp += pc;
   return 0;
 }
 
@@ -9861,26 +10345,6 @@  Operand_label8_rtoa (uint32 *valp, uint32 pc)
   return 0;
 }
 
-static int
-Operand_ulabel8_decode (uint32 *valp)
-{
-  unsigned ulabel8_0, imm8_0;
-  imm8_0 = *valp & 0xff;
-  ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
-  *valp = ulabel8_0;
-  return 0;
-}
-
-static int
-Operand_ulabel8_encode (uint32 *valp)
-{
-  unsigned imm8_0, ulabel8_0;
-  ulabel8_0 = *valp;
-  imm8_0 = (ulabel8_0 - 0x4) & 0xff;
-  *valp = imm8_0;
-  return 0;
-}
-
 static int
 Operand_ulabel8_ator (uint32 *valp, uint32 pc)
 {
@@ -9895,26 +10359,6 @@  Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
   return 0;
 }
 
-static int
-Operand_label12_decode (uint32 *valp)
-{
-  unsigned label12_0, imm12_0;
-  imm12_0 = *valp & 0xfff;
-  label12_0 = 0x4 + (((int) imm12_0 << 20) >> 20);
-  *valp = label12_0;
-  return 0;
-}
-
-static int
-Operand_label12_encode (uint32 *valp)
-{
-  unsigned imm12_0, label12_0;
-  label12_0 = *valp;
-  imm12_0 = (label12_0 - 0x4) & 0xfff;
-  *valp = imm12_0;
-  return 0;
-}
-
 static int
 Operand_label12_ator (uint32 *valp, uint32 pc)
 {
@@ -9929,26 +10373,6 @@  Operand_label12_rtoa (uint32 *valp, uint32 pc)
   return 0;
 }
 
-static int
-Operand_soffset_decode (uint32 *valp)
-{
-  unsigned soffset_0, offset_0;
-  offset_0 = *valp & 0x3ffff;
-  soffset_0 = 0x4 + (((int) offset_0 << 14) >> 14);
-  *valp = soffset_0;
-  return 0;
-}
-
-static int
-Operand_soffset_encode (uint32 *valp)
-{
-  unsigned offset_0, soffset_0;
-  soffset_0 = *valp;
-  offset_0 = (soffset_0 - 0x4) & 0x3ffff;
-  *valp = offset_0;
-  return 0;
-}
-
 static int
 Operand_soffset_ator (uint32 *valp, uint32 pc)
 {
@@ -9963,26 +10387,6 @@  Operand_soffset_rtoa (uint32 *valp, uint32 pc)
   return 0;
 }
 
-static int
-Operand_uimm16x4_decode (uint32 *valp)
-{
-  unsigned uimm16x4_0, imm16_0;
-  imm16_0 = *valp & 0xffff;
-  uimm16x4_0 = (((0xffff) << 16) | imm16_0) << 2;
-  *valp = uimm16x4_0;
-  return 0;
-}
-
-static int
-Operand_uimm16x4_encode (uint32 *valp)
-{
-  unsigned imm16_0, uimm16x4_0;
-  uimm16x4_0 = *valp;
-  imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
-  *valp = imm16_0;
-  return 0;
-}
-
 static int
 Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
 {
@@ -9997,336 +10401,6 @@  Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
   return 0;
 }
 
-static int
-Operand_immt_decode (uint32 *valp)
-{
-  unsigned immt_0, t_0;
-  t_0 = *valp & 0xf;
-  immt_0 = t_0;
-  *valp = immt_0;
-  return 0;
-}
-
-static int
-Operand_immt_encode (uint32 *valp)
-{
-  unsigned t_0, immt_0;
-  immt_0 = *valp;
-  t_0 = immt_0 & 0xf;
-  *valp = t_0;
-  return 0;
-}
-
-static int
-Operand_imms_decode (uint32 *valp)
-{
-  unsigned imms_0, s_0;
-  s_0 = *valp & 0xf;
-  imms_0 = s_0;
-  *valp = imms_0;
-  return 0;
-}
-
-static int
-Operand_imms_encode (uint32 *valp)
-{
-  unsigned s_0, imms_0;
-  imms_0 = *valp;
-  s_0 = imms_0 & 0xf;
-  *valp = s_0;
-  return 0;
-}
-
-static int
-Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
-  return 0;
-}
-
-static int
-Operand_bt_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~0xf) != 0;
-  return error;
-}
-
-static int
-Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
-  return 0;
-}
-
-static int
-Operand_bs_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~0xf) != 0;
-  return error;
-}
-
-static int
-Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
-  return 0;
-}
-
-static int
-Operand_br_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~0xf) != 0;
-  return error;
-}
-
-static int
-Operand_bt2_decode (uint32 *valp)
-{
-  *valp = *valp << 1;
-  return 0;
-}
-
-static int
-Operand_bt2_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~(0x7 << 1)) != 0;
-  *valp = *valp >> 1;
-  return error;
-}
-
-static int
-Operand_bs2_decode (uint32 *valp)
-{
-  *valp = *valp << 1;
-  return 0;
-}
-
-static int
-Operand_bs2_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~(0x7 << 1)) != 0;
-  *valp = *valp >> 1;
-  return error;
-}
-
-static int
-Operand_br2_decode (uint32 *valp)
-{
-  *valp = *valp << 1;
-  return 0;
-}
-
-static int
-Operand_br2_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~(0x7 << 1)) != 0;
-  *valp = *valp >> 1;
-  return error;
-}
-
-static int
-Operand_bt4_decode (uint32 *valp)
-{
-  *valp = *valp << 2;
-  return 0;
-}
-
-static int
-Operand_bt4_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~(0x3 << 2)) != 0;
-  *valp = *valp >> 2;
-  return error;
-}
-
-static int
-Operand_bs4_decode (uint32 *valp)
-{
-  *valp = *valp << 2;
-  return 0;
-}
-
-static int
-Operand_bs4_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~(0x3 << 2)) != 0;
-  *valp = *valp >> 2;
-  return error;
-}
-
-static int
-Operand_br4_decode (uint32 *valp)
-{
-  *valp = *valp << 2;
-  return 0;
-}
-
-static int
-Operand_br4_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~(0x3 << 2)) != 0;
-  *valp = *valp >> 2;
-  return error;
-}
-
-static int
-Operand_bt8_decode (uint32 *valp)
-{
-  *valp = *valp << 3;
-  return 0;
-}
-
-static int
-Operand_bt8_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~(0x1 << 3)) != 0;
-  *valp = *valp >> 3;
-  return error;
-}
-
-static int
-Operand_bs8_decode (uint32 *valp)
-{
-  *valp = *valp << 3;
-  return 0;
-}
-
-static int
-Operand_bs8_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~(0x1 << 3)) != 0;
-  *valp = *valp >> 3;
-  return error;
-}
-
-static int
-Operand_br8_decode (uint32 *valp)
-{
-  *valp = *valp << 3;
-  return 0;
-}
-
-static int
-Operand_br8_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~(0x1 << 3)) != 0;
-  *valp = *valp >> 3;
-  return error;
-}
-
-static int
-Operand_bt16_decode (uint32 *valp)
-{
-  *valp = *valp << 4;
-  return 0;
-}
-
-static int
-Operand_bt16_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~(0 << 4)) != 0;
-  *valp = *valp >> 4;
-  return error;
-}
-
-static int
-Operand_bs16_decode (uint32 *valp)
-{
-  *valp = *valp << 4;
-  return 0;
-}
-
-static int
-Operand_bs16_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~(0 << 4)) != 0;
-  *valp = *valp >> 4;
-  return error;
-}
-
-static int
-Operand_br16_decode (uint32 *valp)
-{
-  *valp = *valp << 4;
-  return 0;
-}
-
-static int
-Operand_br16_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~(0 << 4)) != 0;
-  *valp = *valp >> 4;
-  return error;
-}
-
-static int
-Operand_brall_decode (uint32 *valp)
-{
-  *valp = *valp << 4;
-  return 0;
-}
-
-static int
-Operand_brall_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~(0 << 4)) != 0;
-  *valp = *valp >> 4;
-  return error;
-}
-
-static int
-Operand_tp7_decode (uint32 *valp)
-{
-  unsigned tp7_0, t_0;
-  t_0 = *valp & 0xf;
-  tp7_0 = t_0 + 0x7;
-  *valp = tp7_0;
-  return 0;
-}
-
-static int
-Operand_tp7_encode (uint32 *valp)
-{
-  unsigned t_0, tp7_0;
-  tp7_0 = *valp;
-  t_0 = (tp7_0 - 0x7) & 0xf;
-  *valp = t_0;
-  return 0;
-}
-
-static int
-Operand_xt_wbr15_label_decode (uint32 *valp)
-{
-  unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
-  xt_wbr15_imm_0 = *valp & 0x7fff;
-  xt_wbr15_label_0 = 0x4 + (((int) xt_wbr15_imm_0 << 17) >> 17);
-  *valp = xt_wbr15_label_0;
-  return 0;
-}
-
-static int
-Operand_xt_wbr15_label_encode (uint32 *valp)
-{
-  unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
-  xt_wbr15_label_0 = *valp;
-  xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
-  *valp = xt_wbr15_imm_0;
-  return 0;
-}
-
 static int
 Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
 {
@@ -10341,26 +10415,6 @@  Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
   return 0;
 }
 
-static int
-Operand_xt_wbr18_label_decode (uint32 *valp)
-{
-  unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
-  xt_wbr18_imm_0 = *valp & 0x3ffff;
-  xt_wbr18_label_0 = 0x4 + (((int) xt_wbr18_imm_0 << 14) >> 14);
-  *valp = xt_wbr18_label_0;
-  return 0;
-}
-
-static int
-Operand_xt_wbr18_label_encode (uint32 *valp)
-{
-  unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
-  xt_wbr18_label_0 = *valp;
-  xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
-  *valp = xt_wbr18_imm_0;
-  return 0;
-}
-
 static int
 Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
 {
@@ -10375,481 +10429,323 @@  Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
   return 0;
 }
 
-static int
-Operand_ae_samt32_decode (uint32 *valp)
-{
-  unsigned ae_samt32_0, ftsf14_0;
-  ftsf14_0 = *valp & 0x1f;
-  ae_samt32_0 = (0 << 5) | ftsf14_0;
-  *valp = ae_samt32_0;
-  return 0;
-}
-
-static int
-Operand_ae_samt32_encode (uint32 *valp)
-{
-  unsigned ftsf14_0, ae_samt32_0;
-  ae_samt32_0 = *valp;
-  ftsf14_0 = (ae_samt32_0 & 0x1f);
-  *valp = ftsf14_0;
-  return 0;
-}
-
-static int
-Operand_pr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
-  return 0;
-}
-
-static int
-Operand_pr0_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~0x7) != 0;
-  return error;
-}
-
-static int
-Operand_qr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
-  return 0;
-}
-
-static int
-Operand_qr0_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~0x3) != 0;
-  return error;
-}
-
-static int
-Operand_ae_lsimm16_decode (uint32 *valp)
-{
-  unsigned ae_lsimm16_0, t_0;
-  t_0 = *valp & 0xf;
-  ae_lsimm16_0 = (((int) t_0 << 28) >> 28) << 1;
-  *valp = ae_lsimm16_0;
-  return 0;
-}
-
-static int
-Operand_ae_lsimm16_encode (uint32 *valp)
-{
-  unsigned t_0, ae_lsimm16_0;
-  ae_lsimm16_0 = *valp;
-  t_0 = ((ae_lsimm16_0 >> 1) & 0xf);
-  *valp = t_0;
-  return 0;
-}
-
-static int
-Operand_ae_lsimm32_decode (uint32 *valp)
-{
-  unsigned ae_lsimm32_0, t_0;
-  t_0 = *valp & 0xf;
-  ae_lsimm32_0 = (((int) t_0 << 28) >> 28) << 2;
-  *valp = ae_lsimm32_0;
-  return 0;
-}
-
-static int
-Operand_ae_lsimm32_encode (uint32 *valp)
-{
-  unsigned t_0, ae_lsimm32_0;
-  ae_lsimm32_0 = *valp;
-  t_0 = ((ae_lsimm32_0 >> 2) & 0xf);
-  *valp = t_0;
-  return 0;
-}
-
-static int
-Operand_ae_lsimm64_decode (uint32 *valp)
-{
-  unsigned ae_lsimm64_0, t_0;
-  t_0 = *valp & 0xf;
-  ae_lsimm64_0 = (((int) t_0 << 28) >> 28) << 3;
-  *valp = ae_lsimm64_0;
-  return 0;
-}
-
-static int
-Operand_ae_lsimm64_encode (uint32 *valp)
-{
-  unsigned t_0, ae_lsimm64_0;
-  ae_lsimm64_0 = *valp;
-  t_0 = ((ae_lsimm64_0 >> 3) & 0xf);
-  *valp = t_0;
-  return 0;
-}
-
-static int
-Operand_ae_samt64_decode (uint32 *valp)
-{
-  unsigned ae_samt64_0, ae_samt_s_t_0;
-  ae_samt_s_t_0 = *valp & 0x3f;
-  ae_samt64_0 = (0 << 6) | ae_samt_s_t_0;
-  *valp = ae_samt64_0;
-  return 0;
-}
-
-static int
-Operand_ae_samt64_encode (uint32 *valp)
-{
-  unsigned ae_samt_s_t_0, ae_samt64_0;
-  ae_samt64_0 = *valp;
-  ae_samt_s_t_0 = (ae_samt64_0 & 0x3f);
-  *valp = ae_samt_s_t_0;
-  return 0;
-}
-
-static int
-Operand_ae_ohba_decode (uint32 *valp)
-{
-  unsigned ae_ohba_0, op1_0;
-  op1_0 = *valp & 0xf;
-  ae_ohba_0 = (0 << 5) | (((((op1_0 & 0xf))) == 0) << 4) | ((op1_0 & 0xf));
-  *valp = ae_ohba_0;
-  return 0;
-}
-
-static int
-Operand_ae_ohba_encode (uint32 *valp)
-{
-  unsigned op1_0, ae_ohba_0;
-  ae_ohba_0 = *valp;
-  op1_0 = (ae_ohba_0 & 0xf);
-  *valp = op1_0;
-  return 0;
-}
-
-static int
-Operand_pr_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
-  return 0;
-}
-
-static int
-Operand_pr_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~0x7) != 0;
-  return error;
-}
-
-static int
-Operand_qr0_rw_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
-  return 0;
-}
-
-static int
-Operand_qr0_rw_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~0x3) != 0;
-  return error;
-}
-
-static int
-Operand_qr1_w_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
-  return 0;
-}
-
-static int
-Operand_qr1_w_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~0x3) != 0;
-  return error;
-}
-
-static int
-Operand_ps_decode (uint32 *valp ATTRIBUTE_UNUSED)
-{
-  return 0;
-}
-
-static int
-Operand_ps_encode (uint32 *valp)
-{
-  int error;
-  error = (*valp & ~0x7) != 0;
-  return error;
-}
-
 static xtensa_operand_internal operands[] = {
   { "soffsetx4", FIELD_offset, -1, 0,
     XTENSA_OPERAND_IS_PCRELATIVE,
-    Operand_soffsetx4_encode, Operand_soffsetx4_decode,
+    OperandSem_opnd_sem_soffsetx4_encode, OperandSem_opnd_sem_soffsetx4_decode,
     Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
   { "uimm12x8", FIELD_imm12, -1, 0,
     0,
-    Operand_uimm12x8_encode, Operand_uimm12x8_decode,
+    OperandSem_opnd_sem_uimm12x8_encode, OperandSem_opnd_sem_uimm12x8_decode,
     0, 0 },
   { "simm4", FIELD_mn, -1, 0,
     0,
-    Operand_simm4_encode, Operand_simm4_decode,
+    OperandSem_opnd_sem_simm4_encode, OperandSem_opnd_sem_simm4_decode,
     0, 0 },
   { "arr", FIELD_r, REGFILE_AR, 1,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_arr_encode, Operand_arr_decode,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
     0, 0 },
   { "ars", FIELD_s, REGFILE_AR, 1,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_ars_encode, Operand_ars_decode,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
     0, 0 },
   { "*ars_invisible", FIELD_s, REGFILE_AR, 1,
     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
-    Operand_ars_encode, Operand_ars_decode,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
     0, 0 },
   { "art", FIELD_t, REGFILE_AR, 1,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_art_encode, Operand_art_decode,
+    OperandSem_opnd_sem_AR_encode, OperandSem_opnd_sem_AR_decode,
     0, 0 },
   { "ar0", FIELD__ar0, REGFILE_AR, 1,
     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
-    Operand_ar0_encode, Operand_ar0_decode,
+    OperandSem_opnd_sem_AR_0_encode, OperandSem_opnd_sem_AR_0_decode,
     0, 0 },
   { "ar4", FIELD__ar4, REGFILE_AR, 1,
     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
-    Operand_ar4_encode, Operand_ar4_decode,
+    OperandSem_opnd_sem_AR_1_encode, OperandSem_opnd_sem_AR_1_decode,
     0, 0 },
   { "ar8", FIELD__ar8, REGFILE_AR, 1,
     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
-    Operand_ar8_encode, Operand_ar8_decode,
+    OperandSem_opnd_sem_AR_2_encode, OperandSem_opnd_sem_AR_2_decode,
     0, 0 },
   { "ar12", FIELD__ar12, REGFILE_AR, 1,
     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
-    Operand_ar12_encode, Operand_ar12_decode,
+    OperandSem_opnd_sem_AR_3_encode, OperandSem_opnd_sem_AR_3_decode,
     0, 0 },
   { "ars_entry", FIELD_s, REGFILE_AR, 1,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_ars_entry_encode, Operand_ars_entry_decode,
+    OperandSem_opnd_sem_AR_4_encode, OperandSem_opnd_sem_AR_4_decode,
     0, 0 },
   { "immrx4", FIELD_r, -1, 0,
     0,
-    Operand_immrx4_encode, Operand_immrx4_decode,
+    OperandSem_opnd_sem_immrx4_encode, OperandSem_opnd_sem_immrx4_decode,
     0, 0 },
   { "lsi4x4", FIELD_r, -1, 0,
     0,
-    Operand_lsi4x4_encode, Operand_lsi4x4_decode,
+    OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
     0, 0 },
   { "simm7", FIELD_imm7, -1, 0,
     0,
-    Operand_simm7_encode, Operand_simm7_decode,
+    OperandSem_opnd_sem_simm7_encode, OperandSem_opnd_sem_simm7_decode,
     0, 0 },
   { "uimm6", FIELD_imm6, -1, 0,
     XTENSA_OPERAND_IS_PCRELATIVE,
-    Operand_uimm6_encode, Operand_uimm6_decode,
+    OperandSem_opnd_sem_uimm6_encode, OperandSem_opnd_sem_uimm6_decode,
     Operand_uimm6_ator, Operand_uimm6_rtoa },
   { "ai4const", FIELD_t, -1, 0,
     0,
-    Operand_ai4const_encode, Operand_ai4const_decode,
+    OperandSem_opnd_sem_ai4const_encode, OperandSem_opnd_sem_ai4const_decode,
     0, 0 },
   { "b4const", FIELD_r, -1, 0,
     0,
-    Operand_b4const_encode, Operand_b4const_decode,
+    OperandSem_opnd_sem_b4const_encode, OperandSem_opnd_sem_b4const_decode,
     0, 0 },
   { "b4constu", FIELD_r, -1, 0,
     0,
-    Operand_b4constu_encode, Operand_b4constu_decode,
+    OperandSem_opnd_sem_b4constu_encode, OperandSem_opnd_sem_b4constu_decode,
     0, 0 },
   { "uimm8", FIELD_imm8, -1, 0,
     0,
-    Operand_uimm8_encode, Operand_uimm8_decode,
+    OperandSem_opnd_sem_uimm8_encode, OperandSem_opnd_sem_uimm8_decode,
     0, 0 },
   { "uimm8x2", FIELD_imm8, -1, 0,
     0,
-    Operand_uimm8x2_encode, Operand_uimm8x2_decode,
+    OperandSem_opnd_sem_uimm8x2_encode, OperandSem_opnd_sem_uimm8x2_decode,
     0, 0 },
   { "uimm8x4", FIELD_imm8, -1, 0,
     0,
-    Operand_uimm8x4_encode, Operand_uimm8x4_decode,
+    OperandSem_opnd_sem_uimm8x4_encode, OperandSem_opnd_sem_uimm8x4_decode,
     0, 0 },
   { "uimm4x16", FIELD_op2, -1, 0,
     0,
-    Operand_uimm4x16_encode, Operand_uimm4x16_decode,
+    OperandSem_opnd_sem_uimm4x16_encode, OperandSem_opnd_sem_uimm4x16_decode,
+    0, 0 },
+  { "uimmrx4", FIELD_r, -1, 0,
+    0,
+    OperandSem_opnd_sem_lsi4x4_encode, OperandSem_opnd_sem_lsi4x4_decode,
     0, 0 },
   { "simm8", FIELD_imm8, -1, 0,
     0,
-    Operand_simm8_encode, Operand_simm8_decode,
+    OperandSem_opnd_sem_simm8_encode, OperandSem_opnd_sem_simm8_decode,
     0, 0 },
   { "simm8x256", FIELD_imm8, -1, 0,
     0,
-    Operand_simm8x256_encode, Operand_simm8x256_decode,
+    OperandSem_opnd_sem_simm8x256_encode, OperandSem_opnd_sem_simm8x256_decode,
     0, 0 },
   { "simm12b", FIELD_imm12b, -1, 0,
     0,
-    Operand_simm12b_encode, Operand_simm12b_decode,
+    OperandSem_opnd_sem_simm12b_encode, OperandSem_opnd_sem_simm12b_decode,
     0, 0 },
   { "msalp32", FIELD_sal, -1, 0,
     0,
-    Operand_msalp32_encode, Operand_msalp32_decode,
+    OperandSem_opnd_sem_msalp32_encode, OperandSem_opnd_sem_msalp32_decode,
     0, 0 },
   { "op2p1", FIELD_op2, -1, 0,
     0,
-    Operand_op2p1_encode, Operand_op2p1_decode,
+    OperandSem_opnd_sem_op2p1_encode, OperandSem_opnd_sem_op2p1_decode,
     0, 0 },
   { "label8", FIELD_imm8, -1, 0,
     XTENSA_OPERAND_IS_PCRELATIVE,
-    Operand_label8_encode, Operand_label8_decode,
+    OperandSem_opnd_sem_label8_encode, OperandSem_opnd_sem_label8_decode,
     Operand_label8_ator, Operand_label8_rtoa },
   { "ulabel8", FIELD_imm8, -1, 0,
     XTENSA_OPERAND_IS_PCRELATIVE,
-    Operand_ulabel8_encode, Operand_ulabel8_decode,
+    OperandSem_opnd_sem_ulabel8_encode, OperandSem_opnd_sem_ulabel8_decode,
     Operand_ulabel8_ator, Operand_ulabel8_rtoa },
   { "label12", FIELD_imm12, -1, 0,
     XTENSA_OPERAND_IS_PCRELATIVE,
-    Operand_label12_encode, Operand_label12_decode,
+    OperandSem_opnd_sem_label12_encode, OperandSem_opnd_sem_label12_decode,
     Operand_label12_ator, Operand_label12_rtoa },
   { "soffset", FIELD_offset, -1, 0,
     XTENSA_OPERAND_IS_PCRELATIVE,
-    Operand_soffset_encode, Operand_soffset_decode,
+    OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
     Operand_soffset_ator, Operand_soffset_rtoa },
   { "uimm16x4", FIELD_imm16, -1, 0,
     XTENSA_OPERAND_IS_PCRELATIVE,
-    Operand_uimm16x4_encode, Operand_uimm16x4_decode,
+    OperandSem_opnd_sem_uimm16x4_encode, OperandSem_opnd_sem_uimm16x4_decode,
     Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
+  { "bbi", FIELD_bbi, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "sae", FIELD_sae, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "sas", FIELD_sas, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "sargt", FIELD_sargt, -1, 0,
+    0,
+    OperandSem_opnd_sem_bbi_encode, OperandSem_opnd_sem_bbi_decode,
+    0, 0 },
+  { "s", FIELD_s, -1, 0,
+    0,
+    OperandSem_opnd_sem_s_encode, OperandSem_opnd_sem_s_decode,
+    0, 0 },
   { "immt", FIELD_t, -1, 0,
     0,
-    Operand_immt_encode, Operand_immt_decode,
+    OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
     0, 0 },
   { "imms", FIELD_s, -1, 0,
     0,
-    Operand_imms_encode, Operand_imms_decode,
+    OperandSem_opnd_sem_immt_encode, OperandSem_opnd_sem_immt_decode,
     0, 0 },
   { "bt", FIELD_t, REGFILE_BR, 1,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_bt_encode, Operand_bt_decode,
+    OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
     0, 0 },
   { "bs", FIELD_s, REGFILE_BR, 1,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_bs_encode, Operand_bs_decode,
+    OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
     0, 0 },
   { "br", FIELD_r, REGFILE_BR, 1,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_br_encode, Operand_br_decode,
+    OperandSem_opnd_sem_BR_encode, OperandSem_opnd_sem_BR_decode,
     0, 0 },
   { "bt2", FIELD_t2, REGFILE_BR, 2,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_bt2_encode, Operand_bt2_decode,
+    OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
     0, 0 },
   { "bs2", FIELD_s2, REGFILE_BR, 2,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_bs2_encode, Operand_bs2_decode,
+    OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
     0, 0 },
   { "br2", FIELD_r2, REGFILE_BR, 2,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_br2_encode, Operand_br2_decode,
+    OperandSem_opnd_sem_BR2_encode, OperandSem_opnd_sem_BR2_decode,
     0, 0 },
   { "bt4", FIELD_t4, REGFILE_BR, 4,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_bt4_encode, Operand_bt4_decode,
+    OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
     0, 0 },
   { "bs4", FIELD_s4, REGFILE_BR, 4,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_bs4_encode, Operand_bs4_decode,
+    OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
     0, 0 },
   { "br4", FIELD_r4, REGFILE_BR, 4,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_br4_encode, Operand_br4_decode,
+    OperandSem_opnd_sem_BR4_encode, OperandSem_opnd_sem_BR4_decode,
     0, 0 },
   { "bt8", FIELD_t8, REGFILE_BR, 8,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_bt8_encode, Operand_bt8_decode,
+    OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
     0, 0 },
   { "bs8", FIELD_s8, REGFILE_BR, 8,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_bs8_encode, Operand_bs8_decode,
+    OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
     0, 0 },
   { "br8", FIELD_r8, REGFILE_BR, 8,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_br8_encode, Operand_br8_decode,
+    OperandSem_opnd_sem_BR8_encode, OperandSem_opnd_sem_BR8_decode,
     0, 0 },
   { "bt16", FIELD__bt16, REGFILE_BR, 16,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_bt16_encode, Operand_bt16_decode,
+    OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
     0, 0 },
   { "bs16", FIELD__bs16, REGFILE_BR, 16,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_bs16_encode, Operand_bs16_decode,
+    OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
     0, 0 },
   { "br16", FIELD__br16, REGFILE_BR, 16,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_br16_encode, Operand_br16_decode,
+    OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
     0, 0 },
   { "brall", FIELD__brall, REGFILE_BR, 16,
     XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
-    Operand_brall_encode, Operand_brall_decode,
+    OperandSem_opnd_sem_BR16_encode, OperandSem_opnd_sem_BR16_decode,
     0, 0 },
   { "tp7", FIELD_t, -1, 0,
     0,
-    Operand_tp7_encode, Operand_tp7_decode,
+    OperandSem_opnd_sem_tp7_encode, OperandSem_opnd_sem_tp7_decode,
     0, 0 },
   { "xt_wbr15_label", FIELD_xt_wbr15_imm, -1, 0,
     XTENSA_OPERAND_IS_PCRELATIVE,
-    Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
+    OperandSem_opnd_sem_xt_wbr15_label_encode, OperandSem_opnd_sem_xt_wbr15_label_decode,
     Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
   { "xt_wbr18_label", FIELD_xt_wbr18_imm, -1, 0,
     XTENSA_OPERAND_IS_PCRELATIVE,
-    Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
+    OperandSem_opnd_sem_soffset_encode, OperandSem_opnd_sem_soffset_decode,
     Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
   { "ae_samt32", FIELD_ftsf14, -1, 0,
     0,
-    Operand_ae_samt32_encode, Operand_ae_samt32_decode,
+    OperandSem_opnd_sem_ae_samt32_encode, OperandSem_opnd_sem_ae_samt32_decode,
     0, 0 },
   { "pr0", FIELD_ftsf12, REGFILE_AE_PR, 1,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_pr0_encode, Operand_pr0_decode,
+    OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
     0, 0 },
   { "qr0", FIELD_ftsf13, REGFILE_AE_QR, 1,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_qr0_encode, Operand_qr0_decode,
+    OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+    0, 0 },
+  { "mac_qr0", FIELD_ftsf13, REGFILE_AE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
     0, 0 },
   { "ae_lsimm16", FIELD_t, -1, 0,
     0,
-    Operand_ae_lsimm16_encode, Operand_ae_lsimm16_decode,
+    OperandSem_opnd_sem_ae_lsimm16_encode, OperandSem_opnd_sem_ae_lsimm16_decode,
     0, 0 },
   { "ae_lsimm32", FIELD_t, -1, 0,
     0,
-    Operand_ae_lsimm32_encode, Operand_ae_lsimm32_decode,
+    OperandSem_opnd_sem_ae_lsimm32_encode, OperandSem_opnd_sem_ae_lsimm32_decode,
     0, 0 },
   { "ae_lsimm64", FIELD_t, -1, 0,
     0,
-    Operand_ae_lsimm64_encode, Operand_ae_lsimm64_decode,
+    OperandSem_opnd_sem_ae_lsimm64_encode, OperandSem_opnd_sem_ae_lsimm64_decode,
     0, 0 },
   { "ae_samt64", FIELD_ae_samt_s_t, -1, 0,
     0,
-    Operand_ae_samt64_encode, Operand_ae_samt64_decode,
+    OperandSem_opnd_sem_ae_samt64_encode, OperandSem_opnd_sem_ae_samt64_decode,
     0, 0 },
-  { "ae_ohba", FIELD_op1, -1, 0,
+  { "ae_ohba", FIELD_ae_fld_ohba, -1, 0,
     0,
-    Operand_ae_ohba_encode, Operand_ae_ohba_decode,
+    OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
+    0, 0 },
+  { "ae_ohba2", FIELD_ae_fld_ohba2, -1, 0,
+    0,
+    OperandSem_opnd_sem_ae_ohba_encode, OperandSem_opnd_sem_ae_ohba_decode,
     0, 0 },
   { "pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_pr_encode, Operand_pr_decode,
+    OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
+    0, 0 },
+  { "cvt_pr", FIELD_ae_r20, REGFILE_AE_PR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
     0, 0 },
   { "qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_qr0_rw_encode, Operand_qr0_rw_decode,
+    OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+    0, 0 },
+  { "mac_qr0_rw", FIELD_ae_r10, REGFILE_AE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
     0, 0 },
   { "qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_qr1_w_encode, Operand_qr1_w_decode,
+    OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
+    0, 0 },
+  { "mac_qr1_w", FIELD_ae_r32, REGFILE_AE_QR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AE_QR_encode, OperandSem_opnd_sem_AE_QR_decode,
     0, 0 },
   { "ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
     XTENSA_OPERAND_IS_REGISTER,
-    Operand_ps_encode, Operand_ps_decode,
+    OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
+    0, 0 },
+  { "alupppb_ps", FIELD_ae_s20, REGFILE_AE_PR, 1,
+    XTENSA_OPERAND_IS_REGISTER,
+    OperandSem_opnd_sem_AE_PR_encode, OperandSem_opnd_sem_AE_PR_decode,
     0, 0 },
   { "t", FIELD_t, -1, 0, 0, 0, 0, 0, 0 },
   { "bbi4", FIELD_bbi4, -1, 0, 0, 0, 0, 0, 0 },
-  { "bbi", FIELD_bbi, -1, 0, 0, 0, 0, 0, 0 },
   { "imm12", FIELD_imm12, -1, 0, 0, 0, 0, 0, 0 },
   { "imm8", FIELD_imm8, -1, 0, 0, 0, 0, 0, 0 },
-  { "s", FIELD_s, -1, 0, 0, 0, 0, 0, 0 },
   { "imm12b", FIELD_imm12b, -1, 0, 0, 0, 0, 0, 0 },
   { "imm16", FIELD_imm16, -1, 0, 0, 0, 0, 0, 0 },
   { "m", FIELD_m, -1, 0, 0, 0, 0, 0, 0 },
@@ -10861,11 +10757,8 @@  static xtensa_operand_internal operands[] = {
   { "r", FIELD_r, -1, 0, 0, 0, 0, 0, 0 },
   { "sa4", FIELD_sa4, -1, 0, 0, 0, 0, 0, 0 },
   { "sae4", FIELD_sae4, -1, 0, 0, 0, 0, 0, 0 },
-  { "sae", FIELD_sae, -1, 0, 0, 0, 0, 0, 0 },
   { "sal", FIELD_sal, -1, 0, 0, 0, 0, 0, 0 },
-  { "sargt", FIELD_sargt, -1, 0, 0, 0, 0, 0, 0 },
   { "sas4", FIELD_sas4, -1, 0, 0, 0, 0, 0, 0 },
-  { "sas", FIELD_sas, -1, 0, 0, 0, 0, 0, 0 },
   { "sr", FIELD_sr, -1, 0, 0, 0, 0, 0, 0 },
   { "st", FIELD_st, -1, 0, 0, 0, 0, 0, 0 },
   { "thi3", FIELD_thi3, -1, 0, 0, 0, 0, 0, 0 },
@@ -10898,6 +10791,8 @@  static xtensa_operand_internal operands[] = {
   { "ae_r20", FIELD_ae_r20, -1, 0, 0, 0, 0, 0, 0 },
   { "ae_r10", FIELD_ae_r10, -1, 0, 0, 0, 0, 0, 0 },
   { "ae_s20", FIELD_ae_s20, -1, 0, 0, 0, 0, 0, 0 },
+  { "ae_fld_ohba", FIELD_ae_fld_ohba, -1, 0, 0, 0, 0, 0, 0 },
+  { "ae_fld_ohba2", FIELD_ae_fld_ohba2, -1, 0, 0, 0, 0, 0, 0 },
   { "op0_s3", FIELD_op0_s3, -1, 0, 0, 0, 0, 0, 0 },
   { "ftsf12", FIELD_ftsf12, -1, 0, 0, 0, 0, 0, 0 },
   { "ftsf13", FIELD_ftsf13, -1, 0, 0, 0, 0, 0, 0 },
@@ -11249,6 +11144,7 @@  enum xtensa_operand_id {
   OPERAND_uimm8x2,
   OPERAND_uimm8x4,
   OPERAND_uimm4x16,
+  OPERAND_uimmrx4,
   OPERAND_simm8,
   OPERAND_simm8x256,
   OPERAND_simm12b,
@@ -11259,6 +11155,11 @@  enum xtensa_operand_id {
   OPERAND_label12,
   OPERAND_soffset,
   OPERAND_uimm16x4,
+  OPERAND_bbi,
+  OPERAND_sae,
+  OPERAND_sas,
+  OPERAND_sargt,
+  OPERAND_s,
   OPERAND_immt,
   OPERAND_imms,
   OPERAND_bt,
@@ -11283,21 +11184,25 @@  enum xtensa_operand_id {
   OPERAND_ae_samt32,
   OPERAND_pr0,
   OPERAND_qr0,
+  OPERAND_mac_qr0,
   OPERAND_ae_lsimm16,
   OPERAND_ae_lsimm32,
   OPERAND_ae_lsimm64,
   OPERAND_ae_samt64,
   OPERAND_ae_ohba,
+  OPERAND_ae_ohba2,
   OPERAND_pr,
+  OPERAND_cvt_pr,
   OPERAND_qr0_rw,
+  OPERAND_mac_qr0_rw,
   OPERAND_qr1_w,
+  OPERAND_mac_qr1_w,
   OPERAND_ps,
+  OPERAND_alupppb_ps,
   OPERAND_t,
   OPERAND_bbi4,
-  OPERAND_bbi,
   OPERAND_imm12,
   OPERAND_imm8,
-  OPERAND_s,
   OPERAND_imm12b,
   OPERAND_imm16,
   OPERAND_m,
@@ -11309,11 +11214,8 @@  enum xtensa_operand_id {
   OPERAND_r,
   OPERAND_sa4,
   OPERAND_sae4,
-  OPERAND_sae,
   OPERAND_sal,
-  OPERAND_sargt,
   OPERAND_sas4,
-  OPERAND_sas,
   OPERAND_sr,
   OPERAND_st,
   OPERAND_thi3,
@@ -11346,6 +11248,8 @@  enum xtensa_operand_id {
   OPERAND_ae_r20,
   OPERAND_ae_r10,
   OPERAND_ae_s20,
+  OPERAND_ae_fld_ohba,
+  OPERAND_ae_fld_ohba2,
   OPERAND_op0_s3,
   OPERAND_ftsf12,
   OPERAND_ftsf13,
@@ -12316,29 +12220,29 @@  static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
   { { STATE_LITBEN }, 'm' }
 };
 
-static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_args[] = {
   { { OPERAND_art }, 'o' }
 };
 
-static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid0_stateArgs[] = {
   { { STATE_PSEXCM }, 'i' },
   { { STATE_PSRING }, 'i' }
 };
 
-static xtensa_arg_internal Iclass_xt_iclass_wsr_176_args[] = {
+static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_args[] = {
   { { OPERAND_art }, 'i' }
 };
 
-static xtensa_arg_internal Iclass_xt_iclass_wsr_176_stateArgs[] = {
+static xtensa_arg_internal Iclass_xt_iclass_wsr_configid0_stateArgs[] = {
   { { STATE_PSEXCM }, 'i' },
   { { STATE_PSRING }, 'i' }
 };
 
-static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_args[] = {
   { { OPERAND_art }, 'o' }
 };
 
-static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
+static xtensa_arg_internal Iclass_xt_iclass_rsr_configid1_stateArgs[] = {
   { { STATE_PSEXCM }, 'i' },
   { { STATE_PSRING }, 'i' }
 };
@@ -14759,7 +14663,7 @@  static xtensa_arg_internal Iclass_ae_iclass_cvtq48a32s_stateArgs[] = {
 
 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_args[] = {
   { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_pr }, 'i' }
+  { { OPERAND_cvt_pr }, 'i' }
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = {
@@ -14768,7 +14672,7 @@  static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_l_stateArgs[] = {
 
 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_args[] = {
   { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_pr }, 'i' }
+  { { OPERAND_cvt_pr }, 'i' }
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_cvtq48p24s_h_stateArgs[] = {
@@ -14918,7 +14822,7 @@  static xtensa_arg_internal Iclass_ae_iclass_minp24s_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_args[] = {
-  { { OPERAND_ps }, 'o' },
+  { { OPERAND_alupppb_ps }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' },
   { { OPERAND_bt2 }, 'o' }
@@ -14929,7 +14833,7 @@  static xtensa_arg_internal Iclass_ae_iclass_maxbp24s_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_minbp24s_args[] = {
-  { { OPERAND_ps }, 'o' },
+  { { OPERAND_alupppb_ps }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' },
   { { OPERAND_bt2 }, 'o' }
@@ -15458,7 +15362,7 @@  static xtensa_arg_internal Iclass_ae_iclass_nsaq56s_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15469,7 +15373,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15479,7 +15383,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15489,7 +15393,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulp24s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15500,7 +15404,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15510,7 +15414,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15520,7 +15424,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulp24s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15531,7 +15435,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hl_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15541,7 +15445,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hl_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15551,7 +15455,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hl_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15562,7 +15466,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulfs32p16s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15572,7 +15476,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulfp24s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15582,7 +15486,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulp24s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15593,7 +15497,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15603,7 +15507,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15613,7 +15517,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulap24s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15624,7 +15528,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15634,7 +15538,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15644,7 +15548,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulap24s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15655,7 +15559,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hl_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15665,7 +15569,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hl_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15675,7 +15579,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hl_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15686,7 +15590,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafs32p16s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15696,7 +15600,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafp24s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15706,7 +15610,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulap24s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15717,7 +15621,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15727,7 +15631,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15737,7 +15641,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15748,7 +15652,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15758,7 +15662,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15768,7 +15672,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15779,7 +15683,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hl_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15789,7 +15693,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hl_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15799,7 +15703,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hl_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15810,7 +15714,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfs32p16s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15820,7 +15724,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfp24s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15830,7 +15734,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsp24s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15841,7 +15745,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15852,7 +15756,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15863,7 +15767,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15874,7 +15778,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15885,7 +15789,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hl_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15896,7 +15800,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hl_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15907,7 +15811,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafs56p24s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15918,7 +15822,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulas56p24s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15929,7 +15833,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15940,7 +15844,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15951,7 +15855,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15962,7 +15866,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15973,7 +15877,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hl_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15984,7 +15888,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hl_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -15995,7 +15899,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfs56p24s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16006,8 +15910,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulss56p24s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16016,8 +15920,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_l_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16026,8 +15930,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16s_h_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16036,8 +15940,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_l_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16046,8 +15950,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulfq32sp16u_h_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16056,8 +15960,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_l_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16066,8 +15970,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16s_h_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16076,8 +15980,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_l_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16086,8 +15990,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulq32sp16u_h_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16096,8 +16000,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_l_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16106,8 +16010,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16s_h_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16116,8 +16020,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_l_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16126,8 +16030,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulafq32sp16u_h_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16136,8 +16040,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_l_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16146,8 +16050,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16s_h_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16156,8 +16060,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_l_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16166,8 +16070,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulaq32sp16u_h_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16176,8 +16080,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_l_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16186,8 +16090,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16s_h_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16196,8 +16100,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_l_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16206,8 +16110,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsfq32sp16u_h_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16216,8 +16120,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_l_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16226,8 +16130,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16s_h_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16236,8 +16140,8 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_l_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'm' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' }
 };
 
@@ -16246,10 +16150,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsq32sp16u_h_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16258,10 +16162,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16270,10 +16174,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16282,10 +16186,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16294,10 +16198,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16306,10 +16210,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16318,10 +16222,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16330,10 +16234,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16342,10 +16246,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16354,10 +16258,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16366,10 +16270,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16378,10 +16282,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaaq32sp16u_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16390,10 +16294,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaafq32sp16u_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16402,10 +16306,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16414,10 +16318,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16426,10 +16330,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16438,10 +16342,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16450,10 +16354,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16462,10 +16366,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16474,10 +16378,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16486,10 +16390,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16498,10 +16402,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16510,10 +16414,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16522,10 +16426,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasq32sp16u_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16534,10 +16438,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasfq32sp16u_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16546,10 +16450,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16558,10 +16462,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16570,10 +16474,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16582,10 +16486,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16594,10 +16498,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16606,10 +16510,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16618,10 +16522,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16630,10 +16534,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16642,10 +16546,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16654,10 +16558,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16666,10 +16570,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsaq32sp16u_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16678,10 +16582,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsafq32sp16u_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16690,10 +16594,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16702,10 +16606,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16714,10 +16618,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16726,10 +16630,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16738,10 +16642,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16750,10 +16654,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16762,10 +16666,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16774,10 +16678,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_hh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16786,10 +16690,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16798,10 +16702,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16s_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16810,10 +16714,10 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssq32sp16u_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
-  { { OPERAND_qr0_rw }, 'i' },
+  { { OPERAND_mac_qr1_w }, 'o' },
+  { { OPERAND_mac_qr0_rw }, 'i' },
   { { OPERAND_pr }, 'i' },
-  { { OPERAND_qr0 }, 'i' },
+  { { OPERAND_mac_qr0 }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
 
@@ -16822,7 +16726,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssfq32sp16u_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16832,7 +16736,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16842,7 +16746,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16852,7 +16756,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaafp24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16862,7 +16766,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzaap24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16872,7 +16776,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16882,7 +16786,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16892,7 +16796,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasfp24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16902,7 +16806,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzasp24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16912,7 +16816,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16922,7 +16826,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16932,7 +16836,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsafp24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16942,7 +16846,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzsap24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16952,7 +16856,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16962,7 +16866,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16972,7 +16876,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssfp24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'o' },
+  { { OPERAND_mac_qr1_w }, 'o' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16982,7 +16886,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulzssp24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -16992,7 +16896,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17002,7 +16906,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17012,7 +16916,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulaafp24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17022,7 +16926,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulaap24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17032,7 +16936,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17042,7 +16946,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17052,7 +16956,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulasfp24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17062,7 +16966,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulasp24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17072,7 +16976,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17082,7 +16986,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17092,7 +16996,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsafp24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17102,7 +17006,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulsap24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17112,7 +17016,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17122,7 +17026,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hh_ll_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17132,7 +17036,7 @@  static xtensa_arg_internal Iclass_ae_iclass_mulssfp24s_hl_lh_stateArgs[] = {
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_mulssp24s_hl_lh_args[] = {
-  { { OPERAND_qr1_w }, 'm' },
+  { { OPERAND_mac_qr1_w }, 'm' },
   { { OPERAND_pr }, 'i' },
   { { OPERAND_pr0 }, 'i' }
 };
@@ -17215,7 +17119,7 @@  static xtensa_arg_internal Iclass_ae_iclass_lb_stateArgs[] = {
 
 static xtensa_arg_internal Iclass_ae_iclass_lbi_args[] = {
   { { OPERAND_arr }, 'o' },
-  { { OPERAND_ae_ohba }, 'i' }
+  { { OPERAND_ae_ohba2 }, 'i' }
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_lbi_stateArgs[] = {
@@ -17239,7 +17143,7 @@  static xtensa_arg_internal Iclass_ae_iclass_lbk_stateArgs[] = {
 static xtensa_arg_internal Iclass_ae_iclass_lbki_args[] = {
   { { OPERAND_arr }, 'o' },
   { { OPERAND_ars }, 'i' },
-  { { OPERAND_ae_ohba }, 'i' }
+  { { OPERAND_ae_ohba2 }, 'i' }
 };
 
 static xtensa_arg_internal Iclass_ae_iclass_lbki_stateArgs[] = {
@@ -17349,8 +17253,6 @@  static xtensa_iclass_internal iclasses[] = {
     3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
   { 0, 0 /* xt_iclass_syscall */,
     0, 0, 0, 0 },
-  { 0, 0 /* xt_iclass_simcall */,
-    0, 0, 0, 0 },
   { 2, Iclass_xt_iclass_call12_args,
     1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
   { 2, Iclass_xt_iclass_call8_args,
@@ -17467,6 +17369,8 @@  static xtensa_iclass_internal iclasses[] = {
     0, 0, 0, 0 },
   { 1, Iclass_xt_iclass_return_args,
     0, 0, 0, 0 },
+  { 0, 0 /* xt_iclass_simcall */,
+    0, 0, 0, 0 },
   { 3, Iclass_xt_iclass_s16i_args,
     0, 0, 0, 0 },
   { 3, Iclass_xt_iclass_s32i_args,
@@ -17529,12 +17433,12 @@  static xtensa_iclass_internal iclasses[] = {
     2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
   { 1, Iclass_xt_iclass_xsr_litbase_args,
     2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
-  { 1, Iclass_xt_iclass_rsr_176_args,
-    2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
-  { 1, Iclass_xt_iclass_wsr_176_args,
-    2, Iclass_xt_iclass_wsr_176_stateArgs, 0, 0 },
-  { 1, Iclass_xt_iclass_rsr_208_args,
-    2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_configid0_args,
+    2, Iclass_xt_iclass_rsr_configid0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_wsr_configid0_args,
+    2, Iclass_xt_iclass_wsr_configid0_stateArgs, 0, 0 },
+  { 1, Iclass_xt_iclass_rsr_configid1_args,
+    2, Iclass_xt_iclass_rsr_configid1_stateArgs, 0, 0 },
   { 1, Iclass_xt_iclass_rsr_ps_args,
     7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
   { 1, Iclass_xt_iclass_wsr_ps_args,
@@ -18524,7 +18428,6 @@  enum xtensa_iclass_id {
   ICLASS_xt_iclass_rfe,
   ICLASS_xt_iclass_rfde,
   ICLASS_xt_iclass_syscall,
-  ICLASS_xt_iclass_simcall,
   ICLASS_xt_iclass_call12,
   ICLASS_xt_iclass_call8,
   ICLASS_xt_iclass_call4,
@@ -18583,6 +18486,7 @@  enum xtensa_iclass_id {
   ICLASS_xt_iclass_neg,
   ICLASS_xt_iclass_nop,
   ICLASS_xt_iclass_return,
+  ICLASS_xt_iclass_simcall,
   ICLASS_xt_iclass_s16i,
   ICLASS_xt_iclass_s32i,
   ICLASS_xt_iclass_s8i,
@@ -18614,9 +18518,9 @@  enum xtensa_iclass_id {
   ICLASS_xt_iclass_rsr_litbase,
   ICLASS_xt_iclass_wsr_litbase,
   ICLASS_xt_iclass_xsr_litbase,
-  ICLASS_xt_iclass_rsr_176,
-  ICLASS_xt_iclass_wsr_176,
-  ICLASS_xt_iclass_rsr_208,
+  ICLASS_xt_iclass_rsr_configid0,
+  ICLASS_xt_iclass_wsr_configid0,
+  ICLASS_xt_iclass_rsr_configid1,
   ICLASS_xt_iclass_rsr_ps,
   ICLASS_xt_iclass_wsr_ps,
   ICLASS_xt_iclass_xsr_ps,
@@ -19137,12 +19041,6 @@  Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
   slotbuf[0] = 0x5000;
 }
 
-static void
-Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
-{
-  slotbuf[0] = 0x5100;
-}
-
 static void
 Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
 {
@@ -20031,6 +19929,12 @@  Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
   slotbuf[0] = 0x80;
 }
 
+static void
+Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
+{
+  slotbuf[0] = 0x5100;
+}
+
 static void
 Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
 {
@@ -20344,19 +20248,19 @@  Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
 }
 
 static void
-Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
+Opcode_rsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
 {
   slotbuf[0] = 0x3b000;
 }
 
 static void
-Opcode_wsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
+Opcode_wsr_configid0_Slot_inst_encode (xtensa_insnbuf slotbuf)
 {
   slotbuf[0] = 0x13b000;
 }
 
 static void
-Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
+Opcode_rsr_configid1_Slot_inst_encode (xtensa_insnbuf slotbuf)
 {
   slotbuf[0] = 0x3d000;
 }
@@ -24175,10 +24079,6 @@  static xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
   Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0
 };
 
-static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
-  Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0
-};
-
 static xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
   Opcode_call12_Slot_inst_encode, 0, 0, 0, 0
 };
@@ -24555,6 +24455,10 @@  static xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
   Opcode_ret_Slot_inst_encode, 0, 0, 0, 0
 };
 
+static xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
+  Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0
+};
+
 static xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
   Opcode_s16i_Slot_inst_encode, 0, 0, 0, Opcode_s16i_Slot_ae_slot0_encode
 };
@@ -24703,16 +24607,16 @@  static xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
   Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0
 };
 
-static xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
-  Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0
+static xtensa_opcode_encode_fn Opcode_rsr_configid0_encode_fns[] = {
+  Opcode_rsr_configid0_Slot_inst_encode, 0, 0, 0, 0
 };
 
-static xtensa_opcode_encode_fn Opcode_wsr_176_encode_fns[] = {
-  Opcode_wsr_176_Slot_inst_encode, 0, 0, 0, 0
+static xtensa_opcode_encode_fn Opcode_wsr_configid0_encode_fns[] = {
+  Opcode_wsr_configid0_Slot_inst_encode, 0, 0, 0, 0
 };
 
-static xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
-  Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0
+static xtensa_opcode_encode_fn Opcode_rsr_configid1_encode_fns[] = {
+  Opcode_rsr_configid1_Slot_inst_encode, 0, 0, 0, 0
 };
 
 static xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
@@ -26873,9 +26777,6 @@  static xtensa_opcode_internal opcodes[] = {
   { "syscall", ICLASS_xt_iclass_syscall,
     0,
     Opcode_syscall_encode_fns, 0, 0 },
-  { "simcall", ICLASS_xt_iclass_simcall,
-    0,
-    Opcode_simcall_encode_fns, 0, 0 },
   { "call12", ICLASS_xt_iclass_call12,
     XTENSA_OPCODE_IS_CALL,
     Opcode_call12_encode_fns, 0, 0 },
@@ -27158,6 +27059,9 @@  static xtensa_opcode_internal opcodes[] = {
   { "ret", ICLASS_xt_iclass_return,
     XTENSA_OPCODE_IS_JUMP,
     Opcode_ret_encode_fns, 0, 0 },
+  { "simcall", ICLASS_xt_iclass_simcall,
+    0,
+    Opcode_simcall_encode_fns, 0, 0 },
   { "s16i", ICLASS_xt_iclass_s16i,
     0,
     Opcode_s16i_encode_fns, 0, 0 },
@@ -27269,15 +27173,15 @@  static xtensa_opcode_internal opcodes[] = {
   { "xsr.litbase", ICLASS_xt_iclass_xsr_litbase,
     0,
     Opcode_xsr_litbase_encode_fns, 0, 0 },
-  { "rsr.176", ICLASS_xt_iclass_rsr_176,
+  { "rsr.configid0", ICLASS_xt_iclass_rsr_configid0,
     0,
-    Opcode_rsr_176_encode_fns, 0, 0 },
-  { "wsr.176", ICLASS_xt_iclass_wsr_176,
+    Opcode_rsr_configid0_encode_fns, 0, 0 },
+  { "wsr.configid0", ICLASS_xt_iclass_wsr_configid0,
     0,
-    Opcode_wsr_176_encode_fns, 0, 0 },
-  { "rsr.208", ICLASS_xt_iclass_rsr_208,
+    Opcode_wsr_configid0_encode_fns, 0, 0 },
+  { "rsr.configid1", ICLASS_xt_iclass_rsr_configid1,
     0,
-    Opcode_rsr_208_encode_fns, 0, 0 },
+    Opcode_rsr_configid1_encode_fns, 0, 0 },
   { "rsr.ps", ICLASS_xt_iclass_rsr_ps,
     0,
     Opcode_rsr_ps_encode_fns, 0, 0 },
@@ -28836,7 +28740,6 @@  enum xtensa_opcode_id {
   OPCODE_RFE,
   OPCODE_RFDE,
   OPCODE_SYSCALL,
-  OPCODE_SIMCALL,
   OPCODE_CALL12,
   OPCODE_CALL8,
   OPCODE_CALL4,
@@ -28931,6 +28834,7 @@  enum xtensa_opcode_id {
   OPCODE_ABS,
   OPCODE_NOP,
   OPCODE_RET,
+  OPCODE_SIMCALL,
   OPCODE_S16I,
   OPCODE_S32I,
   OPCODE_S8I,
@@ -28968,9 +28872,9 @@  enum xtensa_opcode_id {
   OPCODE_RSR_LITBASE,
   OPCODE_WSR_LITBASE,
   OPCODE_XSR_LITBASE,
-  OPCODE_RSR_176,
-  OPCODE_WSR_176,
-  OPCODE_RSR_208,
+  OPCODE_RSR_CONFIGID0,
+  OPCODE_WSR_CONFIGID0,
+  OPCODE_RSR_CONFIGID1,
   OPCODE_RSR_PS,
   OPCODE_WSR_PS,
   OPCODE_XSR_PS,
@@ -29496,1327 +29400,1252 @@  enum xtensa_opcode_id {
 static int
 Slot_inst_decode (const xtensa_insnbuf insn)
 {
-  switch (Field_op0_Slot_inst_get (insn))
+  if (Field_op0_Slot_inst_get (insn) == 0)
     {
-    case 0:
-      switch (Field_op1_Slot_inst_get (insn))
+      if (Field_op1_Slot_inst_get (insn) == 0)
 	{
-	case 0:
-	  switch (Field_op2_Slot_inst_get (insn))
+	  if (Field_op2_Slot_inst_get (insn) == 0)
 	    {
-	    case 0:
-	      switch (Field_r_Slot_inst_get (insn))
+	      if (Field_r_Slot_inst_get (insn) == 0)
 		{
-		case 0:
-		  switch (Field_m_Slot_inst_get (insn))
-		    {
-		    case 0:
-		      if (Field_s_Slot_inst_get (insn) == 0 &&
-			  Field_n_Slot_inst_get (insn) == 0)
-			return OPCODE_ILL;
-		      break;
-		    case 2:
-		      switch (Field_n_Slot_inst_get (insn))
-			{
-			case 0:
-			  return OPCODE_RET;
-			case 1:
-			  return OPCODE_RETW;
-			case 2:
-			  return OPCODE_JX;
-			}
-		      break;
-		    case 3:
-		      switch (Field_n_Slot_inst_get (insn))
-			{
-			case 0:
-			  return OPCODE_CALLX0;
-			case 1:
-			  return OPCODE_CALLX4;
-			case 2:
-			  return OPCODE_CALLX8;
-			case 3:
-			  return OPCODE_CALLX12;
-			}
-		      break;
-		    }
-		  break;
-		case 1:
-		  return OPCODE_MOVSP;
-		case 2:
-		  if (Field_s_Slot_inst_get (insn) == 0)
-		    {
-		      switch (Field_t_Slot_inst_get (insn))
-			{
-			case 0:
-			  return OPCODE_ISYNC;
-			case 1:
-			  return OPCODE_RSYNC;
-			case 2:
-			  return OPCODE_ESYNC;
-			case 3:
-			  return OPCODE_DSYNC;
-			case 8:
-			  return OPCODE_EXCW;
-			case 12:
-			  return OPCODE_MEMW;
-			case 13:
-			  return OPCODE_EXTW;
-			case 15:
-			  return OPCODE_NOP;
-			}
-		    }
-		  break;
-		case 3:
-		  switch (Field_t_Slot_inst_get (insn))
+		  if (Field_m_Slot_inst_get (insn) == 0 &&
+		      Field_s_Slot_inst_get (insn) == 0 &&
+		      Field_n_Slot_inst_get (insn) == 0)
+		    return OPCODE_ILL;
+		  if (Field_m_Slot_inst_get (insn) == 2)
 		    {
-		    case 0:
-		      switch (Field_s_Slot_inst_get (insn))
-			{
-			case 0:
-			  return OPCODE_RFE;
-			case 2:
-			  return OPCODE_RFDE;
-			case 4:
-			  return OPCODE_RFWO;
-			case 5:
-			  return OPCODE_RFWU;
-			}
-		      break;
-		    case 1:
-		      return OPCODE_RFI;
+		      if (Field_n_Slot_inst_get (insn) == 0)
+			return OPCODE_RET;
+		      if (Field_n_Slot_inst_get (insn) == 1)
+			return OPCODE_RETW;
+		      if (Field_n_Slot_inst_get (insn) == 2)
+			return OPCODE_JX;
 		    }
-		  break;
-		case 4:
-		  return OPCODE_BREAK;
-		case 5:
-		  switch (Field_s_Slot_inst_get (insn))
+		  if (Field_m_Slot_inst_get (insn) == 3)
 		    {
-		    case 0:
-		      if (Field_t_Slot_inst_get (insn) == 0)
-			return OPCODE_SYSCALL;
-		      break;
-		    case 1:
-		      if (Field_t_Slot_inst_get (insn) == 0)
-			return OPCODE_SIMCALL;
-		      break;
+		      if (Field_n_Slot_inst_get (insn) == 0)
+			return OPCODE_CALLX0;
+		      if (Field_n_Slot_inst_get (insn) == 1)
+			return OPCODE_CALLX4;
+		      if (Field_n_Slot_inst_get (insn) == 2)
+			return OPCODE_CALLX8;
+		      if (Field_n_Slot_inst_get (insn) == 3)
+			return OPCODE_CALLX12;
 		    }
-		  break;
-		case 6:
-		  return OPCODE_RSIL;
-		case 7:
-		  if (Field_t_Slot_inst_get (insn) == 0)
-		    return OPCODE_WAITI;
-		  break;
-		case 8:
-		  return OPCODE_ANY4;
-		case 9:
-		  return OPCODE_ALL4;
-		case 10:
-		  return OPCODE_ANY8;
-		case 11:
-		  return OPCODE_ALL8;
 		}
-	      break;
-	    case 1:
-	      return OPCODE_AND;
-	    case 2:
-	      return OPCODE_OR;
-	    case 3:
-	      return OPCODE_XOR;
-	    case 4:
-	      switch (Field_r_Slot_inst_get (insn))
+	      if (Field_r_Slot_inst_get (insn) == 1)
+		return OPCODE_MOVSP;
+	      if (Field_r_Slot_inst_get (insn) == 2)
 		{
-		case 0:
-		  if (Field_t_Slot_inst_get (insn) == 0)
-		    return OPCODE_SSR;
-		  break;
-		case 1:
-		  if (Field_t_Slot_inst_get (insn) == 0)
-		    return OPCODE_SSL;
-		  break;
-		case 2:
-		  if (Field_t_Slot_inst_get (insn) == 0)
-		    return OPCODE_SSA8L;
-		  break;
-		case 3:
-		  if (Field_t_Slot_inst_get (insn) == 0)
-		    return OPCODE_SSA8B;
-		  break;
-		case 4:
-		  if (Field_thi3_Slot_inst_get (insn) == 0)
-		    return OPCODE_SSAI;
-		  break;
-		case 6:
-		  return OPCODE_RER;
-		case 7:
-		  return OPCODE_WER;
-		case 8:
 		  if (Field_s_Slot_inst_get (insn) == 0)
-		    return OPCODE_ROTW;
-		  break;
-		case 14:
-		  return OPCODE_NSA;
-		case 15:
-		  return OPCODE_NSAU;
+		    {
+		      if (Field_t_Slot_inst_get (insn) == 0)
+			return OPCODE_ISYNC;
+		      if (Field_t_Slot_inst_get (insn) == 1)
+			return OPCODE_RSYNC;
+		      if (Field_t_Slot_inst_get (insn) == 2)
+			return OPCODE_ESYNC;
+		      if (Field_t_Slot_inst_get (insn) == 3)
+			return OPCODE_DSYNC;
+		      if (Field_t_Slot_inst_get (insn) == 8)
+			return OPCODE_EXCW;
+		      if (Field_t_Slot_inst_get (insn) == 12)
+			return OPCODE_MEMW;
+		      if (Field_t_Slot_inst_get (insn) == 13)
+			return OPCODE_EXTW;
+		      if (Field_t_Slot_inst_get (insn) == 15)
+			return OPCODE_NOP;
+		    }
 		}
-	      break;
-	    case 5:
-	      switch (Field_r_Slot_inst_get (insn))
+	      if (Field_r_Slot_inst_get (insn) == 3)
 		{
-		case 1:
-		  return OPCODE_HWWITLBA;
-		case 3:
-		  return OPCODE_RITLB0;
-		case 4:
-		  if (Field_t_Slot_inst_get (insn) == 0)
-		    return OPCODE_IITLB;
-		  break;
-		case 5:
-		  return OPCODE_PITLB;
-		case 6:
-		  return OPCODE_WITLB;
-		case 7:
-		  return OPCODE_RITLB1;
-		case 9:
-		  return OPCODE_HWWDTLBA;
-		case 11:
-		  return OPCODE_RDTLB0;
-		case 12:
 		  if (Field_t_Slot_inst_get (insn) == 0)
-		    return OPCODE_IDTLB;
-		  break;
-		case 13:
-		  return OPCODE_PDTLB;
-		case 14:
-		  return OPCODE_WDTLB;
-		case 15:
-		  return OPCODE_RDTLB1;
-		}
-	      break;
-	    case 6:
-	      switch (Field_s_Slot_inst_get (insn))
-		{
-		case 0:
-		  return OPCODE_NEG;
-		case 1:
-		  return OPCODE_ABS;
-		}
-	      break;
-	    case 8:
-	      return OPCODE_ADD;
-	    case 9:
-	      return OPCODE_ADDX2;
-	    case 10:
-	      return OPCODE_ADDX4;
-	    case 11:
-	      return OPCODE_ADDX8;
-	    case 12:
-	      return OPCODE_SUB;
-	    case 13:
-	      return OPCODE_SUBX2;
-	    case 14:
-	      return OPCODE_SUBX4;
-	    case 15:
-	      return OPCODE_SUBX8;
-	    }
-	  break;
-	case 1:
-	  switch (Field_op2_Slot_inst_get (insn))
-	    {
-	    case 0:
-	    case 1:
-	      return OPCODE_SLLI;
-	    case 2:
-	    case 3:
-	      return OPCODE_SRAI;
-	    case 4:
-	      return OPCODE_SRLI;
-	    case 6:
-	      switch (Field_sr_Slot_inst_get (insn))
-		{
-		case 0:
-		  return OPCODE_XSR_LBEG;
-		case 1:
-		  return OPCODE_XSR_LEND;
-		case 2:
-		  return OPCODE_XSR_LCOUNT;
-		case 3:
-		  return OPCODE_XSR_SAR;
-		case 4:
-		  return OPCODE_XSR_BR;
-		case 5:
-		  return OPCODE_XSR_LITBASE;
-		case 12:
-		  return OPCODE_XSR_SCOMPARE1;
-		case 72:
-		  return OPCODE_XSR_WINDOWBASE;
-		case 73:
-		  return OPCODE_XSR_WINDOWSTART;
-		case 83:
-		  return OPCODE_XSR_PTEVADDR;
-		case 90:
-		  return OPCODE_XSR_RASID;
-		case 91:
-		  return OPCODE_XSR_ITLBCFG;
-		case 92:
-		  return OPCODE_XSR_DTLBCFG;
-		case 99:
-		  return OPCODE_XSR_ATOMCTL;
-		case 104:
-		  return OPCODE_XSR_DDR;
-		case 177:
-		  return OPCODE_XSR_EPC1;
-		case 178:
-		  return OPCODE_XSR_EPC2;
-		case 192:
-		  return OPCODE_XSR_DEPC;
-		case 194:
-		  return OPCODE_XSR_EPS2;
-		case 209:
-		  return OPCODE_XSR_EXCSAVE1;
-		case 210:
-		  return OPCODE_XSR_EXCSAVE2;
-		case 224:
-		  return OPCODE_XSR_CPENABLE;
-		case 228:
-		  return OPCODE_XSR_INTENABLE;
-		case 230:
-		  return OPCODE_XSR_PS;
-		case 231:
-		  return OPCODE_XSR_VECBASE;
-		case 232:
-		  return OPCODE_XSR_EXCCAUSE;
-		case 233:
-		  return OPCODE_XSR_DEBUGCAUSE;
-		case 234:
-		  return OPCODE_XSR_CCOUNT;
-		case 236:
-		  return OPCODE_XSR_ICOUNT;
-		case 237:
-		  return OPCODE_XSR_ICOUNTLEVEL;
-		case 238:
-		  return OPCODE_XSR_EXCVADDR;
-		case 240:
-		  return OPCODE_XSR_CCOMPARE0;
-		case 241:
-		  return OPCODE_XSR_CCOMPARE1;
-		case 244:
-		  return OPCODE_XSR_MISC0;
-		case 245:
-		  return OPCODE_XSR_MISC1;
+		    {
+		      if (Field_s_Slot_inst_get (insn) == 0)
+			return OPCODE_RFE;
+		      if (Field_s_Slot_inst_get (insn) == 2)
+			return OPCODE_RFDE;
+		      if (Field_s_Slot_inst_get (insn) == 4)
+			return OPCODE_RFWO;
+		      if (Field_s_Slot_inst_get (insn) == 5)
+			return OPCODE_RFWU;
+		    }
+		  if (Field_t_Slot_inst_get (insn) == 1)
+		    return OPCODE_RFI;
 		}
-	      break;
-	    case 8:
-	      return OPCODE_SRC;
-	    case 9:
-	      if (Field_s_Slot_inst_get (insn) == 0)
-		return OPCODE_SRL;
-	      break;
-	    case 10:
-	      if (Field_t_Slot_inst_get (insn) == 0)
-		return OPCODE_SLL;
-	      break;
-	    case 11:
-	      if (Field_s_Slot_inst_get (insn) == 0)
-		return OPCODE_SRA;
-	      break;
-	    case 12:
-	      return OPCODE_MUL16U;
-	    case 13:
-	      return OPCODE_MUL16S;
-	    case 15:
-	      switch (Field_r_Slot_inst_get (insn))
+	      if (Field_r_Slot_inst_get (insn) == 4)
+		return OPCODE_BREAK;
+	      if (Field_r_Slot_inst_get (insn) == 5)
 		{
-		case 0:
-		  return OPCODE_LICT;
-		case 1:
-		  return OPCODE_SICT;
-		case 2:
-		  return OPCODE_LICW;
-		case 3:
-		  return OPCODE_SICW;
-		case 8:
-		  return OPCODE_LDCT;
-		case 9:
-		  return OPCODE_SDCT;
-		case 14:
-		  if (Field_t_Slot_inst_get (insn) == 0)
-		    return OPCODE_RFDO;
-		  if (Field_t_Slot_inst_get (insn) == 1)
-		    return OPCODE_RFDD;
-		  break;
-		case 15:
-		  return OPCODE_LDPTE;
+		  if (Field_s_Slot_inst_get (insn) == 0 &&
+		      Field_t_Slot_inst_get (insn) == 0)
+		    return OPCODE_SYSCALL;
+		  if (Field_s_Slot_inst_get (insn) == 1 &&
+		      Field_t_Slot_inst_get (insn) == 0)
+		    return OPCODE_SIMCALL;
 		}
-	      break;
+	      if (Field_r_Slot_inst_get (insn) == 6)
+		return OPCODE_RSIL;
+	      if (Field_r_Slot_inst_get (insn) == 7 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_WAITI;
+	      if (Field_r_Slot_inst_get (insn) == 8)
+		return OPCODE_ANY4;
+	      if (Field_r_Slot_inst_get (insn) == 9)
+		return OPCODE_ALL4;
+	      if (Field_r_Slot_inst_get (insn) == 10)
+		return OPCODE_ANY8;
+	      if (Field_r_Slot_inst_get (insn) == 11)
+		return OPCODE_ALL8;
 	    }
-	  break;
-	case 2:
-	  switch (Field_op2_Slot_inst_get (insn))
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    return OPCODE_AND;
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_OR;
+	  if (Field_op2_Slot_inst_get (insn) == 3)
+	    return OPCODE_XOR;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
 	    {
-	    case 0:
-	      return OPCODE_ANDB;
-	    case 1:
-	      return OPCODE_ANDBC;
-	    case 2:
-	      return OPCODE_ORB;
-	    case 3:
-	      return OPCODE_ORBC;
-	    case 4:
-	      return OPCODE_XORB;
-	    case 8:
-	      return OPCODE_MULL;
+	      if (Field_r_Slot_inst_get (insn) == 0 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSR;
+	      if (Field_r_Slot_inst_get (insn) == 1 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSL;
+	      if (Field_r_Slot_inst_get (insn) == 2 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSA8L;
+	      if (Field_r_Slot_inst_get (insn) == 3 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_SSA8B;
+	      if (Field_r_Slot_inst_get (insn) == 4 &&
+		  Field_thi3_Slot_inst_get (insn) == 0)
+		return OPCODE_SSAI;
+	      if (Field_r_Slot_inst_get (insn) == 6)
+		return OPCODE_RER;
+	      if (Field_r_Slot_inst_get (insn) == 7)
+		return OPCODE_WER;
+	      if (Field_r_Slot_inst_get (insn) == 8 &&
+		  Field_s_Slot_inst_get (insn) == 0)
+		return OPCODE_ROTW;
+	      if (Field_r_Slot_inst_get (insn) == 14)
+		return OPCODE_NSA;
+	      if (Field_r_Slot_inst_get (insn) == 15)
+		return OPCODE_NSAU;
 	    }
-	  break;
-	case 3:
-	  switch (Field_op2_Slot_inst_get (insn))
+	  if (Field_op2_Slot_inst_get (insn) == 5)
 	    {
-	    case 0:
-	      switch (Field_sr_Slot_inst_get (insn))
-		{
-		case 0:
-		  return OPCODE_RSR_LBEG;
-		case 1:
-		  return OPCODE_RSR_LEND;
-		case 2:
-		  return OPCODE_RSR_LCOUNT;
-		case 3:
-		  return OPCODE_RSR_SAR;
-		case 4:
-		  return OPCODE_RSR_BR;
-		case 5:
-		  return OPCODE_RSR_LITBASE;
-		case 12:
-		  return OPCODE_RSR_SCOMPARE1;
-		case 72:
-		  return OPCODE_RSR_WINDOWBASE;
-		case 73:
-		  return OPCODE_RSR_WINDOWSTART;
-		case 83:
-		  return OPCODE_RSR_PTEVADDR;
-		case 90:
-		  return OPCODE_RSR_RASID;
-		case 91:
-		  return OPCODE_RSR_ITLBCFG;
-		case 92:
-		  return OPCODE_RSR_DTLBCFG;
-		case 99:
-		  return OPCODE_RSR_ATOMCTL;
-		case 104:
-		  return OPCODE_RSR_DDR;
-		case 176:
-		  return OPCODE_RSR_176;
-		case 177:
-		  return OPCODE_RSR_EPC1;
-		case 178:
-		  return OPCODE_RSR_EPC2;
-		case 192:
-		  return OPCODE_RSR_DEPC;
-		case 194:
-		  return OPCODE_RSR_EPS2;
-		case 208:
-		  return OPCODE_RSR_208;
-		case 209:
-		  return OPCODE_RSR_EXCSAVE1;
-		case 210:
-		  return OPCODE_RSR_EXCSAVE2;
-		case 224:
-		  return OPCODE_RSR_CPENABLE;
-		case 226:
-		  return OPCODE_RSR_INTERRUPT;
-		case 228:
-		  return OPCODE_RSR_INTENABLE;
-		case 230:
-		  return OPCODE_RSR_PS;
-		case 231:
-		  return OPCODE_RSR_VECBASE;
-		case 232:
-		  return OPCODE_RSR_EXCCAUSE;
-		case 233:
-		  return OPCODE_RSR_DEBUGCAUSE;
-		case 234:
-		  return OPCODE_RSR_CCOUNT;
-		case 235:
-		  return OPCODE_RSR_PRID;
-		case 236:
-		  return OPCODE_RSR_ICOUNT;
-		case 237:
-		  return OPCODE_RSR_ICOUNTLEVEL;
-		case 238:
-		  return OPCODE_RSR_EXCVADDR;
-		case 240:
-		  return OPCODE_RSR_CCOMPARE0;
-		case 241:
-		  return OPCODE_RSR_CCOMPARE1;
-		case 244:
-		  return OPCODE_RSR_MISC0;
-		case 245:
-		  return OPCODE_RSR_MISC1;
-		}
-	      break;
-	    case 1:
-	      switch (Field_sr_Slot_inst_get (insn))
-		{
-		case 0:
-		  return OPCODE_WSR_LBEG;
-		case 1:
-		  return OPCODE_WSR_LEND;
-		case 2:
-		  return OPCODE_WSR_LCOUNT;
-		case 3:
-		  return OPCODE_WSR_SAR;
-		case 4:
-		  return OPCODE_WSR_BR;
-		case 5:
-		  return OPCODE_WSR_LITBASE;
-		case 12:
-		  return OPCODE_WSR_SCOMPARE1;
-		case 72:
-		  return OPCODE_WSR_WINDOWBASE;
-		case 73:
-		  return OPCODE_WSR_WINDOWSTART;
-		case 83:
-		  return OPCODE_WSR_PTEVADDR;
-		case 90:
-		  return OPCODE_WSR_RASID;
-		case 91:
-		  return OPCODE_WSR_ITLBCFG;
-		case 92:
-		  return OPCODE_WSR_DTLBCFG;
-		case 99:
-		  return OPCODE_WSR_ATOMCTL;
-		case 104:
-		  return OPCODE_WSR_DDR;
-		case 176:
-		  return OPCODE_WSR_176;
-		case 177:
-		  return OPCODE_WSR_EPC1;
-		case 178:
-		  return OPCODE_WSR_EPC2;
-		case 192:
-		  return OPCODE_WSR_DEPC;
-		case 194:
-		  return OPCODE_WSR_EPS2;
-		case 209:
-		  return OPCODE_WSR_EXCSAVE1;
-		case 210:
-		  return OPCODE_WSR_EXCSAVE2;
-		case 224:
-		  return OPCODE_WSR_CPENABLE;
-		case 226:
-		  return OPCODE_WSR_INTSET;
-		case 227:
-		  return OPCODE_WSR_INTCLEAR;
-		case 228:
-		  return OPCODE_WSR_INTENABLE;
-		case 230:
-		  return OPCODE_WSR_PS;
-		case 231:
-		  return OPCODE_WSR_VECBASE;
-		case 232:
-		  return OPCODE_WSR_EXCCAUSE;
-		case 233:
-		  return OPCODE_WSR_DEBUGCAUSE;
-		case 234:
-		  return OPCODE_WSR_CCOUNT;
-		case 236:
-		  return OPCODE_WSR_ICOUNT;
-		case 237:
-		  return OPCODE_WSR_ICOUNTLEVEL;
-		case 238:
-		  return OPCODE_WSR_EXCVADDR;
-		case 240:
-		  return OPCODE_WSR_CCOMPARE0;
-		case 241:
-		  return OPCODE_WSR_CCOMPARE1;
-		case 244:
-		  return OPCODE_WSR_MISC0;
-		case 245:
-		  return OPCODE_WSR_MISC1;
-		}
-	      break;
-	    case 2:
-	      return OPCODE_SEXT;
-	    case 3:
-	      return OPCODE_CLAMPS;
-	    case 4:
-	      return OPCODE_MIN;
-	    case 5:
-	      return OPCODE_MAX;
-	    case 6:
-	      return OPCODE_MINU;
-	    case 7:
-	      return OPCODE_MAXU;
-	    case 8:
-	      return OPCODE_MOVEQZ;
-	    case 9:
-	      return OPCODE_MOVNEZ;
-	    case 10:
-	      return OPCODE_MOVLTZ;
-	    case 11:
-	      return OPCODE_MOVGEZ;
-	    case 12:
-	      return OPCODE_MOVF;
-	    case 13:
-	      return OPCODE_MOVT;
-	    case 14:
-	      switch (Field_st_Slot_inst_get (insn))
-		{
-		case 231:
-		  return OPCODE_RUR_THREADPTR;
-		case 240:
-		  return OPCODE_RUR_AE_OVF_SAR;
-		case 241:
-		  return OPCODE_RUR_AE_BITHEAD;
-		case 242:
-		  return OPCODE_RUR_AE_TS_FTS_BU_BP;
-		case 243:
-		  return OPCODE_RUR_AE_SD_NO;
-		}
-	      break;
-	    case 15:
-	      switch (Field_sr_Slot_inst_get (insn))
-		{
-		case 231:
-		  return OPCODE_WUR_THREADPTR;
-		case 240:
-		  return OPCODE_WUR_AE_OVF_SAR;
-		case 241:
-		  return OPCODE_WUR_AE_BITHEAD;
-		case 242:
-		  return OPCODE_WUR_AE_TS_FTS_BU_BP;
-		case 243:
-		  return OPCODE_WUR_AE_SD_NO;
-		}
-	      break;
+	      if (Field_r_Slot_inst_get (insn) == 1)
+		return OPCODE_HWWITLBA;
+	      if (Field_r_Slot_inst_get (insn) == 3)
+		return OPCODE_RITLB0;
+	      if (Field_r_Slot_inst_get (insn) == 4 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_IITLB;
+	      if (Field_r_Slot_inst_get (insn) == 5)
+		return OPCODE_PITLB;
+	      if (Field_r_Slot_inst_get (insn) == 6)
+		return OPCODE_WITLB;
+	      if (Field_r_Slot_inst_get (insn) == 7)
+		return OPCODE_RITLB1;
+	      if (Field_r_Slot_inst_get (insn) == 9)
+		return OPCODE_HWWDTLBA;
+	      if (Field_r_Slot_inst_get (insn) == 11)
+		return OPCODE_RDTLB0;
+	      if (Field_r_Slot_inst_get (insn) == 12 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_IDTLB;
+	      if (Field_r_Slot_inst_get (insn) == 13)
+		return OPCODE_PDTLB;
+	      if (Field_r_Slot_inst_get (insn) == 14)
+		return OPCODE_WDTLB;
+	      if (Field_r_Slot_inst_get (insn) == 15)
+		return OPCODE_RDTLB1;
 	    }
-	  break;
-	case 4:
-	case 5:
-	  return OPCODE_EXTUI;
-	case 9:
-	  switch (Field_op2_Slot_inst_get (insn))
+	  if (Field_op2_Slot_inst_get (insn) == 6)
 	    {
-	    case 0:
-	      return OPCODE_L32E;
-	    case 4:
-	      return OPCODE_S32E;
+	      if (Field_s_Slot_inst_get (insn) == 0)
+		return OPCODE_NEG;
+	      if (Field_s_Slot_inst_get (insn) == 1)
+		return OPCODE_ABS;
 	    }
-	  break;
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_ADD;
+	  if (Field_op2_Slot_inst_get (insn) == 9)
+	    return OPCODE_ADDX2;
+	  if (Field_op2_Slot_inst_get (insn) == 10)
+	    return OPCODE_ADDX4;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_ADDX8;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_SUB;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_SUBX2;
+	  if (Field_op2_Slot_inst_get (insn) == 14)
+	    return OPCODE_SUBX4;
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    return OPCODE_SUBX8;
 	}
-      break;
-    case 1:
-      return OPCODE_L32R;
-    case 2:
-      switch (Field_r_Slot_inst_get (insn))
+      if (Field_op1_Slot_inst_get (insn) == 1)
 	{
-	case 0:
-	  return OPCODE_L8UI;
-	case 1:
-	  return OPCODE_L16UI;
-	case 2:
-	  return OPCODE_L32I;
-	case 4:
-	  return OPCODE_S8I;
-	case 5:
-	  return OPCODE_S16I;
-	case 6:
-	  return OPCODE_S32I;
-	case 7:
-	  switch (Field_t_Slot_inst_get (insn))
+	  if ((Field_op2_Slot_inst_get (insn) == 0 ||
+	       Field_op2_Slot_inst_get (insn) == 1))
+	    return OPCODE_SLLI;
+	  if ((Field_op2_Slot_inst_get (insn) == 2 ||
+	       Field_op2_Slot_inst_get (insn) == 3))
+	    return OPCODE_SRAI;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_SRLI;
+	  if (Field_op2_Slot_inst_get (insn) == 6)
 	    {
-	    case 0:
-	      return OPCODE_DPFR;
-	    case 1:
-	      return OPCODE_DPFW;
-	    case 2:
-	      return OPCODE_DPFRO;
-	    case 3:
-	      return OPCODE_DPFWO;
-	    case 4:
-	      return OPCODE_DHWB;
-	    case 5:
-	      return OPCODE_DHWBI;
-	    case 6:
-	      return OPCODE_DHI;
-	    case 7:
-	      return OPCODE_DII;
-	    case 8:
-	      switch (Field_op1_Slot_inst_get (insn))
-		{
-		case 4:
-		  return OPCODE_DIWB;
-		case 5:
-		  return OPCODE_DIWBI;
-		}
-	      break;
-	    case 12:
-	      return OPCODE_IPF;
-	    case 14:
-	      return OPCODE_IHI;
-	    case 15:
-	      return OPCODE_III;
+	      if (Field_sr_Slot_inst_get (insn) == 0)
+		return OPCODE_XSR_LBEG;
+	      if (Field_sr_Slot_inst_get (insn) == 1)
+		return OPCODE_XSR_LEND;
+	      if (Field_sr_Slot_inst_get (insn) == 2)
+		return OPCODE_XSR_LCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 3)
+		return OPCODE_XSR_SAR;
+	      if (Field_sr_Slot_inst_get (insn) == 4)
+		return OPCODE_XSR_BR;
+	      if (Field_sr_Slot_inst_get (insn) == 5)
+		return OPCODE_XSR_LITBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 12)
+		return OPCODE_XSR_SCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 72)
+		return OPCODE_XSR_WINDOWBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 73)
+		return OPCODE_XSR_WINDOWSTART;
+	      if (Field_sr_Slot_inst_get (insn) == 83)
+		return OPCODE_XSR_PTEVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 90)
+		return OPCODE_XSR_RASID;
+	      if (Field_sr_Slot_inst_get (insn) == 91)
+		return OPCODE_XSR_ITLBCFG;
+	      if (Field_sr_Slot_inst_get (insn) == 92)
+		return OPCODE_XSR_DTLBCFG;
+	      if (Field_sr_Slot_inst_get (insn) == 99)
+		return OPCODE_XSR_ATOMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 104)
+		return OPCODE_XSR_DDR;
+	      if (Field_sr_Slot_inst_get (insn) == 177)
+		return OPCODE_XSR_EPC1;
+	      if (Field_sr_Slot_inst_get (insn) == 178)
+		return OPCODE_XSR_EPC2;
+	      if (Field_sr_Slot_inst_get (insn) == 192)
+		return OPCODE_XSR_DEPC;
+	      if (Field_sr_Slot_inst_get (insn) == 194)
+		return OPCODE_XSR_EPS2;
+	      if (Field_sr_Slot_inst_get (insn) == 209)
+		return OPCODE_XSR_EXCSAVE1;
+	      if (Field_sr_Slot_inst_get (insn) == 210)
+		return OPCODE_XSR_EXCSAVE2;
+	      if (Field_sr_Slot_inst_get (insn) == 224)
+		return OPCODE_XSR_CPENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 228)
+		return OPCODE_XSR_INTENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 230)
+		return OPCODE_XSR_PS;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_XSR_VECBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 232)
+		return OPCODE_XSR_EXCCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 233)
+		return OPCODE_XSR_DEBUGCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 234)
+		return OPCODE_XSR_CCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 236)
+		return OPCODE_XSR_ICOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 237)
+		return OPCODE_XSR_ICOUNTLEVEL;
+	      if (Field_sr_Slot_inst_get (insn) == 238)
+		return OPCODE_XSR_EXCVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 240)
+		return OPCODE_XSR_CCOMPARE0;
+	      if (Field_sr_Slot_inst_get (insn) == 241)
+		return OPCODE_XSR_CCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 244)
+		return OPCODE_XSR_MISC0;
+	      if (Field_sr_Slot_inst_get (insn) == 245)
+		return OPCODE_XSR_MISC1;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_SRC;
+	  if (Field_op2_Slot_inst_get (insn) == 9 &&
+	      Field_s_Slot_inst_get (insn) == 0)
+	    return OPCODE_SRL;
+	  if (Field_op2_Slot_inst_get (insn) == 10 &&
+	      Field_t_Slot_inst_get (insn) == 0)
+	    return OPCODE_SLL;
+	  if (Field_op2_Slot_inst_get (insn) == 11 &&
+	      Field_s_Slot_inst_get (insn) == 0)
+	    return OPCODE_SRA;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_MUL16U;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_MUL16S;
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    {
+	      if (Field_r_Slot_inst_get (insn) == 0)
+		return OPCODE_LICT;
+	      if (Field_r_Slot_inst_get (insn) == 1)
+		return OPCODE_SICT;
+	      if (Field_r_Slot_inst_get (insn) == 2)
+		return OPCODE_LICW;
+	      if (Field_r_Slot_inst_get (insn) == 3)
+		return OPCODE_SICW;
+	      if (Field_r_Slot_inst_get (insn) == 8)
+		return OPCODE_LDCT;
+	      if (Field_r_Slot_inst_get (insn) == 9)
+		return OPCODE_SDCT;
+	      if (Field_r_Slot_inst_get (insn) == 14 &&
+		  Field_t_Slot_inst_get (insn) == 0)
+		return OPCODE_RFDO;
+	      if (Field_r_Slot_inst_get (insn) == 14 &&
+		  Field_t_Slot_inst_get (insn) == 1)
+		return OPCODE_RFDD;
+	      if (Field_r_Slot_inst_get (insn) == 15)
+		return OPCODE_LDPTE;
 	    }
-	  break;
-	case 9:
-	  return OPCODE_L16SI;
-	case 10:
-	  return OPCODE_MOVI;
-	case 11:
-	  return OPCODE_L32AI;
-	case 12:
-	  return OPCODE_ADDI;
-	case 13:
-	  return OPCODE_ADDMI;
-	case 14:
-	  return OPCODE_S32C1I;
-	case 15:
-	  return OPCODE_S32RI;
-	}
-      break;
-    case 4:
-      switch (Field_ae_r10_Slot_inst_get (insn))
-	{
-	case 0:
-	  if (Field_op1_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_LQ56_I;
-	  if (Field_op1_Slot_inst_get (insn) == 2 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_LQ56_X;
-	  break;
-	case 1:
-	  if (Field_op1_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_LQ32F_I;
-	  if (Field_op1_Slot_inst_get (insn) == 2 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_LQ32F_X;
-	  break;
-	case 2:
-	  if (Field_op1_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_LQ56_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 2 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_LQ56_XU;
-	  if (Field_op1_Slot_inst_get (insn) == 7 &&
-	      Field_t_Slot_inst_get (insn) == 3 &&
-	      Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_CVTQ48A32S;
-	  break;
-	case 3:
-	  if (Field_op1_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_LQ32F_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 2 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_LQ32F_XU;
-	  break;
-	}
-      switch (Field_ae_r3_Slot_inst_get (insn))
-	{
-	case 0:
-	  if (Field_op1_Slot_inst_get (insn) == 5 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP16F_I;
-	  if (Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP16F_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 12 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP16F_X;
-	  if (Field_op1_Slot_inst_get (insn) == 15 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP16F_XU;
-	  if (Field_op1_Slot_inst_get (insn) == 6 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP24F_I;
-	  if (Field_op1_Slot_inst_get (insn) == 10 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP24F_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 13 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP24F_X;
-	  if (Field_op1_Slot_inst_get (insn) == 0 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_LP24F_XU;
-	  if (Field_op1_Slot_inst_get (insn) == 7 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP24X2F_I;
-	  if (Field_op1_Slot_inst_get (insn) == 11 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP24X2F_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 14 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP24X2F_X;
-	  if (Field_op1_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_LP24X2F_XU;
-	  if (Field_op1_Slot_inst_get (insn) == 2 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP16X2F_I;
-	  if (Field_op1_Slot_inst_get (insn) == 5 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP16X2F_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 8 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP16X2F_X;
-	  if (Field_op1_Slot_inst_get (insn) == 11 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP16X2F_XU;
-	  if (Field_op1_Slot_inst_get (insn) == 3 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24X2F_I;
-	  if (Field_op1_Slot_inst_get (insn) == 6 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24X2F_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24X2F_X;
-	  if (Field_op1_Slot_inst_get (insn) == 12 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24X2F_XU;
-	  if (Field_op1_Slot_inst_get (insn) == 4 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24S_L_I;
-	  if (Field_op1_Slot_inst_get (insn) == 7 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24S_L_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 10 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24S_L_X;
-	  if (Field_op1_Slot_inst_get (insn) == 13 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24S_L_XU;
-	  if (Field_ae_s3_Slot_inst_get (insn) == 0 &&
-	      Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_MOVP48;
-	  if (Field_op1_Slot_inst_get (insn) == 0 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_MOVPA24X2;
-	  if (Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 11 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_CVTA32P24_L;
-	  if (Field_op1_Slot_inst_get (insn) == 14 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_CVTP24A16X2_LL;
-	  if (Field_op1_Slot_inst_get (insn) == 15 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_CVTP24A16X2_HL;
-	  if (Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 7 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_MOVAP24S_L;
-	  if (Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 8 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_TRUNCA16P24S_L;
-	  break;
-	case 1:
-	  if (Field_op1_Slot_inst_get (insn) == 5 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP24_I;
-	  if (Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP24_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 12 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP24_X;
-	  if (Field_op1_Slot_inst_get (insn) == 15 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP24_XU;
-	  if (Field_op1_Slot_inst_get (insn) == 6 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP16X2F_I;
-	  if (Field_op1_Slot_inst_get (insn) == 10 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP16X2F_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 13 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP16X2F_X;
-	  if (Field_op1_Slot_inst_get (insn) == 0 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_LP16X2F_XU;
-	  if (Field_op1_Slot_inst_get (insn) == 7 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP24X2_I;
-	  if (Field_op1_Slot_inst_get (insn) == 11 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP24X2_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 14 &&
-	      Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LP24X2_X;
-	  if (Field_op1_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_LP24X2_XU;
-	  if (Field_op1_Slot_inst_get (insn) == 2 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24X2S_I;
-	  if (Field_op1_Slot_inst_get (insn) == 5 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24X2S_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 8 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24X2S_X;
-	  if (Field_op1_Slot_inst_get (insn) == 11 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24X2S_XU;
-	  if (Field_op1_Slot_inst_get (insn) == 3 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP16F_L_I;
-	  if (Field_op1_Slot_inst_get (insn) == 6 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP16F_L_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP16F_L_X;
-	  if (Field_op1_Slot_inst_get (insn) == 12 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP16F_L_XU;
-	  if (Field_op1_Slot_inst_get (insn) == 4 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24F_L_I;
-	  if (Field_op1_Slot_inst_get (insn) == 7 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24F_L_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 10 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24F_L_X;
-	  if (Field_op1_Slot_inst_get (insn) == 13 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_SP24F_L_XU;
-	  if (Field_op1_Slot_inst_get (insn) == 0 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_TRUNCP24A32X2;
-	  if (Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 11 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_CVTA32P24_H;
-	  if (Field_op1_Slot_inst_get (insn) == 14 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_CVTP24A16X2_LH;
-	  if (Field_op1_Slot_inst_get (insn) == 15 &&
-	      Field_op2_Slot_inst_get (insn) == 11)
-	    return OPCODE_AE_CVTP24A16X2_HH;
-	  if (Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 7 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_MOVAP24S_H;
-	  if (Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 8 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_TRUNCA16P24S_H;
-	  break;
-	}
-      switch (Field_ae_r32_Slot_inst_get (insn))
-	{
-	case 0:
-	  if (Field_op1_Slot_inst_get (insn) == 3 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SQ56S_I;
-	  if (Field_op1_Slot_inst_get (insn) == 4 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SQ56S_X;
-	  if (Field_op1_Slot_inst_get (insn) == 7 &&
-	      Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_TRUNCA32Q48;
-	  break;
-	case 1:
-	  if (Field_op1_Slot_inst_get (insn) == 3 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SQ32F_I;
-	  if (Field_op1_Slot_inst_get (insn) == 4 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SQ32F_X;
-	  if (Field_op1_Slot_inst_get (insn) == 7 &&
-	      Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_NSAQ56S;
-	  break;
-	case 2:
-	  if (Field_op1_Slot_inst_get (insn) == 3 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SQ56S_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 4 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SQ56S_XU;
-	  break;
-	case 3:
-	  if (Field_op1_Slot_inst_get (insn) == 3 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SQ32F_IU;
-	  if (Field_op1_Slot_inst_get (insn) == 4 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SQ32F_XU;
-	  break;
 	}
-      switch (Field_ae_s_non_samt_Slot_inst_get (insn))
+      if (Field_op1_Slot_inst_get (insn) == 2)
 	{
-	case 0:
-	  if (Field_op1_Slot_inst_get (insn) == 5 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SLLIQ56;
-	  break;
-	case 1:
-	  if (Field_op1_Slot_inst_get (insn) == 5 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SRLIQ56;
-	  break;
-	case 2:
-	  if (Field_op1_Slot_inst_get (insn) == 5 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SRAIQ56;
-	  break;
-	case 3:
-	  if (Field_op1_Slot_inst_get (insn) == 5 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SLLISQ56S;
-	  break;
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    return OPCODE_ANDB;
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    return OPCODE_ANDBC;
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_ORB;
+	  if (Field_op2_Slot_inst_get (insn) == 3)
+	    return OPCODE_ORBC;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_XORB;
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_MULL;
 	}
-      switch (Field_op1_Slot_inst_get (insn))
+      if (Field_op1_Slot_inst_get (insn) == 3)
 	{
-	case 0:
-	  if (Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_SHA32;
-	  if (Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_VLDL32T;
-	  break;
-	case 1:
-	  if (Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_SLLAQ56;
-	  if (Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_VLDL16T;
-	  break;
-	case 2:
-	  if (Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_SRLAQ56;
-	  if (Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_LBK;
-	  break;
-	case 3:
-	  if (Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_SRAAQ56;
-	  if (Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_VLEL32T;
-	  break;
-	case 4:
-	  if (Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_SLLASQ56S;
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 0)
+		return OPCODE_RSR_LBEG;
+	      if (Field_sr_Slot_inst_get (insn) == 1)
+		return OPCODE_RSR_LEND;
+	      if (Field_sr_Slot_inst_get (insn) == 2)
+		return OPCODE_RSR_LCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 3)
+		return OPCODE_RSR_SAR;
+	      if (Field_sr_Slot_inst_get (insn) == 4)
+		return OPCODE_RSR_BR;
+	      if (Field_sr_Slot_inst_get (insn) == 5)
+		return OPCODE_RSR_LITBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 12)
+		return OPCODE_RSR_SCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 72)
+		return OPCODE_RSR_WINDOWBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 73)
+		return OPCODE_RSR_WINDOWSTART;
+	      if (Field_sr_Slot_inst_get (insn) == 83)
+		return OPCODE_RSR_PTEVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 90)
+		return OPCODE_RSR_RASID;
+	      if (Field_sr_Slot_inst_get (insn) == 91)
+		return OPCODE_RSR_ITLBCFG;
+	      if (Field_sr_Slot_inst_get (insn) == 92)
+		return OPCODE_RSR_DTLBCFG;
+	      if (Field_sr_Slot_inst_get (insn) == 99)
+		return OPCODE_RSR_ATOMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 104)
+		return OPCODE_RSR_DDR;
+	      if (Field_sr_Slot_inst_get (insn) == 176)
+		return OPCODE_RSR_CONFIGID0;
+	      if (Field_sr_Slot_inst_get (insn) == 177)
+		return OPCODE_RSR_EPC1;
+	      if (Field_sr_Slot_inst_get (insn) == 178)
+		return OPCODE_RSR_EPC2;
+	      if (Field_sr_Slot_inst_get (insn) == 192)
+		return OPCODE_RSR_DEPC;
+	      if (Field_sr_Slot_inst_get (insn) == 194)
+		return OPCODE_RSR_EPS2;
+	      if (Field_sr_Slot_inst_get (insn) == 208)
+		return OPCODE_RSR_CONFIGID1;
+	      if (Field_sr_Slot_inst_get (insn) == 209)
+		return OPCODE_RSR_EXCSAVE1;
+	      if (Field_sr_Slot_inst_get (insn) == 210)
+		return OPCODE_RSR_EXCSAVE2;
+	      if (Field_sr_Slot_inst_get (insn) == 224)
+		return OPCODE_RSR_CPENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 226)
+		return OPCODE_RSR_INTERRUPT;
+	      if (Field_sr_Slot_inst_get (insn) == 228)
+		return OPCODE_RSR_INTENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 230)
+		return OPCODE_RSR_PS;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_RSR_VECBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 232)
+		return OPCODE_RSR_EXCCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 233)
+		return OPCODE_RSR_DEBUGCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 234)
+		return OPCODE_RSR_CCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 235)
+		return OPCODE_RSR_PRID;
+	      if (Field_sr_Slot_inst_get (insn) == 236)
+		return OPCODE_RSR_ICOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 237)
+		return OPCODE_RSR_ICOUNTLEVEL;
+	      if (Field_sr_Slot_inst_get (insn) == 238)
+		return OPCODE_RSR_EXCVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 240)
+		return OPCODE_RSR_CCOMPARE0;
+	      if (Field_sr_Slot_inst_get (insn) == 241)
+		return OPCODE_RSR_CCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 244)
+		return OPCODE_RSR_MISC0;
+	      if (Field_sr_Slot_inst_get (insn) == 245)
+		return OPCODE_RSR_MISC1;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 1)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 0)
+		return OPCODE_WSR_LBEG;
+	      if (Field_sr_Slot_inst_get (insn) == 1)
+		return OPCODE_WSR_LEND;
+	      if (Field_sr_Slot_inst_get (insn) == 2)
+		return OPCODE_WSR_LCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 3)
+		return OPCODE_WSR_SAR;
+	      if (Field_sr_Slot_inst_get (insn) == 4)
+		return OPCODE_WSR_BR;
+	      if (Field_sr_Slot_inst_get (insn) == 5)
+		return OPCODE_WSR_LITBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 12)
+		return OPCODE_WSR_SCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 72)
+		return OPCODE_WSR_WINDOWBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 73)
+		return OPCODE_WSR_WINDOWSTART;
+	      if (Field_sr_Slot_inst_get (insn) == 83)
+		return OPCODE_WSR_PTEVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 90)
+		return OPCODE_WSR_RASID;
+	      if (Field_sr_Slot_inst_get (insn) == 91)
+		return OPCODE_WSR_ITLBCFG;
+	      if (Field_sr_Slot_inst_get (insn) == 92)
+		return OPCODE_WSR_DTLBCFG;
+	      if (Field_sr_Slot_inst_get (insn) == 99)
+		return OPCODE_WSR_ATOMCTL;
+	      if (Field_sr_Slot_inst_get (insn) == 104)
+		return OPCODE_WSR_DDR;
+	      if (Field_sr_Slot_inst_get (insn) == 176)
+		return OPCODE_WSR_CONFIGID0;
+	      if (Field_sr_Slot_inst_get (insn) == 177)
+		return OPCODE_WSR_EPC1;
+	      if (Field_sr_Slot_inst_get (insn) == 178)
+		return OPCODE_WSR_EPC2;
+	      if (Field_sr_Slot_inst_get (insn) == 192)
+		return OPCODE_WSR_DEPC;
+	      if (Field_sr_Slot_inst_get (insn) == 194)
+		return OPCODE_WSR_EPS2;
+	      if (Field_sr_Slot_inst_get (insn) == 209)
+		return OPCODE_WSR_EXCSAVE1;
+	      if (Field_sr_Slot_inst_get (insn) == 210)
+		return OPCODE_WSR_EXCSAVE2;
+	      if (Field_sr_Slot_inst_get (insn) == 224)
+		return OPCODE_WSR_CPENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 226)
+		return OPCODE_WSR_INTSET;
+	      if (Field_sr_Slot_inst_get (insn) == 227)
+		return OPCODE_WSR_INTCLEAR;
+	      if (Field_sr_Slot_inst_get (insn) == 228)
+		return OPCODE_WSR_INTENABLE;
+	      if (Field_sr_Slot_inst_get (insn) == 230)
+		return OPCODE_WSR_PS;
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_WSR_VECBASE;
+	      if (Field_sr_Slot_inst_get (insn) == 232)
+		return OPCODE_WSR_EXCCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 233)
+		return OPCODE_WSR_DEBUGCAUSE;
+	      if (Field_sr_Slot_inst_get (insn) == 234)
+		return OPCODE_WSR_CCOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 236)
+		return OPCODE_WSR_ICOUNT;
+	      if (Field_sr_Slot_inst_get (insn) == 237)
+		return OPCODE_WSR_ICOUNTLEVEL;
+	      if (Field_sr_Slot_inst_get (insn) == 238)
+		return OPCODE_WSR_EXCVADDR;
+	      if (Field_sr_Slot_inst_get (insn) == 240)
+		return OPCODE_WSR_CCOMPARE0;
+	      if (Field_sr_Slot_inst_get (insn) == 241)
+		return OPCODE_WSR_CCOMPARE1;
+	      if (Field_sr_Slot_inst_get (insn) == 244)
+		return OPCODE_WSR_MISC0;
+	      if (Field_sr_Slot_inst_get (insn) == 245)
+		return OPCODE_WSR_MISC1;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 2)
+	    return OPCODE_SEXT;
+	  if (Field_op2_Slot_inst_get (insn) == 3)
+	    return OPCODE_CLAMPS;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_MIN;
+	  if (Field_op2_Slot_inst_get (insn) == 5)
+	    return OPCODE_MAX;
+	  if (Field_op2_Slot_inst_get (insn) == 6)
+	    return OPCODE_MINU;
+	  if (Field_op2_Slot_inst_get (insn) == 7)
+	    return OPCODE_MAXU;
+	  if (Field_op2_Slot_inst_get (insn) == 8)
+	    return OPCODE_MOVEQZ;
+	  if (Field_op2_Slot_inst_get (insn) == 9)
+	    return OPCODE_MOVNEZ;
 	  if (Field_op2_Slot_inst_get (insn) == 10)
-	    return OPCODE_AE_VLEL16T;
-	  break;
-	case 5:
-	  if (Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_MOVTQ56;
-	  break;
-	case 6:
-	  if (Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_MOVFQ56;
-	  break;
+	    return OPCODE_MOVLTZ;
+	  if (Field_op2_Slot_inst_get (insn) == 11)
+	    return OPCODE_MOVGEZ;
+	  if (Field_op2_Slot_inst_get (insn) == 12)
+	    return OPCODE_MOVF;
+	  if (Field_op2_Slot_inst_get (insn) == 13)
+	    return OPCODE_MOVT;
+	  if (Field_op2_Slot_inst_get (insn) == 14)
+	    {
+	      if (Field_st_Slot_inst_get (insn) == 231)
+		return OPCODE_RUR_THREADPTR;
+	      if (Field_st_Slot_inst_get (insn) == 240)
+		return OPCODE_RUR_AE_OVF_SAR;
+	      if (Field_st_Slot_inst_get (insn) == 241)
+		return OPCODE_RUR_AE_BITHEAD;
+	      if (Field_st_Slot_inst_get (insn) == 242)
+		return OPCODE_RUR_AE_TS_FTS_BU_BP;
+	      if (Field_st_Slot_inst_get (insn) == 243)
+		return OPCODE_RUR_AE_SD_NO;
+	    }
+	  if (Field_op2_Slot_inst_get (insn) == 15)
+	    {
+	      if (Field_sr_Slot_inst_get (insn) == 231)
+		return OPCODE_WUR_THREADPTR;
+	      if (Field_sr_Slot_inst_get (insn) == 240)
+		return OPCODE_WUR_AE_OVF_SAR;
+	      if (Field_sr_Slot_inst_get (insn) == 241)
+		return OPCODE_WUR_AE_BITHEAD;
+	      if (Field_sr_Slot_inst_get (insn) == 242)
+		return OPCODE_WUR_AE_TS_FTS_BU_BP;
+	      if (Field_sr_Slot_inst_get (insn) == 243)
+		return OPCODE_WUR_AE_SD_NO;
+	    }
 	}
-      switch (Field_r_Slot_inst_get (insn))
+      if ((Field_op1_Slot_inst_get (insn) == 4 ||
+	   Field_op1_Slot_inst_get (insn) == 5))
+	return OPCODE_EXTUI;
+      if (Field_op1_Slot_inst_get (insn) == 9)
 	{
-	case 0:
-	  if (Field_s_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 10 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_WUR_AE_OVERFLOW;
-	  if (Field_op2_Slot_inst_get (insn) == 15)
-	    return OPCODE_AE_SBI;
-	  break;
-	case 1:
-	  if (Field_s_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 10 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_WUR_AE_SAR;
-	  if (Field_op1_Slot_inst_get (insn) == 0 &&
-	      Field_op2_Slot_inst_get (insn) == 15)
-	    return OPCODE_AE_DB;
-	  if (Field_op1_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 15)
-	    return OPCODE_AE_SB;
-	  break;
-	case 2:
-	  if (Field_s_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 10 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_WUR_AE_BITPTR;
-	  break;
-	case 3:
-	  if (Field_s_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 10 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_WUR_AE_BITSUSED;
-	  break;
-	case 4:
-	  if (Field_s_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 10 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_WUR_AE_TABLESIZE;
-	  break;
-	case 5:
-	  if (Field_s_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 10 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_WUR_AE_FIRST_TS;
-	  break;
-	case 6:
-	  if (Field_s_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 10 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_WUR_AE_NEXTOFFSET;
-	  break;
-	case 7:
-	  if (Field_s_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 10 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_WUR_AE_SEARCHDONE;
-	  break;
-	case 8:
-	  if (Field_s_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 10 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_VLDSHT;
-	  break;
-	case 12:
-	  if (Field_op1_Slot_inst_get (insn) == 7 &&
-	      Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_VLES16C;
-	  break;
-	case 13:
-	  if (Field_op1_Slot_inst_get (insn) == 7 &&
-	      Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_SBF;
-	  break;
-	case 14:
-	  if (Field_op1_Slot_inst_get (insn) == 7 &&
-	      Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_VLDL16C;
-	  break;
+	  if (Field_op2_Slot_inst_get (insn) == 0)
+	    return OPCODE_L32E;
+	  if (Field_op2_Slot_inst_get (insn) == 4)
+	    return OPCODE_S32E;
 	}
-      switch (Field_s_Slot_inst_get (insn))
+    }
+  if (Field_op0_Slot_inst_get (insn) == 1)
+    return OPCODE_L32R;
+  if (Field_op0_Slot_inst_get (insn) == 2)
+    {
+      if (Field_r_Slot_inst_get (insn) == 0)
+	return OPCODE_L8UI;
+      if (Field_r_Slot_inst_get (insn) == 1)
+	return OPCODE_L16UI;
+      if (Field_r_Slot_inst_get (insn) == 2)
+	return OPCODE_L32I;
+      if (Field_r_Slot_inst_get (insn) == 4)
+	return OPCODE_S8I;
+      if (Field_r_Slot_inst_get (insn) == 5)
+	return OPCODE_S16I;
+      if (Field_r_Slot_inst_get (insn) == 6)
+	return OPCODE_S32I;
+      if (Field_r_Slot_inst_get (insn) == 7)
 	{
-	case 0:
-	  if (Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SLLSQ56;
-	  if (Field_op1_Slot_inst_get (insn) == 6 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_LB;
-	  break;
-	case 1:
-	  if (Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SRLSQ56;
-	  break;
-	case 2:
-	  if (Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SRASQ56;
-	  break;
-	case 3:
-	  if (Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_SLLSSQ56S;
-	  break;
-	case 4:
-	  if (Field_t_Slot_inst_get (insn) == 1 &&
-	      Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_AE_MOVQ56;
-	  break;
-	case 8:
-	  if (Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_RUR_AE_OVERFLOW;
-	  break;
-	case 9:
-	  if (Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_RUR_AE_SAR;
-	  break;
-	case 10:
-	  if (Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_RUR_AE_BITPTR;
-	  break;
-	case 11:
-	  if (Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_RUR_AE_BITSUSED;
-	  break;
-	case 12:
-	  if (Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_RUR_AE_TABLESIZE;
-	  break;
-	case 13:
-	  if (Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_RUR_AE_FIRST_TS;
-	  break;
-	case 14:
-	  if (Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_RUR_AE_NEXTOFFSET;
-	  break;
-	case 15:
-	  if (Field_t_Slot_inst_get (insn) == 0 &&
-	      Field_op1_Slot_inst_get (insn) == 9 &&
-	      Field_op2_Slot_inst_get (insn) == 12)
-	    return OPCODE_RUR_AE_SEARCHDONE;
-	  break;
+	  if (Field_t_Slot_inst_get (insn) == 0)
+	    return OPCODE_DPFR;
+	  if (Field_t_Slot_inst_get (insn) == 1)
+	    return OPCODE_DPFW;
+	  if (Field_t_Slot_inst_get (insn) == 2)
+	    return OPCODE_DPFRO;
+	  if (Field_t_Slot_inst_get (insn) == 3)
+	    return OPCODE_DPFWO;
+	  if (Field_t_Slot_inst_get (insn) == 4)
+	    return OPCODE_DHWB;
+	  if (Field_t_Slot_inst_get (insn) == 5)
+	    return OPCODE_DHWBI;
+	  if (Field_t_Slot_inst_get (insn) == 6)
+	    return OPCODE_DHI;
+	  if (Field_t_Slot_inst_get (insn) == 7)
+	    return OPCODE_DII;
+	  if (Field_t_Slot_inst_get (insn) == 8)
+	    {
+	      if (Field_op1_Slot_inst_get (insn) == 4)
+		return OPCODE_DIWB;
+	      if (Field_op1_Slot_inst_get (insn) == 5)
+		return OPCODE_DIWBI;
+	    }
+	  if (Field_t_Slot_inst_get (insn) == 12)
+	    return OPCODE_IPF;
+	  if (Field_t_Slot_inst_get (insn) == 14)
+	    return OPCODE_IHI;
+	  if (Field_t_Slot_inst_get (insn) == 15)
+	    return OPCODE_III;
 	}
-      switch (Field_t_Slot_inst_get (insn))
+      if (Field_r_Slot_inst_get (insn) == 9)
+	return OPCODE_L16SI;
+      if (Field_r_Slot_inst_get (insn) == 10)
+	return OPCODE_MOVI;
+      if (Field_r_Slot_inst_get (insn) == 11)
+	return OPCODE_L32AI;
+      if (Field_r_Slot_inst_get (insn) == 12)
+	return OPCODE_ADDI;
+      if (Field_r_Slot_inst_get (insn) == 13)
+	return OPCODE_ADDMI;
+      if (Field_r_Slot_inst_get (insn) == 14)
+	return OPCODE_S32C1I;
+      if (Field_r_Slot_inst_get (insn) == 15)
+	return OPCODE_S32RI;
+    }
+  if (Field_op0_Slot_inst_get (insn) == 4)
+    {
+      if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_LQ56_I;
+      if (Field_ae_r10_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 2 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_LQ56_X;
+      if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_LQ32F_I;
+      if (Field_ae_r10_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 2 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_LQ32F_X;
+      if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
+	  Field_op1_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_LQ56_IU;
+      if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
+	  Field_op1_Slot_inst_get (insn) == 2 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_LQ56_XU;
+      if (Field_ae_r10_Slot_inst_get (insn) == 2 &&
+	  Field_op1_Slot_inst_get (insn) == 7 &&
+	  Field_t_Slot_inst_get (insn) == 3 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_CVTQ48A32S;
+      if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
+	  Field_op1_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_LQ32F_IU;
+      if (Field_ae_r10_Slot_inst_get (insn) == 3 &&
+	  Field_op1_Slot_inst_get (insn) == 2 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_LQ32F_XU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 5 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP16F_I;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP16F_IU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 12 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP16F_X;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 15 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP16F_XU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 6 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP24F_I;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 10 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP24F_IU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 13 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP24F_X;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 0 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_LP24F_XU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 7 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP24X2F_I;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 11 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP24X2F_IU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 14 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP24X2F_X;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_LP24X2F_XU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 2 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP16X2F_I;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 5 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP16X2F_IU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 8 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP16X2F_X;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 11 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP16X2F_XU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 3 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24X2F_I;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 6 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24X2F_IU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24X2F_X;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 12 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24X2F_XU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 4 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24S_L_I;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 7 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24S_L_IU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 10 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24S_L_X;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 13 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24S_L_XU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_ae_s3_Slot_inst_get (insn) == 0 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_MOVP48;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 0 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_MOVPA24X2;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 11 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_CVTA32P24_L;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 14 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_CVTP24A16X2_LL;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 15 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_CVTP24A16X2_HL;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 7 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_MOVAP24S_L;
+      if (Field_ae_r3_Slot_inst_get (insn) == 0 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 8 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_TRUNCA16P24S_L;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 5 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP24_I;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP24_IU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 12 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP24_X;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 15 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP24_XU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 6 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP16X2F_I;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 10 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP16X2F_IU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 13 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP16X2F_X;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 0 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_LP16X2F_XU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 7 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP24X2_I;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 11 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP24X2_IU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 14 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LP24X2_X;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_LP24X2_XU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 2 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24X2S_I;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 5 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24X2S_IU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 8 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24X2S_X;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 11 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24X2S_XU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 3 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP16F_L_I;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 6 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP16F_L_IU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP16F_L_X;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 12 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP16F_L_XU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 4 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24F_L_I;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 7 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24F_L_IU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 10 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24F_L_X;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 13 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_SP24F_L_XU;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 0 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_TRUNCP24A32X2;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 11 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_CVTA32P24_H;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 14 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_CVTP24A16X2_LH;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 15 &&
+	  Field_op2_Slot_inst_get (insn) == 11)
+	return OPCODE_AE_CVTP24A16X2_HH;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 7 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_MOVAP24S_H;
+      if (Field_ae_r3_Slot_inst_get (insn) == 1 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 8 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_TRUNCA16P24S_H;
+      if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 3 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SQ56S_I;
+      if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 4 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SQ56S_X;
+      if (Field_ae_r32_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 7 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_TRUNCA32Q48;
+      if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 3 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SQ32F_I;
+      if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 4 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SQ32F_X;
+      if (Field_ae_r32_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 7 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_NSAQ56S;
+      if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
+	  Field_op1_Slot_inst_get (insn) == 3 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SQ56S_IU;
+      if (Field_ae_r32_Slot_inst_get (insn) == 2 &&
+	  Field_op1_Slot_inst_get (insn) == 4 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SQ56S_XU;
+      if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
+	  Field_op1_Slot_inst_get (insn) == 3 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SQ32F_IU;
+      if (Field_ae_r32_Slot_inst_get (insn) == 3 &&
+	  Field_op1_Slot_inst_get (insn) == 4 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SQ32F_XU;
+      if (Field_ae_s_non_samt_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 5 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SLLIQ56;
+      if (Field_ae_s_non_samt_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 5 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SRLIQ56;
+      if (Field_ae_s_non_samt_Slot_inst_get (insn) == 2 &&
+	  Field_op1_Slot_inst_get (insn) == 5 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SRAIQ56;
+      if (Field_ae_s_non_samt_Slot_inst_get (insn) == 3 &&
+	  Field_op1_Slot_inst_get (insn) == 5 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SLLISQ56S;
+      if (Field_op1_Slot_inst_get (insn) == 0 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_SHA32;
+      if (Field_op1_Slot_inst_get (insn) == 0 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_VLDL32T;
+      if (Field_op1_Slot_inst_get (insn) == 1 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_SLLAQ56;
+      if (Field_op1_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_VLDL16T;
+      if (Field_op1_Slot_inst_get (insn) == 2 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_SRLAQ56;
+      if (Field_op1_Slot_inst_get (insn) == 2 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_LBK;
+      if (Field_op1_Slot_inst_get (insn) == 3 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_SRAAQ56;
+      if (Field_op1_Slot_inst_get (insn) == 3 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_VLEL32T;
+      if (Field_op1_Slot_inst_get (insn) == 4 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_SLLASQ56S;
+      if (Field_op1_Slot_inst_get (insn) == 4 &&
+	  Field_op2_Slot_inst_get (insn) == 10)
+	return OPCODE_AE_VLEL16T;
+      if (Field_op1_Slot_inst_get (insn) == 5 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_MOVTQ56;
+      if (Field_op1_Slot_inst_get (insn) == 6 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_MOVFQ56;
+      if (Field_r_Slot_inst_get (insn) == 0 &&
+	  Field_s_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 10 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_WUR_AE_OVERFLOW;
+      if (Field_r_Slot_inst_get (insn) == 0 &&
+	  Field_op2_Slot_inst_get (insn) == 15)
+	return OPCODE_AE_SBI;
+      if (Field_r_Slot_inst_get (insn) == 1 &&
+	  Field_s_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 10 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_WUR_AE_SAR;
+      if (Field_r_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 0 &&
+	  Field_op2_Slot_inst_get (insn) == 15)
+	return OPCODE_AE_DB;
+      if (Field_r_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 15)
+	return OPCODE_AE_SB;
+      if (Field_r_Slot_inst_get (insn) == 2 &&
+	  Field_s_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 10 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_WUR_AE_BITPTR;
+      if (Field_r_Slot_inst_get (insn) == 3 &&
+	  Field_s_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 10 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_WUR_AE_BITSUSED;
+      if (Field_r_Slot_inst_get (insn) == 4 &&
+	  Field_s_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 10 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_WUR_AE_TABLESIZE;
+      if (Field_r_Slot_inst_get (insn) == 5 &&
+	  Field_s_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 10 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_WUR_AE_FIRST_TS;
+      if (Field_r_Slot_inst_get (insn) == 6 &&
+	  Field_s_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 10 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_WUR_AE_NEXTOFFSET;
+      if (Field_r_Slot_inst_get (insn) == 7 &&
+	  Field_s_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 10 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_WUR_AE_SEARCHDONE;
+      if (Field_r_Slot_inst_get (insn) == 8 &&
+	  Field_s_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 10 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_VLDSHT;
+      if (Field_r_Slot_inst_get (insn) == 12 &&
+	  Field_op1_Slot_inst_get (insn) == 7 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_VLES16C;
+      if (Field_r_Slot_inst_get (insn) == 13 &&
+	  Field_op1_Slot_inst_get (insn) == 7 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_SBF;
+      if (Field_r_Slot_inst_get (insn) == 14 &&
+	  Field_op1_Slot_inst_get (insn) == 7 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_VLDL16C;
+      if (Field_s_Slot_inst_get (insn) == 0 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SLLSQ56;
+      if (Field_s_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 6 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_LB;
+      if (Field_s_Slot_inst_get (insn) == 1 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SRLSQ56;
+      if (Field_s_Slot_inst_get (insn) == 2 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SRASQ56;
+      if (Field_s_Slot_inst_get (insn) == 3 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_SLLSSQ56S;
+      if (Field_s_Slot_inst_get (insn) == 4 &&
+	  Field_t_Slot_inst_get (insn) == 1 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_AE_MOVQ56;
+      if (Field_s_Slot_inst_get (insn) == 8 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_RUR_AE_OVERFLOW;
+      if (Field_s_Slot_inst_get (insn) == 9 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_RUR_AE_SAR;
+      if (Field_s_Slot_inst_get (insn) == 10 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_RUR_AE_BITPTR;
+      if (Field_s_Slot_inst_get (insn) == 11 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_RUR_AE_BITSUSED;
+      if (Field_s_Slot_inst_get (insn) == 12 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_RUR_AE_TABLESIZE;
+      if (Field_s_Slot_inst_get (insn) == 13 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_RUR_AE_FIRST_TS;
+      if (Field_s_Slot_inst_get (insn) == 14 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_RUR_AE_NEXTOFFSET;
+      if (Field_s_Slot_inst_get (insn) == 15 &&
+	  Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op1_Slot_inst_get (insn) == 9 &&
+	  Field_op2_Slot_inst_get (insn) == 12)
+	return OPCODE_RUR_AE_SEARCHDONE;
+      if (Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_LBKI;
+      if (Field_t_Slot_inst_get (insn) == 0 &&
+	  Field_r_Slot_inst_get (insn) == 2 &&
+	  Field_op2_Slot_inst_get (insn) == 15)
+	return OPCODE_AE_DBI;
+      if (Field_t_Slot_inst_get (insn) == 2 &&
+	  Field_s_Slot_inst_get (insn) == 0 &&
+	  Field_op2_Slot_inst_get (insn) == 14)
+	return OPCODE_AE_LBI;
+    }
+  if (Field_op0_Slot_inst_get (insn) == 5)
+    {
+      if (Field_n_Slot_inst_get (insn) == 0)
+	return OPCODE_CALL0;
+      if (Field_n_Slot_inst_get (insn) == 1)
+	return OPCODE_CALL4;
+      if (Field_n_Slot_inst_get (insn) == 2)
+	return OPCODE_CALL8;
+      if (Field_n_Slot_inst_get (insn) == 3)
+	return OPCODE_CALL12;
+    }
+  if (Field_op0_Slot_inst_get (insn) == 6)
+    {
+      if (Field_n_Slot_inst_get (insn) == 0)
+	return OPCODE_J;
+      if (Field_n_Slot_inst_get (insn) == 1)
 	{
-	case 0:
-	  if (Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_LBKI;
-	  if (Field_r_Slot_inst_get (insn) == 2 &&
-	      Field_op2_Slot_inst_get (insn) == 15)
-	    return OPCODE_AE_DBI;
-	  break;
-	case 2:
-	  if (Field_s_Slot_inst_get (insn) == 0 &&
-	      Field_op2_Slot_inst_get (insn) == 14)
-	    return OPCODE_AE_LBI;
-	  break;
+	  if (Field_m_Slot_inst_get (insn) == 0)
+	    return OPCODE_BEQZ;
+	  if (Field_m_Slot_inst_get (insn) == 1)
+	    return OPCODE_BNEZ;
+	  if (Field_m_Slot_inst_get (insn) == 2)
+	    return OPCODE_BLTZ;
+	  if (Field_m_Slot_inst_get (insn) == 3)
+	    return OPCODE_BGEZ;
 	}
-      break;
-    case 5:
-      switch (Field_n_Slot_inst_get (insn))
+      if (Field_n_Slot_inst_get (insn) == 2)
 	{
-	case 0:
-	  return OPCODE_CALL0;
-	case 1:
-	  return OPCODE_CALL4;
-	case 2:
-	  return OPCODE_CALL8;
-	case 3:
-	  return OPCODE_CALL12;
+	  if (Field_m_Slot_inst_get (insn) == 0)
+	    return OPCODE_BEQI;
+	  if (Field_m_Slot_inst_get (insn) == 1)
+	    return OPCODE_BNEI;
+	  if (Field_m_Slot_inst_get (insn) == 2)
+	    return OPCODE_BLTI;
+	  if (Field_m_Slot_inst_get (insn) == 3)
+	    return OPCODE_BGEI;
 	}
-      break;
-    case 6:
-      switch (Field_n_Slot_inst_get (insn))
+      if (Field_n_Slot_inst_get (insn) == 3)
 	{
-	case 0:
-	  return OPCODE_J;
-	case 1:
-	  switch (Field_m_Slot_inst_get (insn))
-	    {
-	    case 0:
-	      return OPCODE_BEQZ;
-	    case 1:
-	      return OPCODE_BNEZ;
-	    case 2:
-	      return OPCODE_BLTZ;
-	    case 3:
-	      return OPCODE_BGEZ;
-	    }
-	  break;
-	case 2:
-	  switch (Field_m_Slot_inst_get (insn))
-	    {
-	    case 0:
-	      return OPCODE_BEQI;
-	    case 1:
-	      return OPCODE_BNEI;
-	    case 2:
-	      return OPCODE_BLTI;
-	    case 3:
-	      return OPCODE_BGEI;
-	    }
-	  break;
-	case 3:
-	  switch (Field_m_Slot_inst_get (insn))
+	  if (Field_m_Slot_inst_get (insn) == 0)
+	    return OPCODE_ENTRY;
+	  if (Field_m_Slot_inst_get (insn) == 1)
 	    {
-	    case 0:
-	      return OPCODE_ENTRY;
-	    case 1:
-	      switch (Field_r_Slot_inst_get (insn))
-		{
-		case 0:
-		  return OPCODE_BF;
-		case 1:
-		  return OPCODE_BT;
-		case 8:
-		  return OPCODE_LOOP;
-		case 9:
-		  return OPCODE_LOOPNEZ;
-		case 10:
-		  return OPCODE_LOOPGTZ;
-		}
-	      break;
-	    case 2:
-	      return OPCODE_BLTUI;
-	    case 3:
-	      return OPCODE_BGEUI;
+	      if (Field_r_Slot_inst_get (insn) == 0)
+		return OPCODE_BF;
+	      if (Field_r_Slot_inst_get (insn) == 1)
+		return OPCODE_BT;
+	      if (Field_r_Slot_inst_get (insn) == 8)
+		return OPCODE_LOOP;
+	      if (Field_r_Slot_inst_get (insn) == 9)
+		return OPCODE_LOOPNEZ;
+	      if (Field_r_Slot_inst_get (insn) == 10)
+		return OPCODE_LOOPGTZ;
 	    }
-	  break;
+	  if (Field_m_Slot_inst_get (insn) == 2)
+	    return OPCODE_BLTUI;
+	  if (Field_m_Slot_inst_get (insn) == 3)
+	    return OPCODE_BGEUI;
 	}
-      break;
-    case 7:
-      switch (Field_r_Slot_inst_get (insn))
-	{
-	case 0:
-	  return OPCODE_BNONE;
-	case 1:
-	  return OPCODE_BEQ;
-	case 2:
-	  return OPCODE_BLT;
-	case 3:
-	  return OPCODE_BLTU;
-	case 4:
-	  return OPCODE_BALL;
-	case 5:
-	  return OPCODE_BBC;
-	case 6:
-	case 7:
-	  return OPCODE_BBCI;
-	case 8:
-	  return OPCODE_BANY;
-	case 9:
-	  return OPCODE_BNE;
-	case 10:
-	  return OPCODE_BGE;
-	case 11:
-	  return OPCODE_BGEU;
-	case 12:
-	  return OPCODE_BNALL;
-	case 13:
-	  return OPCODE_BBS;
-	case 14:
-	case 15:
-	  return OPCODE_BBSI;
-	}
-      break;
+    }
+  if (Field_op0_Slot_inst_get (insn) == 7)
+    {
+      if (Field_r_Slot_inst_get (insn) == 0)
+	return OPCODE_BNONE;
+      if (Field_r_Slot_inst_get (insn) == 1)
+	return OPCODE_BEQ;
+      if (Field_r_Slot_inst_get (insn) == 2)
+	return OPCODE_BLT;
+      if (Field_r_Slot_inst_get (insn) == 3)
+	return OPCODE_BLTU;
+      if (Field_r_Slot_inst_get (insn) == 4)
+	return OPCODE_BALL;
+      if (Field_r_Slot_inst_get (insn) == 5)
+	return OPCODE_BBC;
+      if ((Field_r_Slot_inst_get (insn) == 6 ||
+	   Field_r_Slot_inst_get (insn) == 7))
+	return OPCODE_BBCI;
+      if (Field_r_Slot_inst_get (insn) == 8)
+	return OPCODE_BANY;
+      if (Field_r_Slot_inst_get (insn) == 9)
+	return OPCODE_BNE;
+      if (Field_r_Slot_inst_get (insn) == 10)
+	return OPCODE_BGE;
+      if (Field_r_Slot_inst_get (insn) == 11)
+	return OPCODE_BGEU;
+      if (Field_r_Slot_inst_get (insn) == 12)
+	return OPCODE_BNALL;
+      if (Field_r_Slot_inst_get (insn) == 13)
+	return OPCODE_BBS;
+      if ((Field_r_Slot_inst_get (insn) == 14 ||
+	   Field_r_Slot_inst_get (insn) == 15))
+	return OPCODE_BBSI;
     }
   return XTENSA_UNDEFINED;
 }
@@ -30824,50 +30653,37 @@  Slot_inst_decode (const xtensa_insnbuf insn)
 static int
 Slot_inst16b_decode (const xtensa_insnbuf insn)
 {
-  switch (Field_op0_Slot_inst16b_get (insn))
+  if (Field_op0_Slot_inst16b_get (insn) == 12)
     {
-    case 12:
-      switch (Field_i_Slot_inst16b_get (insn))
+      if (Field_i_Slot_inst16b_get (insn) == 0)
+	return OPCODE_MOVI_N;
+      if (Field_i_Slot_inst16b_get (insn) == 1)
 	{
-	case 0:
-	  return OPCODE_MOVI_N;
-	case 1:
-	  switch (Field_z_Slot_inst16b_get (insn))
-	    {
-	    case 0:
-	      return OPCODE_BEQZ_N;
-	    case 1:
-	      return OPCODE_BNEZ_N;
-	    }
-	  break;
+	  if (Field_z_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_BEQZ_N;
+	  if (Field_z_Slot_inst16b_get (insn) == 1)
+	    return OPCODE_BNEZ_N;
 	}
-      break;
-    case 13:
-      switch (Field_r_Slot_inst16b_get (insn))
+    }
+  if (Field_op0_Slot_inst16b_get (insn) == 13)
+    {
+      if (Field_r_Slot_inst16b_get (insn) == 0)
+	return OPCODE_MOV_N;
+      if (Field_r_Slot_inst16b_get (insn) == 15)
 	{
-	case 0:
-	  return OPCODE_MOV_N;
-	case 15:
-	  switch (Field_t_Slot_inst16b_get (insn))
-	    {
-	    case 0:
-	      return OPCODE_RET_N;
-	    case 1:
-	      return OPCODE_RETW_N;
-	    case 2:
-	      return OPCODE_BREAK_N;
-	    case 3:
-	      if (Field_s_Slot_inst16b_get (insn) == 0)
-		return OPCODE_NOP_N;
-	      break;
-	    case 6:
-	      if (Field_s_Slot_inst16b_get (insn) == 0)
-		return OPCODE_ILL_N;
-	      break;
-	    }
-	  break;
+	  if (Field_t_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_RET_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 1)
+	    return OPCODE_RETW_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 2)
+	    return OPCODE_BREAK_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 3 &&
+	      Field_s_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_NOP_N;
+	  if (Field_t_Slot_inst16b_get (insn) == 6 &&
+	      Field_s_Slot_inst16b_get (insn) == 0)
+	    return OPCODE_ILL_N;
 	}
-      break;
     }
   return XTENSA_UNDEFINED;
 }
@@ -30875,17 +30691,14 @@  Slot_inst16b_decode (const xtensa_insnbuf insn)
 static int
 Slot_inst16a_decode (const xtensa_insnbuf insn)
 {
-  switch (Field_op0_Slot_inst16a_get (insn))
-    {
-    case 8:
-      return OPCODE_L32I_N;
-    case 9:
-      return OPCODE_S32I_N;
-    case 10:
-      return OPCODE_ADD_N;
-    case 11:
-      return OPCODE_ADDI_N;
-    }
+  if (Field_op0_Slot_inst16a_get (insn) == 8)
+    return OPCODE_L32I_N;
+  if (Field_op0_Slot_inst16a_get (insn) == 9)
+    return OPCODE_S32I_N;
+  if (Field_op0_Slot_inst16a_get (insn) == 10)
+    return OPCODE_ADD_N;
+  if (Field_op0_Slot_inst16a_get (insn) == 11)
+    return OPCODE_ADDI_N;
   return XTENSA_UNDEFINED;
 }
 
@@ -30898,45 +30711,31 @@  Slot_ae_slot0_decode (const xtensa_insnbuf insn)
   if (Field_ftsf213ae_slot0_Slot_ae_slot0_get (insn) == 2 &&
       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
     return OPCODE_EXTUI;
-  switch (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn))
-    {
-    case 6:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_BGEZ;
-      break;
-    case 7:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_BLTZ;
-      break;
-    case 8:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_BEQZ;
-      break;
-    case 9:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_BNEZ;
-      break;
-    case 10:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_MOVI;
-      break;
-    }
-  switch (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn))
-    {
-    case 88:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_SRAI;
-      break;
-    case 96:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_SLLI;
-      break;
-    case 123:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
-	  Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0)
-	return OPCODE_AE_MOVTQ56;
-      break;
-    }
+  if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 6 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_BGEZ;
+  if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 7 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_BLTZ;
+  if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 8 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_BEQZ;
+  if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 9 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_BNEZ;
+  if (Field_ftsf214ae_slot0_Slot_ae_slot0_get (insn) == 10 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_MOVI;
+  if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 88 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_SRAI;
+  if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 96 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_SLLI;
+  if (Field_ftsf215ae_slot0_Slot_ae_slot0_get (insn) == 123 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+      Field_ftsf364ae_slot0_Slot_ae_slot0_get (insn) == 0)
+    return OPCODE_AE_MOVTQ56;
   if (Field_ftsf216ae_slot0_Slot_ae_slot0_get (insn) == 418 &&
       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
     return OPCODE_AE_CVTP24A16X2_HH;
@@ -31160,17 +30959,12 @@  Slot_ae_slot0_decode (const xtensa_insnbuf insn)
       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
       Field_s_Slot_ae_slot0_get (insn) == 0)
     return OPCODE_ALL8;
-  switch (Field_ftsf293_Slot_ae_slot0_get (insn))
-    {
-    case 0:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
-	return OPCODE_BBCI;
-      break;
-    case 1:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
-	return OPCODE_BBSI;
-      break;
-    }
+  if (Field_ftsf293_Slot_ae_slot0_get (insn) == 0 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+    return OPCODE_BBCI;
+  if (Field_ftsf293_Slot_ae_slot0_get (insn) == 1 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+    return OPCODE_BBSI;
   if (Field_ftsf294ae_slot0_Slot_ae_slot0_get (insn) == 1915 &&
       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
       Field_s_Slot_ae_slot0_get (insn) == 0)
@@ -31188,57 +30982,38 @@  Slot_ae_slot0_decode (const xtensa_insnbuf insn)
   if (Field_ftsf298ae_slot0_Slot_ae_slot0_get (insn) == 963 &&
       Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
     return OPCODE_AE_SQ56S_IU;
-  switch (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn))
-    {
-    case 964:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_AE_SLLIQ56;
-      break;
-    case 965:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_AE_SRAIQ56;
-      break;
-    case 966:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_AE_SRLIQ56;
-      break;
-    case 968:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_AE_SLLISQ56S;
-      break;
-    }
-  switch (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn))
-    {
-    case 3868:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_ABS;
-      break;
-    case 3869:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_NEG;
-      break;
-    case 3870:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_SRA;
-      break;
-    case 3871:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_SRL;
-      break;
-    }
-  switch (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn))
-    {
-    case 7752:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
-	  Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
-	return OPCODE_AE_MOVP48;
-      break;
-    case 7753:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
-	  Field_ftsf353_Slot_ae_slot0_get (insn) == 0)
-	return OPCODE_ANY4;
-      break;
-    }
+  if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 964 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_AE_SLLIQ56;
+  if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 965 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_AE_SRAIQ56;
+  if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 966 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_AE_SRLIQ56;
+  if (Field_ftsf299ae_slot0_Slot_ae_slot0_get (insn) == 968 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_AE_SLLISQ56S;
+  if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3868 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_ABS;
+  if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3869 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_NEG;
+  if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3870 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_SRA;
+  if (Field_ftsf300ae_slot0_Slot_ae_slot0_get (insn) == 3871 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_SRL;
+  if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7752 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+      Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
+    return OPCODE_AE_MOVP48;
+  if (Field_ftsf301ae_slot0_Slot_ae_slot0_get (insn) == 7753 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+      Field_ftsf353_Slot_ae_slot0_get (insn) == 0)
+    return OPCODE_ANY4;
   if (Field_ftsf302ae_slot0_Slot_ae_slot0_get (insn) == 31016 &&
       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
       Field_ftsf321_Slot_ae_slot0_get (insn) == 0)
@@ -31328,239 +31103,181 @@  Slot_ae_slot0_decode (const xtensa_insnbuf insn)
       Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
       Field_ftsf362ae_slot0_Slot_ae_slot0_get (insn) == 0)
     return OPCODE_AE_SQ32F_XU;
-  switch (Field_imm8_Slot_ae_slot0_get (insn))
-    {
-    case 178:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_ADD;
-      break;
-    case 179:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_ADDX8;
-      break;
-    case 180:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_ADDX2;
-      break;
-    case 181:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_AND;
-      break;
-    case 182:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_ANDB;
-      break;
-    case 183:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_ANDBC;
-      break;
-    case 184:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_ADDX4;
-      break;
-    case 185:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_CLAMPS;
-      break;
-    case 186:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_MAX;
-      break;
-    case 187:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_MIN;
-      break;
-    case 188:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_MAXU;
-      break;
-    case 189:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_MINU;
-      break;
-    case 190:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_MOVEQZ;
-      break;
-    case 191:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_MOVF;
-      break;
-    case 194:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_MOVGEZ;
-      break;
-    case 195:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_ORB;
-      break;
-    case 196:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_MOVLTZ;
-      break;
-    case 197:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_ORBC;
-      break;
-    case 198:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_SEXT;
-      break;
-    case 199:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_SRC;
-      break;
-    case 200:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_MOVNEZ;
-      break;
-    case 201:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_SRLI;
-      break;
-    case 202:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_SUB;
-      break;
-    case 203:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_SUBX4;
-      break;
-    case 204:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_SUBX2;
-      break;
-    case 205:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_SUBX8;
-      break;
-    case 206:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_XOR;
-      break;
-    case 207:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_XORB;
-      break;
-    case 208:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_MOVT;
-      break;
-    case 224:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
-	return OPCODE_OR;
-      break;
-    case 244:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
-	  Field_ae_r32_Slot_ae_slot0_get (insn) == 0)
-	return OPCODE_AE_SQ32F_X;
-      break;
-    }
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 178 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_ADD;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 179 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_ADDX8;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 180 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_ADDX2;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 181 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_AND;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 182 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_ANDB;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 183 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_ANDBC;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 184 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_ADDX4;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 185 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_CLAMPS;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 186 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_MAX;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 187 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_MIN;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 188 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_MAXU;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 189 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_MINU;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 190 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_MOVEQZ;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 191 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_MOVF;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 194 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_MOVGEZ;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 195 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_ORB;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 196 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_MOVLTZ;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 197 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_ORBC;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 198 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_SEXT;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 199 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_SRC;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 200 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_MOVNEZ;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 201 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_SRLI;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 202 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_SUB;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 203 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_SUBX4;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 204 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_SUBX2;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 205 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_SUBX8;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 206 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_XOR;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 207 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_XORB;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 208 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_MOVT;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 224 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1)
+    return OPCODE_OR;
+  if (Field_imm8_Slot_ae_slot0_get (insn) == 244 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 1 &&
+      Field_ae_r32_Slot_ae_slot0_get (insn) == 0)
+    return OPCODE_AE_SQ32F_X;
   if (Field_op0_s4_Slot_ae_slot0_get (insn) == 5)
     return OPCODE_L32R;
-  switch (Field_r_Slot_ae_slot0_get (insn))
-    {
-    case 0:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
-	return OPCODE_BNE;
-      break;
-    case 1:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
-	return OPCODE_BNONE;
-      break;
-    case 2:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
-	return OPCODE_L16SI;
-      break;
-    case 3:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
-	return OPCODE_L8UI;
-      break;
-    case 4:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
-	return OPCODE_ADDI;
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
-	return OPCODE_L16UI;
-      break;
-    case 5:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
-	return OPCODE_BALL;
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
-	return OPCODE_S16I;
-      break;
-    case 6:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
-	return OPCODE_BANY;
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
-	return OPCODE_S32I;
-      break;
-    case 7:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
-	return OPCODE_BBC;
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
-	return OPCODE_S8I;
-      break;
-    case 8:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
-	return OPCODE_ADDMI;
-      break;
-    case 9:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
-	return OPCODE_BBS;
-      break;
-    case 10:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
-	return OPCODE_BEQ;
-      break;
-    case 11:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
-	return OPCODE_BGEU;
-      break;
-    case 12:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
-	return OPCODE_BGE;
-      break;
-    case 13:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
-	return OPCODE_BLT;
-      break;
-    case 14:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
-	return OPCODE_BLTU;
-      break;
-    case 15:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
-	return OPCODE_BNALL;
-      break;
-    }
-  switch (Field_t_Slot_ae_slot0_get (insn))
-    {
-    case 0:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
-	return OPCODE_BEQI;
-      break;
-    case 1:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
-	return OPCODE_BGEI;
-      break;
-    case 2:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
-	return OPCODE_BGEUI;
-      break;
-    case 3:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
-	return OPCODE_BNEI;
-      break;
-    case 4:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
-	return OPCODE_BLTI;
-      break;
-    case 5:
-      if (Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
-	  Field_r_Slot_ae_slot0_get (insn) == 0)
-	return OPCODE_BF;
-      break;
-    }
+  if (Field_r_Slot_ae_slot0_get (insn) == 0 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+    return OPCODE_BNE;
+  if (Field_r_Slot_ae_slot0_get (insn) == 1 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+    return OPCODE_BNONE;
+  if (Field_r_Slot_ae_slot0_get (insn) == 2 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+    return OPCODE_L16SI;
+  if (Field_r_Slot_ae_slot0_get (insn) == 3 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+    return OPCODE_L8UI;
+  if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+    return OPCODE_ADDI;
+  if (Field_r_Slot_ae_slot0_get (insn) == 4 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+    return OPCODE_L16UI;
+  if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+    return OPCODE_BALL;
+  if (Field_r_Slot_ae_slot0_get (insn) == 5 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+    return OPCODE_S16I;
+  if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+    return OPCODE_BANY;
+  if (Field_r_Slot_ae_slot0_get (insn) == 6 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+    return OPCODE_S32I;
+  if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+    return OPCODE_BBC;
+  if (Field_r_Slot_ae_slot0_get (insn) == 7 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 4)
+    return OPCODE_S8I;
+  if (Field_r_Slot_ae_slot0_get (insn) == 8 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+    return OPCODE_ADDMI;
+  if (Field_r_Slot_ae_slot0_get (insn) == 9 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+    return OPCODE_BBS;
+  if (Field_r_Slot_ae_slot0_get (insn) == 10 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+    return OPCODE_BEQ;
+  if (Field_r_Slot_ae_slot0_get (insn) == 11 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+    return OPCODE_BGEU;
+  if (Field_r_Slot_ae_slot0_get (insn) == 12 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+    return OPCODE_BGE;
+  if (Field_r_Slot_ae_slot0_get (insn) == 13 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+    return OPCODE_BLT;
+  if (Field_r_Slot_ae_slot0_get (insn) == 14 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+    return OPCODE_BLTU;
+  if (Field_r_Slot_ae_slot0_get (insn) == 15 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 2)
+    return OPCODE_BNALL;
+  if (Field_t_Slot_ae_slot0_get (insn) == 0 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+    return OPCODE_BEQI;
+  if (Field_t_Slot_ae_slot0_get (insn) == 1 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+    return OPCODE_BGEI;
+  if (Field_t_Slot_ae_slot0_get (insn) == 2 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+    return OPCODE_BGEUI;
+  if (Field_t_Slot_ae_slot0_get (insn) == 3 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+    return OPCODE_BNEI;
+  if (Field_t_Slot_ae_slot0_get (insn) == 4 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 3)
+    return OPCODE_BLTI;
+  if (Field_t_Slot_ae_slot0_get (insn) == 5 &&
+      Field_op0_s4_Slot_ae_slot0_get (insn) == 3 &&
+      Field_r_Slot_ae_slot0_get (insn) == 0)
+    return OPCODE_BF;
   return XTENSA_UNDEFINED;
 }
 
@@ -31958,21 +31675,15 @@  Slot_ae_slot1_decode (const xtensa_insnbuf insn)
   if (Field_ftsf36ae_slot1_Slot_ae_slot1_get (insn) == 31 &&
       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
     return OPCODE_AE_SUBP24;
-  switch (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn))
-    {
-    case 8:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
-	return OPCODE_AE_SLLIP24;
-      break;
-    case 9:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
-	return OPCODE_AE_SRAIP24;
-      break;
-    case 10:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
-	return OPCODE_AE_SRLIP24;
-      break;
-    }
+  if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 8 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+    return OPCODE_AE_SLLIP24;
+  if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 9 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+    return OPCODE_AE_SRAIP24;
+  if (Field_ftsf37ae_slot1_Slot_ae_slot1_get (insn) == 10 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
+    return OPCODE_AE_SRLIP24;
   if (Field_ftsf38ae_slot1_Slot_ae_slot1_get (insn) == 176 &&
       Field_op0_s3_Slot_ae_slot1_get (insn) == 1)
     return OPCODE_AE_MULAFQ32SP16S_L;
@@ -32148,137 +31859,150 @@  Slot_ae_slot1_decode (const xtensa_insnbuf insn)
       Field_op0_s3_Slot_ae_slot1_get (insn) == 1 &&
       Field_ae_r20_Slot_ae_slot1_get (insn) == 0)
     return OPCODE_AE_ABSP24;
-  switch (Field_t_Slot_ae_slot1_get (insn))
-    {
-    case 0:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZAAFQ32SP16S_HH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZASFQ32SP16U_LH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSAQ32SP16S_LL;
-      break;
-    case 1:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZAAFQ32SP16S_LH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZASFQ32SP16U_LL;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSAQ32SP16U_HH;
-      break;
-    case 2:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZAAFQ32SP16S_LL;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZASQ32SP16S_HH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSAQ32SP16U_LH;
-      break;
-    case 3:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZAAFQ32SP16U_LL;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZASQ32SP16U_HH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSSFQ32SP16S_LH;
-      break;
-    case 4:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZAAFQ32SP16U_HH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZASQ32SP16S_LH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSAQ32SP16U_LL;
-      break;
-    case 5:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZAAQ32SP16S_HH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZASQ32SP16U_LH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSSFQ32SP16S_LL;
-      break;
-    case 6:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZAAQ32SP16S_LH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZASQ32SP16U_LL;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSSFQ32SP16U_HH;
-      break;
-    case 7:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZAAQ32SP16S_LL;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZSAFQ32SP16S_HH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSSFQ32SP16U_LH;
-      break;
-    case 8:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZAAFQ32SP16U_LH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZASQ32SP16S_LL;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSSFQ32SP16S_HH;
-      break;
-    case 9:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZAAQ32SP16U_HH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZSAFQ32SP16S_LH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSSFQ32SP16U_LL;
-      break;
-    case 10:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZAAQ32SP16U_LH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZSAFQ32SP16S_LL;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSSQ32SP16S_HH;
-      break;
-    case 11:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZASFQ32SP16S_HH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZSAFQ32SP16U_LH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSSQ32SP16S_LL;
-      break;
-    case 12:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZAAQ32SP16U_LL;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZSAFQ32SP16U_HH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSSQ32SP16S_LH;
-      break;
-    case 13:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZASFQ32SP16S_LH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZSAFQ32SP16U_LL;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSSQ32SP16U_HH;
-      break;
-    case 14:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZASFQ32SP16S_LL;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZSAQ32SP16S_HH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSSQ32SP16U_LH;
-      break;
-    case 15:
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
-	return OPCODE_AE_MULZASFQ32SP16U_HH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
-	return OPCODE_AE_MULZSAQ32SP16S_LH;
-      if (Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
-	return OPCODE_AE_MULZSSQ32SP16U_LL;
-      break;
-    }
+  if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZAAFQ32SP16S_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZASFQ32SP16U_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 0 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSAQ32SP16S_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZAAFQ32SP16S_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZASFQ32SP16U_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 1 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSAQ32SP16U_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZAAFQ32SP16S_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZASQ32SP16S_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 2 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSAQ32SP16U_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZAAFQ32SP16U_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZASQ32SP16U_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 3 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSSFQ32SP16S_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZAAFQ32SP16U_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZASQ32SP16S_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 4 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSAQ32SP16U_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZAAQ32SP16S_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZASQ32SP16U_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 5 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSSFQ32SP16S_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZAAQ32SP16S_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZASQ32SP16U_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 6 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSSFQ32SP16U_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZAAQ32SP16S_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZSAFQ32SP16S_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 7 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSSFQ32SP16U_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZAAFQ32SP16U_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZASQ32SP16S_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 8 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSSFQ32SP16S_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZAAQ32SP16U_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZSAFQ32SP16S_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 9 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSSFQ32SP16U_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZAAQ32SP16U_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZSAFQ32SP16S_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 10 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSSQ32SP16S_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZASFQ32SP16S_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZSAFQ32SP16U_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 11 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSSQ32SP16S_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZAAQ32SP16U_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZSAFQ32SP16U_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 12 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSSQ32SP16S_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZASFQ32SP16S_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZSAFQ32SP16U_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 13 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSSQ32SP16U_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZASFQ32SP16S_LL;
+  if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZSAQ32SP16S_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 14 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSSQ32SP16U_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 2)
+    return OPCODE_AE_MULZASFQ32SP16U_HH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 3)
+    return OPCODE_AE_MULZSAQ32SP16S_LH;
+  if (Field_t_Slot_ae_slot1_get (insn) == 15 &&
+      Field_op0_s3_Slot_ae_slot1_get (insn) == 4)
+    return OPCODE_AE_MULZSSQ32SP16U_LL;
   return XTENSA_UNDEFINED;
 }
 
@@ -32418,6 +32142,8 @@  Slot_inst_get_field_fns[] = {
   Field_ae_r20_Slot_inst_get,
   Field_ae_r10_Slot_inst_get,
   Field_ae_s20_Slot_inst_get,
+  Field_ae_fld_ohba_Slot_inst_get,
+  Field_ae_fld_ohba2_Slot_inst_get,
   0,
   Field_ftsf12_Slot_inst_get,
   Field_ftsf13_Slot_inst_get,
@@ -32809,6 +32535,8 @@  Slot_inst_set_field_fns[] = {
   Field_ae_r20_Slot_inst_set,
   Field_ae_r10_Slot_inst_set,
   Field_ae_s20_Slot_inst_set,
+  Field_ae_fld_ohba_Slot_inst_set,
+  Field_ae_fld_ohba2_Slot_inst_set,
   0,
   Field_ftsf12_Slot_inst_set,
   Field_ftsf13_Slot_inst_set,
@@ -33525,6 +33253,8 @@  Slot_inst16a_get_field_fns[] = {
   0,
   0,
   0,
+  0,
+  0,
   Implicit_Field_ar0_get,
   Implicit_Field_ar4_get,
   Implicit_Field_ar8_get,
@@ -33916,6 +33646,8 @@  Slot_inst16a_set_field_fns[] = {
   0,
   0,
   0,
+  0,
+  0,
   Implicit_Field_set,
   Implicit_Field_set,
   Implicit_Field_set,
@@ -34307,6 +34039,8 @@  Slot_inst16b_get_field_fns[] = {
   0,
   0,
   0,
+  0,
+  0,
   Implicit_Field_ar0_get,
   Implicit_Field_ar4_get,
   Implicit_Field_ar8_get,
@@ -34698,6 +34432,8 @@  Slot_inst16b_set_field_fns[] = {
   0,
   0,
   0,
+  0,
+  0,
   Implicit_Field_set,
   Implicit_Field_set,
   Implicit_Field_set,
@@ -34764,6 +34500,8 @@  Slot_ae_slot1_get_field_fns[] = {
   Field_ae_r20_Slot_ae_slot1_get,
   Field_ae_r10_Slot_ae_slot1_get,
   Field_ae_s20_Slot_ae_slot1_get,
+  0,
+  0,
   Field_op0_s3_Slot_ae_slot1_get,
   Field_ftsf12_Slot_ae_slot1_get,
   Field_ftsf13_Slot_ae_slot1_get,
@@ -35155,6 +34893,8 @@  Slot_ae_slot1_set_field_fns[] = {
   Field_ae_r20_Slot_ae_slot1_set,
   Field_ae_r10_Slot_ae_slot1_set,
   Field_ae_s20_Slot_ae_slot1_set,
+  0,
+  0,
   Field_op0_s3_Slot_ae_slot1_set,
   Field_ftsf12_Slot_ae_slot1_set,
   Field_ftsf13_Slot_ae_slot1_set,
@@ -35745,6 +35485,8 @@  Slot_ae_slot0_get_field_fns[] = {
   0,
   0,
   0,
+  0,
+  0,
   Field_op0_s4_Slot_ae_slot0_get,
   Field_ftsf212ae_slot0_Slot_ae_slot0_get,
   Field_ftsf213ae_slot0_Slot_ae_slot0_get,
@@ -36136,6 +35878,8 @@  Slot_ae_slot0_set_field_fns[] = {
   0,
   0,
   0,
+  0,
+  0,
   Field_op0_s4_Slot_ae_slot0_set,
   Field_ftsf212ae_slot0_Slot_ae_slot0_set,
   Field_ftsf213ae_slot0_Slot_ae_slot0_set,
@@ -36356,7 +36100,247 @@  format_decoder (const xtensa_insnbuf insn)
   return -1;
 }
 
-static int length_table[16] = {
+static int length_table[256] = {
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  3,
+  2,
+  2,
+  2,
+  2,
+  2,
+  2,
+  -1,
+  8,
   3,
   3,
   3,
@@ -36378,8 +36362,8 @@  static int length_table[16] = {
 static int
 length_decoder (const unsigned char *insn)
 {
-  int op0 = insn[0] & 0xf;
-  return length_table[op0];
+  int l = insn[0];
+  return length_table[l];
 }
 
 
@@ -36390,8 +36374,8 @@  xtensa_isa_internal xtensa_modules = {
   8 /* insn_size */, 0,
   4, formats, format_decoder, length_decoder,
   5, slots,
-  387 /* num_fields */,
-  445, operands,
+  389 /* num_fields */,
+  454, operands,
   588, iclasses,
   656, opcodes, 0,
   8, regfiles,