From patchwork Tue Oct 22 16:21:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= X-Patchwork-Id: 11204911 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 44CB51747 for ; Tue, 22 Oct 2019 17:00:44 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 109B621929 for ; Tue, 22 Oct 2019 17:00:44 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="LkJIrAsL" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 109B621929 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:36558 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iMxWD-0001K9-BV for patchwork-qemu-devel@patchwork.kernel.org; Tue, 22 Oct 2019 13:00:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39006) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iMwy2-00010o-0C for qemu-devel@nongnu.org; Tue, 22 Oct 2019 12:25:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iMwy0-0008AL-CU for qemu-devel@nongnu.org; Tue, 22 Oct 2019 12:25:05 -0400 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:26771 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iMwy0-0008A3-9B for qemu-devel@nongnu.org; Tue, 22 Oct 2019 12:25:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1571761503; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OWXPuZe/N59AA+45n08Y6AMqBs3KXImECglmyR34SnU=; b=LkJIrAsLxhH0sIKI7pjFMABVoma/lFG5ueQnBWE1zgaQNSbuttWI8nhvz+s7jkx2YaeB5O iri8kBGddsdjGGFu1yO5etA+AxZBtnyP3c4U2hjVs2XNtcFU6BY3/jXH8Qwlzqd6wVeMHB h8NhivgKxW+IUXKJ+/KRyiLuhImUAPo= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-174-RHzneXQmMjqukV0TqwtQ0w-1; Tue, 22 Oct 2019 12:24:59 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 5E31680183D; Tue, 22 Oct 2019 16:24:57 +0000 (UTC) Received: from localhost (ovpn-112-21.ams2.redhat.com [10.36.112.21]) by smtp.corp.redhat.com (Postfix) with ESMTP id 6B0C45C219; Tue, 22 Oct 2019 16:24:54 +0000 (UTC) From: =?utf-8?q?Marc-Andr=C3=A9_Lureau?= To: qemu-devel@nongnu.org Subject: [PATCH v2 26/28] omap-gpio: remove PROP_PTR Date: Tue, 22 Oct 2019 18:21:35 +0200 Message-Id: <20191022162137.27161-27-marcandre.lureau@redhat.com> In-Reply-To: <20191022162137.27161-1-marcandre.lureau@redhat.com> References: <20191022162137.27161-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-MC-Unique: RHzneXQmMjqukV0TqwtQ0w-1 X-Mimecast-Spam-Score: 0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Corey Minyard , Peter Maydell , "Michael S. Tsirkin" , Jason Wang , Mark Cave-Ayland , KONRAD Frederic , "Edgar E. Iglesias" , Aleksandar Rikalo , Magnus Damm , =?utf-8?q?Herv=C3=A9_Poussineau?= , =?utf-8?q?Marc-An?= =?utf-8?q?dr=C3=A9_Lureau?= , Artyom Tarasenko , Eduardo Habkost , Fabien Chouteau , qemu-arm@nongnu.org, Richard Henderson , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , qemu-ppc@nongnu.org, Aleksandar Markovic , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Since clocks are not QOM objects, replace PROP_PTR of clocks with setters methods. Move/adapt the existing TODO comment about a clock framework. Reviewed-by: Peter Maydell Signed-off-by: Marc-André Lureau --- hw/arm/omap1.c | 2 +- hw/arm/omap2.c | 13 +++++++------ hw/gpio/omap_gpio.c | 42 +++++++++++++++--------------------------- include/hw/arm/omap.h | 33 +++++++++++++++++++++++++++++---- 4 files changed, 52 insertions(+), 38 deletions(-) diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index fe55c44c7e..f13d46afaa 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -4014,7 +4014,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, s->gpio = qdev_create(NULL, "omap-gpio"); qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); - qdev_prop_set_ptr(s->gpio, "clk", omap_findclk(s, "arm_gpio_ck")); + omap_gpio_set_clk(OMAP1_GPIO(s->gpio), omap_findclk(s, "arm_gpio_ck")); qdev_init_nofail(s->gpio); sysbus_connect_irq(SYS_BUS_DEVICE(s->gpio), 0, qdev_get_gpio_in(s->ih[0], OMAP_INT_GPIO_BANK1)); diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index 046fb6ffb5..d5c20f6486 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -2452,13 +2452,14 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, s->gpio = qdev_create(NULL, "omap2-gpio"); qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model); - qdev_prop_set_ptr(s->gpio, "iclk", omap_findclk(s, "gpio_iclk")); - qdev_prop_set_ptr(s->gpio, "fclk0", omap_findclk(s, "gpio1_dbclk")); - qdev_prop_set_ptr(s->gpio, "fclk1", omap_findclk(s, "gpio2_dbclk")); - qdev_prop_set_ptr(s->gpio, "fclk2", omap_findclk(s, "gpio3_dbclk")); - qdev_prop_set_ptr(s->gpio, "fclk3", omap_findclk(s, "gpio4_dbclk")); + omap2_gpio_set_iclk(OMAP2_GPIO(s->gpio), omap_findclk(s, "gpio_iclk")); + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 0, omap_findclk(s, "gpio1_dbclk")); + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 1, omap_findclk(s, "gpio2_dbclk")); + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 2, omap_findclk(s, "gpio3_dbclk")); + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 3, omap_findclk(s, "gpio4_dbclk")); if (s->mpu_model == omap2430) { - qdev_prop_set_ptr(s->gpio, "fclk4", omap_findclk(s, "gpio5_dbclk")); + omap2_gpio_set_fclk(OMAP2_GPIO(s->gpio), 4, + omap_findclk(s, "gpio5_dbclk")); } qdev_init_nofail(s->gpio); busdev = SYS_BUS_DEVICE(s->gpio); diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c index 41e1aa798c..85c16897ae 100644 --- a/hw/gpio/omap_gpio.c +++ b/hw/gpio/omap_gpio.c @@ -40,10 +40,6 @@ struct omap_gpio_s { uint16_t pins; }; -#define TYPE_OMAP1_GPIO "omap-gpio" -#define OMAP1_GPIO(obj) \ - OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO) - struct omap_gpif_s { SysBusDevice parent_obj; @@ -212,10 +208,6 @@ struct omap2_gpio_s { uint8_t delay; }; -#define TYPE_OMAP2_GPIO "omap2-gpio" -#define OMAP2_GPIO(obj) \ - OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO) - struct omap2_gpif_s { SysBusDevice parent_obj; @@ -747,21 +739,13 @@ static void omap2_gpio_realize(DeviceState *dev, Error **errp) } } -/* Using qdev pointer properties for the clocks is not ideal. - * qdev should support a generic means of defining a 'port' with - * an arbitrary interface for connecting two devices. Then we - * could reframe the omap clock API in terms of clock ports, - * and get some type safety. For now the best qdev provides is - * passing an arbitrary pointer. - * (It's not possible to pass in the string which is the clock - * name, because this device does not have the necessary information - * (ie the struct omap_mpu_state_s*) to do the clockname to pointer - * translation.) - */ +void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk) +{ + gpio->clk = clk; +} static Property omap_gpio_properties[] = { DEFINE_PROP_INT32("mpu_model", struct omap_gpif_s, mpu_model, 0), - DEFINE_PROP_PTR("clk", struct omap_gpif_s, clk), DEFINE_PROP_END_OF_LIST(), }; @@ -784,15 +768,19 @@ static const TypeInfo omap_gpio_info = { .class_init = omap_gpio_class_init, }; +void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk) +{ + gpio->iclk = clk; +} + +void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk) +{ + assert(i <= 5); + gpio->fclk[i] = clk; +} + static Property omap2_gpio_properties[] = { DEFINE_PROP_INT32("mpu_model", struct omap2_gpif_s, mpu_model, 0), - DEFINE_PROP_PTR("iclk", struct omap2_gpif_s, iclk), - DEFINE_PROP_PTR("fclk0", struct omap2_gpif_s, fclk[0]), - DEFINE_PROP_PTR("fclk1", struct omap2_gpif_s, fclk[1]), - DEFINE_PROP_PTR("fclk2", struct omap2_gpif_s, fclk[2]), - DEFINE_PROP_PTR("fclk3", struct omap2_gpif_s, fclk[3]), - DEFINE_PROP_PTR("fclk4", struct omap2_gpif_s, fclk[4]), - DEFINE_PROP_PTR("fclk5", struct omap2_gpif_s, fclk[5]), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h index 19fc442c45..acc4ef3d9f 100644 --- a/include/hw/arm/omap.h +++ b/include/hw/arm/omap.h @@ -77,6 +77,16 @@ typedef struct omap_intr_handler_s omap_intr_handler; /* * TODO: Ideally we should have a clock framework that * let us wire these clocks up with QOM properties or links. + * + * qdev should support a generic means of defining a 'port' with + * an arbitrary interface for connecting two devices. Then we + * could reframe the omap clock API in terms of clock ports, + * and get some type safety. For now the best qdev provides is + * passing an arbitrary pointer. + * (It's not possible to pass in the string which is the clock + * name, because this device does not have the necessary information + * (ie the struct omap_mpu_state_s*) to do the clockname to pointer + * translation.) */ void omap_intc_set_iclk(omap_intr_handler *intc, omap_clk clk); void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk); @@ -87,13 +97,28 @@ void omap_intc_set_fclk(omap_intr_handler *intc, omap_clk clk); typedef struct OMAPI2CState OMAPI2CState; -/* - * TODO: Ideally we should have a clock framework that - * let us wire these clocks up with QOM properties or links. - */ +/* TODO: clock framework (see above) */ void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk); void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk); +/* omap_gpio.c */ +#define TYPE_OMAP1_GPIO "omap-gpio" +#define OMAP1_GPIO(obj) \ + OBJECT_CHECK(struct omap_gpif_s, (obj), TYPE_OMAP1_GPIO) + +#define TYPE_OMAP2_GPIO "omap2-gpio" +#define OMAP2_GPIO(obj) \ + OBJECT_CHECK(struct omap2_gpif_s, (obj), TYPE_OMAP2_GPIO) + +typedef struct omap_gpif_s omap_gpif; +typedef struct omap2_gpif_s omap2_gpif; + +/* TODO: clock framework (see above) */ +void omap_gpio_set_clk(omap_gpif *gpio, omap_clk clk); + +void omap2_gpio_set_iclk(omap2_gpif *gpio, omap_clk clk); +void omap2_gpio_set_fclk(omap2_gpif *gpio, uint8_t i, omap_clk clk); + /* OMAP2 l4 Interconnect */ struct omap_l4_s; struct omap_l4_region_s {