From patchwork Tue Dec 17 04:42:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296585 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id D548214B7 for ; Tue, 17 Dec 2019 04:58:32 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AB40020733 for ; Tue, 17 Dec 2019 04:58:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="cM2m+FkK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org AB40020733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35286 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4wJ-0003LU-Bp for patchwork-qemu-devel@patchwork.kernel.org; Mon, 16 Dec 2019 23:58:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33495) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4i0-00088Z-FH for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4hz-0005QE-AD for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:43:44 -0500 Received: from ozlabs.org ([203.11.71.1]:51113) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4hy-0005Ij-Uw; Mon, 16 Dec 2019 23:43:43 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWQ1vdjz9sSf; Tue, 17 Dec 2019 15:43:29 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557810; bh=YLyu+TvN7QrUe5KSxjn+8t7hVOL9DOYECayzY0UoxQ0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cM2m+FkKSmhv6a6eeLH7PuMRwGE16qJRzFbL486Gr6EKFK/kSj73KfyHvBQJJoWmU 9+PE7q7Fql3zqyGZO5VLtJCb91/R/8naMGS/I1D0AgMacD/NqQtWQ9tlPKlWXGTcK6 ZiVjs80xns3Wnan2xL+lDbCglW8OHy2WbJ4aflEg= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 18/88] ppc/xive: Introduce helpers for the NVT id Date: Tue, 17 Dec 2019 15:42:12 +1100 Message-Id: <20191217044322.351838-19-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater Each vCPU in the system is identified with an NVT identifier which is pushed in the OS CAM line (QW1W2) of the HW thread interrupt context register when the vCPU is dispatched on a HW thread. This identifier is used by the presenter subengine to find a matching target to notify of an event. It is also used to fetch the associate NVT structure which may contain pending interrupts that need a resend. Add a couple of helpers for the NVT ids. The NVT space is 19 bits wide, giving a maximum of 512K per chip. Signed-off-by: Cédric Le Goater Message-Id: <20191115162436.30548-3-clg@kaod.org> Signed-off-by: David Gibson --- include/hw/ppc/xive.h | 5 ----- include/hw/ppc/xive_regs.h | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 8fd439ec9b..fa7adf87fe 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -418,11 +418,6 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); void xive_tctx_reset(XiveTCTX *tctx); void xive_tctx_destroy(XiveTCTX *tctx); -static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) -{ - return (nvt_blk << 19) | nvt_idx; -} - /* * KVM XIVE device helpers */ diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h index 530f232b04..1a5622f8de 100644 --- a/include/hw/ppc/xive_regs.h +++ b/include/hw/ppc/xive_regs.h @@ -272,4 +272,25 @@ typedef struct XiveNVT { #define xive_nvt_is_valid(nvt) (be32_to_cpu((nvt)->w0) & NVT_W0_VALID) +/* + * The VP number space in a block is defined by the END_W6_NVT_INDEX + * field of the XIVE END + */ +#define XIVE_NVT_SHIFT 19 + +static inline uint32_t xive_nvt_cam_line(uint8_t nvt_blk, uint32_t nvt_idx) +{ + return (nvt_blk << XIVE_NVT_SHIFT) | nvt_idx; +} + +static inline uint32_t xive_nvt_idx(uint32_t cam_line) +{ + return cam_line & ((1 << XIVE_NVT_SHIFT) - 1); +} + +static inline uint32_t xive_nvt_blk(uint32_t cam_line) +{ + return (cam_line >> XIVE_NVT_SHIFT) & 0xf; +} + #endif /* PPC_XIVE_REGS_H */