From patchwork Tue Dec 17 04:42:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296653 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 781E46C1 for ; Tue, 17 Dec 2019 05:20:10 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3AD2B2072D for ; Tue, 17 Dec 2019 05:20:10 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="EnwRO3qQ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3AD2B2072D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5HE-0000mt-Qu for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:20:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34008) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4ia-0000LJ-8r for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4iZ-0005vp-31 for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:44:20 -0500 Received: from ozlabs.org ([203.11.71.1]:49689) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4iY-0005aN-NY; Mon, 16 Dec 2019 23:44:19 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWV4SJlz9sSs; Tue, 17 Dec 2019 15:43:32 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557814; bh=DSSa+2JspH3S+BZddb51VgY8bu9p/D1QJFBo+rul0po=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EnwRO3qQoy/YU3F+usm43cfCb9ZV920WTksOoJBDGErVlEEcYnjPUL4bRPCyy4QUo lwpYDw21utzN6K5FdrijBG8MY/NkwQjQjBFmQs8PDuh6ok74LhwIbCm6DkQK6piiqv Uy+P4q8GKXJaSPQ78+KXMUlmSKB6Hax0LnRwYtbk= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 32/88] ppc/pnv: Introduce a pnv_xive_is_cpu_enabled() helper Date: Tue, 17 Dec 2019 15:42:26 +1100 Message-Id: <20191217044322.351838-33-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater and use this helper to exclude CPUs which are not enabled in the XIVE controller. Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-7-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 19 +++++++++++++++++++ include/hw/ppc/pnv.h | 5 +++++ 2 files changed, 24 insertions(+) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 9798bd9e72..ec8349ee4a 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -372,6 +372,21 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx, return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas); } +/* + * One bit per thread id. The first register PC_THREAD_EN_REG0 covers + * the first cores 0-15 (normal) of the chip or 0-7 (fused). The + * second register covers cores 16-23 (normal) or 8-11 (fused). + */ +static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu) +{ + int pir = ppc_cpu_pir(cpu); + uint32_t fc = PNV9_PIR2FUSEDCORE(pir); + uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1; + uint32_t bit = pir & 0x3f; + + return xive->regs[reg >> 3] & PPC_BIT(bit); +} + static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, @@ -391,6 +406,10 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, XiveTCTX *tctx; int ring; + if (!pnv_xive_is_cpu_enabled(xive, cpu)) { + continue; + } + tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); /* diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 03cb429f21..12b0169a40 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -99,6 +99,11 @@ typedef struct Pnv9Chip { PnvQuad *quads; } Pnv9Chip; +/* + * A SMT8 fused core is a pair of SMT4 cores. + */ +#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) + typedef struct PnvChipClass { /*< private >*/ SysBusDeviceClass parent_class;