From patchwork Tue Dec 17 04:42:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296667 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0090D6C1 for ; Tue, 17 Dec 2019 05:23:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB7EC2072B for ; Tue, 17 Dec 2019 05:23:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="m6i7wqdO" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CB7EC2072B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5KO-0005U8-Kq for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:23:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34756) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4jK-0001c4-QC for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4jJ-00070z-EE for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:45:06 -0500 Received: from bilbo.ozlabs.org ([203.11.71.1]:45849 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4jJ-0006Qf-2I; Mon, 16 Dec 2019 23:45:05 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWZ6LY5z9sTB; Tue, 17 Dec 2019 15:43:35 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557818; bh=X9t78hdpVHh941VAJHuK29vpxbHkZ/R4dADMSE3VC54=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=m6i7wqdO4d4YBwzEhzwovnqyySwkfV6NhXCK81IqPjFW1L1mUmxKh1b8JHuJ/cz5R U91fUiLu+IoB0LEOEL95sIlVeIYS1ldTS0aIPIqgmii8wnuvwNjUKEgREckfj5dcn+ xkAS1eMJINs1qgya4oZs0pGxSGr1l4v2UQX8RnSI= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 43/88] ppc/pnv: Clarify how the TIMA is accessed on a multichip system Date: Tue, 17 Dec 2019 15:42:37 +1100 Message-Id: <20191217044322.351838-44-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Cédric Le Goater The TIMA region gives access to the thread interrupt context registers of a CPU. It is mapped at the same address on all chips and can be accessed by any CPU of the system. To identify the chip from which the access is being done, the PowerBUS uses a 'chip' field in the load/store messages. QEMU does not model these messages, instead, we extract the chip id from the CPU PIR and do a lookup at the machine level to fetch the targeted interrupt controller. Introduce pnv_get_chip() and pnv_xive_tm_get_xive() helpers to clarify this process in pnv_xive_get_tctx(). The latter will be removed in the subsequent patches but the same principle will be kept. Signed-off-by: Cédric Le Goater Message-Id: <20191125065820.927-14-clg@kaod.org> Signed-off-by: David Gibson --- hw/intc/pnv_xive.c | 40 +++++++++++++++++++++++----------------- hw/ppc/pnv.c | 14 ++++++++++++++ include/hw/ppc/pnv.h | 3 +++ 3 files changed, 40 insertions(+), 17 deletions(-) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 95e9de312c..db9d9c11a8 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -439,31 +439,37 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, return count; } +/* + * The TIMA MMIO space is shared among the chips and to identify the + * chip from which the access is being done, we extract the chip id + * from the PIR. + */ +static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) +{ + int pir = ppc_cpu_pir(cpu); + PnvChip *chip; + PnvXive *xive; + + chip = pnv_get_chip(PNV9_PIR2CHIP(pir)); + assert(chip); + xive = &PNV9_CHIP(chip)->xive; + + if (!pnv_xive_is_cpu_enabled(xive, cpu)) { + xive_error(xive, "IC: CPU %x is not enabled", pir); + } + return xive; +} + static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); - XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); - PnvXive *xive = NULL; - CPUPPCState *env = &cpu->env; - int pir = env->spr_cb[SPR_PIR].default_value; + PnvXive *xive = pnv_xive_tm_get_xive(cpu); - /* - * Perform an extra check on the HW thread enablement. - * - * The TIMA is shared among the chips and to identify the chip - * from which the access is being done, we extract the chip id - * from the PIR. - */ - xive = pnv_xive_get_ic((pir >> 8) & 0xf); if (!xive) { return NULL; } - if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) { - xive_error(PNV_XIVE(xrtr), "IC: CPU %x is not enabled", pir); - } - - return tctx; + return XIVE_TCTX(pnv_cpu_state(cpu)->intc); } /* diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 5b8b07f6ae..fa656858b2 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1472,6 +1472,20 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, return total_count; } +PnvChip *pnv_get_chip(uint32_t chip_id) +{ + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); + int i; + + for (i = 0; i < pnv->num_chips; i++) { + PnvChip *chip = pnv->chips[i]; + if (chip->chip_id == chip_id) { + return chip; + } + } + return NULL; +} + static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index a58cfea3f2..3a7bc3c57e 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -103,6 +103,7 @@ typedef struct Pnv9Chip { * A SMT8 fused core is a pair of SMT4 cores. */ #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) +#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) typedef struct PnvChipClass { /*< private >*/ @@ -197,6 +198,8 @@ static inline bool pnv_is_power9(PnvMachineState *pnv) return pnv_chip_is_power9(pnv->chips[0]); } +PnvChip *pnv_get_chip(uint32_t chip_id); + #define PNV_FDT_ADDR 0x01000000 #define PNV_TIMEBASE_FREQ 512000000ULL