From patchwork Tue Dec 17 04:43:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: David Gibson X-Patchwork-Id: 11296717 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C5815138C for ; Tue, 17 Dec 2019 05:38:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9B92520733 for ; Tue, 17 Dec 2019 05:38:41 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=gibson.dropbear.id.au header.i=@gibson.dropbear.id.au header.b="LUl5y+Us" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9B92520733 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=gibson.dropbear.id.au Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih5ZA-0002cK-LF for patchwork-qemu-devel@patchwork.kernel.org; Tue, 17 Dec 2019 00:38:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35865) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ih4kX-0002uQ-EZ for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ih4kW-0000EV-4t for qemu-devel@nongnu.org; Mon, 16 Dec 2019 23:46:21 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:48539 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ih4kV-0000AG-Qc; Mon, 16 Dec 2019 23:46:20 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 47cQWl3KnJz9sRp; Tue, 17 Dec 2019 15:43:43 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1576557827; bh=np9HcZx1KFwcdtSNbC/6aMTF85SHkdWiNq+VeNbUHxQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LUl5y+UsDMwQYqxEFOcV16ZS9koA9Tz8+pPDbG85i5MtOHrsBJnC+aISTYUzTNysj +/zOWpd4gW6DbNwyokYI6lUTLoXCoQrbWb9ImjDG9Xm/XVGrv8lJvHsq6vrImedbmR TA59GeT4QAePL0kt87Rdyt7z7sLGnitBROwY3gxw= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 76/88] ppc/pnv: Introduce PnvPsiClass::compat Date: Tue, 17 Dec 2019 15:43:10 +1100 Message-Id: <20191217044322.351838-77-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191217044322.351838-1-david@gibson.dropbear.id.au> References: <20191217044322.351838-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Greg Kurz The Processor Service Interface (PSI) model has a chip_type class level attribute, which is used to generate the content of the "compatible" DT property according to the CPU type. Since the PSI model already has specialized classes for each supported CPU type, it seems cleaner to achieve this with QOM. Provide the content of the "compatible" property with a new class level attribute. Signed-off-by: Greg Kurz Message-Id: <157623837974.360005.14706607446188964477.stgit@bahia.lan> Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/ppc/pnv_psi.c | 25 +++++++++++-------------- include/hw/ppc/pnv_psi.h | 2 ++ 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 572924388b..98a82b25e0 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -536,10 +536,6 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) qemu_register_reset(pnv_psi_reset, dev); } -static const char compat_p8[] = "ibm,power8-psihb-x\0ibm,psihb-x"; -static const char compat_p9[] = "ibm,power9-psihb-x\0ibm,psihb-x"; -static const char compat_p10[] = "ibm,power10-psihb-x\0ibm,psihb-x"; - static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) { PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev); @@ -558,16 +554,8 @@ static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))); _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2)); _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1)); - if (ppc->chip_type == PNV_CHIP_POWER10) { - _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10, - sizeof(compat_p10))); - } else if (ppc->chip_type == PNV_CHIP_POWER9) { - _FDT(fdt_setprop(fdt, offset, "compatible", compat_p9, - sizeof(compat_p9))); - } else { - _FDT(fdt_setprop(fdt, offset, "compatible", compat_p8, - sizeof(compat_p8))); - } + _FDT(fdt_setprop(fdt, offset, "compatible", ppc->compat, + ppc->compat_size)); return 0; } @@ -581,6 +569,7 @@ static void pnv_psi_power8_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PnvPsiClass *ppc = PNV_PSI_CLASS(klass); + static const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x"; dc->desc = "PowerNV PSI Controller POWER8"; dc->realize = pnv_psi_power8_realize; @@ -590,6 +579,8 @@ static void pnv_psi_power8_class_init(ObjectClass *klass, void *data) ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE; ppc->bar_mask = PSIHB_BAR_MASK; ppc->irq_set = pnv_psi_power8_irq_set; + ppc->compat = compat; + ppc->compat_size = sizeof(compat); } static const TypeInfo pnv_psi_power8_info = { @@ -888,6 +879,7 @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PnvPsiClass *ppc = PNV_PSI_CLASS(klass); XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass); + static const char compat[] = "ibm,power9-psihb-x\0ibm,psihb-x"; dc->desc = "PowerNV PSI Controller POWER9"; dc->realize = pnv_psi_power9_realize; @@ -897,6 +889,8 @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE; ppc->bar_mask = PSIHB9_BAR_MASK; ppc->irq_set = pnv_psi_power9_irq_set; + ppc->compat = compat; + ppc->compat_size = sizeof(compat); xfc->notify = pnv_psi_notify; } @@ -917,12 +911,15 @@ static void pnv_psi_power10_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PnvPsiClass *ppc = PNV_PSI_CLASS(klass); + static const char compat[] = "ibm,power10-psihb-x\0ibm,psihb-x"; dc->desc = "PowerNV PSI Controller POWER10"; ppc->chip_type = PNV_CHIP_POWER10; ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE; ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE; + ppc->compat = compat; + ppc->compat_size = sizeof(compat); } static const TypeInfo pnv_psi_power10_info = { diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h index a044aab304..fc068c95e5 100644 --- a/include/hw/ppc/pnv_psi.h +++ b/include/hw/ppc/pnv_psi.h @@ -83,6 +83,8 @@ typedef struct PnvPsiClass { uint32_t xscom_pcba; uint32_t xscom_size; uint64_t bar_mask; + const char *compat; + int compat_size; void (*irq_set)(PnvPsi *psi, int, bool state); } PnvPsiClass;