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[RFC,1/4] ppc: Drop PPC_EMULATE_32BITS_HYPV stub

Message ID 20200103063911.180977-2-david@gibson.dropbear.id.au
State New, archived
Headers show
Series target/ppc: Correct some errors with real mode handling | expand

Commit Message

David Gibson Jan. 3, 2020, 6:39 a.m. UTC
The only effect of the PPC_EMULATE_32BITS_HYPV define is to change how
MSR_HVB is defined.  This appears to be something to handle hypervisor mode
for 32-bit CPUs, but there's really no other code to handle this.  The
MSR_THV bit, which it uses is implemented for no cpus we model.

It's unlikely anyone is going to implement this any time soon, so just drop

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
 target/ppc/cpu.h | 7 -------
 1 file changed, 7 deletions(-)
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diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 103bfe9dc2..2de9e2fa2b 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -26,8 +26,6 @@ 
 #include "exec/cpu-defs.h"
 #include "cpu-qom.h"
-/* #define PPC_EMULATE_32BITS_HYPV */
 #define TARGET_PAGE_BITS_64K 16
@@ -450,14 +448,9 @@  typedef struct ppc_v3_pate_t {
 #define MSR_HVB (1ULL << MSR_SHV)
 #define msr_hv  msr_shv
-#if defined(PPC_EMULATE_32BITS_HYPV)
-#define MSR_HVB (1ULL << MSR_THV)
-#define msr_hv  msr_thv
 #define MSR_HVB (0ULL)
 #define msr_hv  (0)
 /* DSISR */
 #define DSISR_NOPTE              0x40000000