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Tue, 4 Feb 2020 09:52:20 +0000 From: Klaus Jensen To: Subject: [PATCH v5 09/26] nvme: add temperature threshold feature Date: Tue, 4 Feb 2020 10:51:51 +0100 Message-ID: <20200204095208.269131-10-k.jensen@samsung.com> X-Mailer: git-send-email 2.25.0 In-Reply-To: <20200204095208.269131-1-k.jensen@samsung.com> MIME-Version: 1.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrIKsWRmVeSWpSXmKPExsWy7djP87pX7SzjDC7MlrTY3N/OaLH/4DdW i0mHrjFaLLmYajHvlrLFrHftbBbHe3ewOLB7nNtxnt1j06pONo871/aweTy5tpnJ4/2+q2wB rFFcNimpOZllqUX6dglcGT9WNbEVXNSomHTiHmsDY49cFyMHh4SAicSZT5VdjFwcQgIrGCUW Lj/DBOF8YZRYv6eBDcL5zCjx5sgk5i5GTrCOe3tmM0IkljNKbP69lAWu6vzVRVAtpxklFt14 xArh7GSU2HPrJhtIP5uApsT2P/9ZQGwRAWmJ9quTwIqYBX4zSsxtnAhWJCzgKHGo4zDYQhYB FYn3m4+xg5zLK2AtcfJeIsQd8hKzG0+DlXMChfevOsEEYvMKCEqcnPkEbD4zUE3z1tnMELaE xMEXL5hBdkkI7GKX+LH+KxPEIBeJ7z9/s0HYwhKvjm9hh7BlJP7vnM8E0dDNKNH34StU9wxG ienLvrNBAtBaou9MDkSDo8SeWRugwnwSN94KQizmk5i0bTozRJhXoqNNCKJaTWJH01bGCYzK s5CcPQvJ2bOQnL2AkXkVo3hqaXFuemqxYV5quV5xYm5xaV66XnJ+7iZGYMI5/e/4px2MXy8l HWIU4GBU4uG9YGcRJ8SaWFZcmXuIUYKDWUmE97y+ZZwQb0piZVVqUX58UWlOavEhRmkOFiVx XuNFL2OFBNITS1KzU1MLUotgskwcnFINjC3e9+Mf3Vibe+qS0aswnr8i/O9DHhqfYt8cPvVZ pOS0I9/2H9z9W09u4+Vq7vlv5nVVfEv2VZ69c9J9y9mzMzrY+k8syjWN8OlKkjXZZl92iGtt W5xKkty0b26mE2fOSvE6c6/Wfh3L43UGS0S3hRZ90J9XJNfwyCz0q8O9YknJ344dq1t+VCmx FGckGmoxFxUnAgCreOB+NAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrDIsWRmVeSWpSXmKPExsVy+t/xu7pX7SzjDLqeslps7m9ntNh/8Bur xaRD1xgtllxMtZh3S9li1rt2NovjvTtYHNg9zu04z+6xaVUnm8eda3vYPJ5c28zk8X7fVbYA 1ig9m6L80pJUhYz84hJbpWhDCyM9Q0sLPSMTSz1DY/NYKyNTJX07m5TUnMyy1CJ9uwS9jB+r mtgKLmpUTDpxj7WBsUeui5GTQ0LAROLentmMXYxcHEICSxkldi3+xgqRkJH4dOUjO4QtLPHn WhcbRNFHRokXL55DdZxmlHj95ARUZiejxLHLuxlBWtgENCW2//nPAmKLCEhLtF+dBDaWWeA3 o8SfvkAQW1jAUeJQx2FmEJtFQEXi/eZjQOs4OHgFrCVO3kuE2CwvMbvxNBuIzQkU3r/qBBNI iZCAlUTrUW6QMK+AoMTJmU9YIKbLSzRvnc0MYUtIHHzxgnkCo/AsJGWzkJTNQlK2gJF5FaNI amlxbnpusaFecWJucWleul5yfu4mRmDMbTv2c/MOxksbgw8xCnAwKvHwXrCziBNiTSwrrsw9 xCjBwawkwnte3zJOiDclsbIqtSg/vqg0J7X4EKMp0GsTmaVEk/OB6SCvJN7Q1NDcwtLQ3Njc 2MxCSZy3Q+BgjJBAemJJanZqakFqEUwfEwenVAMjf3rYPPGtfC92uyza9P/6z8jrle++vFmU yWPTHPerYbO78c4fi/aK32mTTF9g/H2nbtu/mQsVm+6ua2S7uPrjIU1PrRU9BVW7PHyWWjxy WdxdFLVrptS9ODHvXIbMdJP/MR4ZReefWG8JfL7xzpziuv2JmYwHa1LnfPnU28U87ULq/01f hOM/K7EUZyQaajEXFScCANxXMjnPAgAA X-CMS-MailID: 20200204095221eucas1p1d5b1c9578d79e6bcc5714976bbe7dc11 X-Msg-Generator: CA X-RootMTR: 20200204095221eucas1p1d5b1c9578d79e6bcc5714976bbe7dc11 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20200204095221eucas1p1d5b1c9578d79e6bcc5714976bbe7dc11 References: <20200204095208.269131-1-k.jensen@samsung.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 210.118.77.11 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" It might seem wierd to implement this feature for an emulated device, but it is mandatory to support and the feature is useful for testing asynchronous event request support, which will be added in a later patch. Signed-off-by: Klaus Jensen --- hw/block/nvme.c | 50 ++++++++++++++++++++++++++++++++++++++++++++ hw/block/nvme.h | 2 ++ include/block/nvme.h | 7 ++++++- 3 files changed, 58 insertions(+), 1 deletion(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 81514eaef63a..f72348344832 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -45,6 +45,9 @@ #define NVME_SPEC_VER 0x00010201 #define NVME_MAX_QS PCI_MSIX_FLAGS_QSIZE +#define NVME_TEMPERATURE 0x143 +#define NVME_TEMPERATURE_WARNING 0x157 +#define NVME_TEMPERATURE_CRITICAL 0x175 #define NVME_GUEST_ERR(trace, fmt, ...) \ do { \ @@ -798,9 +801,31 @@ static uint16_t nvme_get_feature_timestamp(NvmeCtrl *n, NvmeCmd *cmd) static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) { uint32_t dw10 = le32_to_cpu(cmd->cdw10); + uint32_t dw11 = le32_to_cpu(cmd->cdw11); uint32_t result; switch (dw10) { + case NVME_TEMPERATURE_THRESHOLD: + result = 0; + + /* + * The controller only implements the Composite Temperature sensor, so + * return 0 for all other sensors. + */ + if (NVME_TEMP_TMPSEL(dw11)) { + break; + } + + switch (NVME_TEMP_THSEL(dw11)) { + case 0x0: + result = cpu_to_le16(n->features.temp_thresh_hi); + break; + case 0x1: + result = cpu_to_le16(n->features.temp_thresh_low); + break; + } + + break; case NVME_VOLATILE_WRITE_CACHE: result = blk_enable_write_cache(n->conf.blk); trace_nvme_dev_getfeat_vwcache(result ? "enabled" : "disabled"); @@ -845,6 +870,23 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *cmd, NvmeRequest *req) uint32_t dw11 = le32_to_cpu(cmd->cdw11); switch (dw10) { + case NVME_TEMPERATURE_THRESHOLD: + if (NVME_TEMP_TMPSEL(dw11)) { + break; + } + + switch (NVME_TEMP_THSEL(dw11)) { + case 0x0: + n->features.temp_thresh_hi = NVME_TEMP_TMPTH(dw11); + break; + case 0x1: + n->features.temp_thresh_low = NVME_TEMP_TMPTH(dw11); + break; + default: + return NVME_INVALID_FIELD | NVME_DNR; + } + + break; case NVME_VOLATILE_WRITE_CACHE: blk_set_enable_write_cache(n->conf.blk, dw11 & 1); break; @@ -1366,6 +1408,9 @@ static void nvme_init_state(NvmeCtrl *n) n->namespaces = g_new0(NvmeNamespace, n->num_namespaces); n->sq = g_new0(NvmeSQueue *, n->params.num_queues); n->cq = g_new0(NvmeCQueue *, n->params.num_queues); + + n->temperature = NVME_TEMPERATURE; + n->features.temp_thresh_hi = NVME_TEMPERATURE_WARNING; } static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev) @@ -1447,6 +1492,11 @@ static void nvme_init_ctrl(NvmeCtrl *n) id->acl = 3; id->frmw = 7 << 1; id->lpa = 1 << 0; + + /* recommended default value (~70 C) */ + id->wctemp = cpu_to_le16(NVME_TEMPERATURE_WARNING); + id->cctemp = cpu_to_le16(NVME_TEMPERATURE_CRITICAL); + id->sqes = (0x6 << 4) | 0x6; id->cqes = (0x4 << 4) | 0x4; id->nn = cpu_to_le32(n->num_namespaces); diff --git a/hw/block/nvme.h b/hw/block/nvme.h index a867bdfabafd..1518f32557a3 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -108,6 +108,7 @@ typedef struct NvmeCtrl { uint64_t irq_status; uint64_t host_timestamp; /* Timestamp sent by the host */ uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */ + uint16_t temperature; NvmeNamespace *namespaces; NvmeSQueue **sq; @@ -115,6 +116,7 @@ typedef struct NvmeCtrl { NvmeSQueue admin_sq; NvmeCQueue admin_cq; NvmeIdCtrl id_ctrl; + NvmeFeatureVal features; } NvmeCtrl; static inline uint64_t nvme_ns_nlbas(NvmeCtrl *n, NvmeNamespace *ns) diff --git a/include/block/nvme.h b/include/block/nvme.h index d2f65e8fe496..ff31cb32117c 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -616,7 +616,8 @@ enum NvmeIdCtrlOncs { typedef struct NvmeFeatureVal { uint32_t arbitration; uint32_t power_mgmt; - uint32_t temp_thresh; + uint16_t temp_thresh_hi; + uint16_t temp_thresh_low; uint32_t err_rec; uint32_t volatile_wc; uint32_t num_queues; @@ -635,6 +636,10 @@ typedef struct NvmeFeatureVal { #define NVME_INTC_THR(intc) (intc & 0xff) #define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff) +#define NVME_TEMP_THSEL(temp) ((temp >> 20) & 0x3) +#define NVME_TEMP_TMPSEL(temp) ((temp >> 16) & 0xf) +#define NVME_TEMP_TMPTH(temp) (temp & 0xffff) + enum NvmeFeatureIds { NVME_ARBITRATION = 0x1, NVME_POWER_MANAGEMENT = 0x2,