From patchwork Thu Feb 6 10:54:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 11368169 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 13B6C14E3 for ; Thu, 6 Feb 2020 10:57:38 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id DFB8220659 for ; Thu, 6 Feb 2020 10:57:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="trOC2uwh" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org DFB8220659 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:35718 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1izeqn-0000Am-11 for patchwork-qemu-devel@patchwork.kernel.org; Thu, 06 Feb 2020 05:57:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:49788) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1izeoK-00031Z-EC for qemu-devel@nongnu.org; Thu, 06 Feb 2020 05:55:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1izeoJ-0006qq-18 for qemu-devel@nongnu.org; Thu, 06 Feb 2020 05:55:04 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:36765) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1izeoH-0006hr-2w for qemu-devel@nongnu.org; Thu, 06 Feb 2020 05:55:02 -0500 Received: by mail-wm1-x343.google.com with SMTP id p17so6490955wma.1 for ; Thu, 06 Feb 2020 02:55:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xWQDTJxCBS53lXeb1FTjGVhvsu7aORlIiz5LAboaglI=; b=trOC2uwhrS9cFy6q8n8rB93uXwtZlc21RJ4HbK8BhZxNqGtVVtgfSLcXaMOgtR66+b M3k/EjzdHUw4/awPXZi0tM2QtDH3aVz/sTIksGVcrtoUNRfC0WJCzn/kDykKV+jAMbIJ unVOxNfwkBiQijEnW6JBtI+6AZuF7hAtqUZRDYQEmgPbSmH9nZsdxppY8jbVNft7/oqv uKydfsBYmZLW53YeNb9A6ghMKGCVTaycFxJHDNyBwl8r0j0GjxE1xjJx9R7ypQ1tnwn6 +HGeUE+L5y12sXyrw6uDwXGoxLQTUKD7J34LVAH6QHswgB5fx00maEZh7AHdNLlKEPEI Le5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xWQDTJxCBS53lXeb1FTjGVhvsu7aORlIiz5LAboaglI=; b=ApZloACnZnlOykDBiLp0luNC+t1qiurUo+65TUNifO/++cFVEmfd54QpRjs4XIT2HW HF+fjglkxi4pw2M/KuBoCSAt3YwO5km0Ors7PnvPGWqZBxpCntqBHNesC0G2WXCYnJYs zIh/5b3VrEq9Q1e3XVK/6X1rdC0rzRWG9nwAZmhDQzUQgi+Oe+LlWoCCwU4TGIDaOjmo 2uXkgE41+Lsygxh9Eoe4mhhzHbkirtTSM3tGkWUVwcpD6C43AV8INyp1XdBckdxOKoaH Q4Kv5P2rrqABqZwcHwUR6/r9mKzdrxLFdV5/QLCe2Xj3cI6AVPth+3dCvAZhnvsfhhGy 6rjA== X-Gm-Message-State: APjAAAVfTBJL0drqaAXqW+q3nhrejjpfVttb/xvl8y7penRm/gG/KhlY /0nrsxRkygcg+IIUc4GUrpJU7+jMfhKsrw== X-Google-Smtp-Source: APXvYqwWK+R415JnPsxg+qjxPVnIqjLt0IryCDjrrSg0//pgrY60AYuucMvQPrd7N8WGn4NTySNIog== X-Received: by 2002:a1c:f001:: with SMTP id a1mr3737781wmb.76.1580986498900; Thu, 06 Feb 2020 02:54:58 -0800 (PST) Received: from cloudburst.c.hoisthospitality.com ([135.196.99.211]) by smtp.gmail.com with ESMTPSA id m21sm3364995wmi.27.2020.02.06.02.54.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2020 02:54:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v7 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* Date: Thu, 6 Feb 2020 10:54:18 +0000 Message-Id: <20200206105448.4726-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200206105448.4726-1-richard.henderson@linaro.org> References: <20200206105448.4726-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" This is part of a reorganization to the set of mmu_idx. The EL1&0 regime is the only one that uses 2-stage translation. Spelling out Stage avoids confusion with Secure. Tested-by: Alex Bennée Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- v5: Adjust || indentation (ajb) --- target/arm/cpu.h | 4 ++-- target/arm/internals.h | 6 +++--- target/arm/helper.c | 27 ++++++++++++++------------- 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6da3d3043..afc3e76ce5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2923,8 +2923,8 @@ typedef enum ARMMMUIdx { /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ - ARMMMUIdx_S1NSE0 = 0 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_S1NSE1 = 1 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB, } ARMMMUIdx; /* Bit macros for the core-mmu-index values for each index, diff --git a/target/arm/internals.h b/target/arm/internals.h index 1509e45e98..280b5b0c82 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -810,8 +810,8 @@ static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) switch (mmu_idx) { case ARMMMUIdx_E10_0: case ARMMMUIdx_E10_1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_S1E2: case ARMMMUIdx_Stage2: case ARMMMUIdx_MPrivNegPri: @@ -975,7 +975,7 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env); #ifdef CONFIG_USER_ONLY static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) { - return ARMMMUIdx_S1NSE0; + return ARMMMUIdx_Stage1_E0; } #else ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); diff --git a/target/arm/helper.c b/target/arm/helper.c index a6d4f449cc..2d87c3a2e5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3041,7 +3041,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value, bool take_exc = false; if (fi.s1ptw && current_el == 1 && !arm_is_secure(env) - && (mmu_idx == ARMMMUIdx_S1NSE1 || mmu_idx == ARMMMUIdx_S1NSE0)) { + && (mmu_idx == ARMMMUIdx_Stage1_E1 || + mmu_idx == ARMMMUIdx_Stage1_E0)) { /* * Synchronous stage 2 fault on an access made as part of the * translation table walk for AT S1E0* or AT S1E1* insn @@ -3189,10 +3190,10 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) mmu_idx = ARMMMUIdx_S1E3; break; case 2: - mmu_idx = ARMMMUIdx_S1NSE1; + mmu_idx = ARMMMUIdx_Stage1_E1; break; case 1: - mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; + mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; break; default: g_assert_not_reached(); @@ -3205,10 +3206,10 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) mmu_idx = ARMMMUIdx_S1SE0; break; case 2: - mmu_idx = ARMMMUIdx_S1NSE0; + mmu_idx = ARMMMUIdx_Stage1_E0; break; case 1: - mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; + mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; break; default: g_assert_not_reached(); @@ -3262,7 +3263,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, case 0: switch (ri->opc1) { case 0: /* AT S1E1R, AT S1E1W */ - mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1; + mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_Stage1_E1; break; case 4: /* AT S1E2R, AT S1E2W */ mmu_idx = ARMMMUIdx_S1E2; @@ -3275,7 +3276,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, } break; case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0; + mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_Stage1_E0; break; case 4: /* AT S12E1R, AT S12E1W */ mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_E10_1; @@ -8717,8 +8718,8 @@ static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) case ARMMMUIdx_S1SE0: return arm_el_is_aa64(env, 3) ? 1 : 3; case ARMMMUIdx_S1SE1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_MPrivNegPri: case ARMMMUIdx_MUserNegPri: case ARMMMUIdx_MPriv: @@ -8776,7 +8777,7 @@ static inline bool regime_translation_disabled(CPUARMState *env, } if ((env->cp15.hcr_el2 & HCR_DC) && - (mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1)) { + (mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1)) { /* HCR.DC means SCTLR_EL1.M behaves as 0 */ return true; } @@ -8821,7 +8822,7 @@ static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx) static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) { if (mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_E10_1) { - mmu_idx += (ARMMMUIdx_S1NSE0 - ARMMMUIdx_E10_0); + mmu_idx += (ARMMMUIdx_Stage1_E0 - ARMMMUIdx_E10_0); } return mmu_idx; } @@ -8856,7 +8857,7 @@ static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_Stage1_E0: case ARMMMUIdx_MUser: case ARMMMUIdx_MSUser: case ARMMMUIdx_MUserNegPri: @@ -9087,7 +9088,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr addr, MemTxAttrs txattrs, ARMMMUFaultInfo *fi) { - if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) && + if ((mmu_idx == ARMMMUIdx_Stage1_E0 || mmu_idx == ARMMMUIdx_Stage1_E1) && !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { target_ulong s2size; hwaddr s2pa;