| Message ID | 20200214072127.64330-4-anup.patel@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V Spike machine improvements | expand |
On Thu, Feb 13, 2020 at 11:24 PM Anup Patel <anup.patel@wdc.com> wrote: > > Currently, the upstream Spike ISA simulator allows more than > one CPUs so we update QEMU Spike machine on similar lines to > allow more than one CPUs. > > The maximum number of CPUs for QEMU Spike machine is kept > same as QEMU Virt machine. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/spike.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 060a86f922..1eac0d9a83 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -469,7 +469,7 @@ static void spike_machine_init(MachineClass *mc) > { > mc->desc = "RISC-V Spike Board"; > mc->init = spike_board_init; > - mc->max_cpus = 1; > + mc->max_cpus = 8; > mc->is_default = 1; > mc->default_cpu_type = SPIKE_V1_10_0_CPU; > } > -- > 2.17.1 > >
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 060a86f922..1eac0d9a83 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -469,7 +469,7 @@ static void spike_machine_init(MachineClass *mc) { mc->desc = "RISC-V Spike Board"; mc->init = spike_board_init; - mc->max_cpus = 1; + mc->max_cpus = 8; mc->is_default = 1; mc->default_cpu_type = SPIKE_V1_10_0_CPU; }
Currently, the upstream Spike ISA simulator allows more than one CPUs so we update QEMU Spike machine on similar lines to allow more than one CPUs. The maximum number of CPUs for QEMU Spike machine is kept same as QEMU Virt machine. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- hw/riscv/spike.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)