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Fri, 14 Feb 2020 07:22:13 +0000 From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH 3/3] hw/riscv/spike: Allow more than one CPUs Date: Fri, 14 Feb 2020 12:51:27 +0530 Message-Id: <20200214072127.64330-4-anup.patel@wdc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200214072127.64330-1-anup.patel@wdc.com> References: <20200214072127.64330-1-anup.patel@wdc.com> X-ClientProxiedBy: MA1PR0101CA0015.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::25) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) MIME-Version: 1.0 Received: from wdc.com (106.51.31.230) by MA1PR0101CA0015.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:21::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2729.23 via Frontend Transport; Fri, 14 Feb 2020 07:22:09 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [106.51.31.230] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 3b45c916-a3da-4008-2378-08d7b11e9c72 X-MS-TrafficTypeDiagnostic: MN2PR04MB6288: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-Forefront-PRVS: 03137AC81E X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10019020)(4636009)(136003)(346002)(376002)(39860400002)(366004)(396003)(199004)(189003)(110136005)(478600001)(54906003)(316002)(52116002)(1076003)(7696005)(66946007)(36756003)(16526019)(8676002)(4326008)(4744005)(81156014)(1006002)(44832011)(55236004)(8886007)(2906002)(956004)(26005)(66556008)(66476007)(8936002)(2616005)(5660300002)(86362001)(186003)(55016002)(81166006)(6666004)(32040200004); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB6288; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: d2oVMRC2/mQGjO9IS/ZVeMb94q9zRQ0kNJnjOCqW1nkATIL22RlR36e4iS47nSQRV5hqtzyjMmtPBBBl2TbU4V7CYahhNxfmUcqvsEogG+fqfnCdm5/fr/zORWjbEGGpyK538jxlirwuUx/IzRwFS3Mw6+s7itz/Bh5Tr0ONpa7OPEmEFo8QrJ1GDyg06sw4irihG2F2r/F5+sjWtUB8wdK5txDPt53K+oX8iq2L+WnfvqFHeflr8Pew2Dj2055d6LIv3GQYqmpNKwtqIHo7pWOmsVx1SvJG+H1W+wU4GEzaS0Oac3IHKE9qGM99aGtiQOrdk85vIZQGBDBywaQyW1Jf+qk+hvQ/DXrdgFzzfrZ06dG9YUGUv80Ao2FAyd9+nfwun8io6Bs6vm41bOeJOUJ7HCZzDyiy66cjN+hMJOFbh6krz8ULd/TCeqeMYBywtow8WDG9c1R/IoCJa+tSyQPH5LNeACOWCa51HjIitc1iParHogEMg/W5f3yepU/9 X-MS-Exchange-AntiSpam-MessageData: ku/s4C4uI+7ezBZYSpud+MG+qGYll8jEIFmRvCrHU90cRRzu7nnKvfUIqhpY23yqCF42f7YHmxbof3gI6rHxm3fYGN+HqgF+IXjyFVtErOKEfaFR8TFH1PXHs5n/UAWA9LkRtS+INvxbPnOAnDtTmQ== X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3b45c916-a3da-4008-2378-08d7b11e9c72 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2020 07:22:13.2013 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: u3H93okejwB4ryZi+GLlLiywC/5mvB94U4CbaHcqkjVEIsXBX0jW0inCAa4ogxxYgSLJpJ/mLBCnTM0JF1n9jg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6288 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 216.71.154.45 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Currently, the upstream Spike ISA simulator allows more than one CPUs so we update QEMU Spike machine on similar lines to allow more than one CPUs. The maximum number of CPUs for QEMU Spike machine is kept same as QEMU Virt machine. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- hw/riscv/spike.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 060a86f922..1eac0d9a83 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -469,7 +469,7 @@ static void spike_machine_init(MachineClass *mc) { mc->desc = "RISC-V Spike Board"; mc->init = spike_board_init; - mc->max_cpus = 1; + mc->max_cpus = 8; mc->is_default = 1; mc->default_cpu_type = SPIKE_V1_10_0_CPU; }