diff mbox series

[PULL,28/52] target/arm: Provide ARMv8.4-PMU in '-cpu max'

Message ID	20200221130740.7583-29-peter.maydell@linaro.org (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=TTYX=4J=nongnu.org=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 56B3A206D7 From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 28/52] target/arm: Provide ARMv8.4-PMU in '-cpu max' Date: Fri, 21 Feb 2020 13:07:16 +0000 Message-Id: <20200221130740.7583-29-peter.maydell@linaro.org> In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: list Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	[PULL,01/52] aspeed/scu: Create separate write callbacks \| expand [PULL,01/52] aspeed/scu: Create separate write callbacks [PULL,02/52] aspeed/scu: Implement chip ID register [PULL,03/52] hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register [PULL,04/52] mainstone: Make providing flash images non-mandatory [PULL,05/52] z2: Make providing flash images non-mandatory [PULL,06/52] target/arm: Flush high bits of sve register after AdvSIMD EXT [PULL,07/52] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX [PULL,08/52] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN [PULL,09/52] target/arm: Flush high bits of sve register after AdvSIMD INS [PULL,10/52] target/arm: Use bit 55 explicitly for pauth [PULL,11/52] target/arm: Fix select for aa64_va_parameters_both [PULL,12/52] target/arm: Remove ttbr1_valid check from get_phys_addr_lpae [PULL,13/52] target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid [PULL,14/52] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers [PULL,15/52] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan [PULL,16/52] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions [PULL,17/52] target/arm: Define and use any_predinv isar_feature test [PULL,18/52] target/arm: Factor out PMU register definitions [PULL,19/52] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 [PULL,20/52] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field [PULL,21/52] target/arm: Define an aa32_pmu_8_1 isar feature test function [PULL,22/52] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks [PULL,23/52] target/arm: Stop assuming DBGDIDR always exists [PULL,24/52] target/arm: Move DBGDIDR into ARMISARegisters [PULL,25/52] target/arm: Read debug-related ID registers from KVM [PULL,26/52] target/arm: Implement ARMv8.1-PMU extension [PULL,27/52] target/arm: Implement ARMv8.4-PMU extension [PULL,28/52] target/arm: Provide ARMv8.4-PMU in '-cpu max' [PULL,29/52] target/arm: Correct definition of PMCRDP [PULL,30/52] target/arm: Correct handling of PMCR_EL0.LC bit [PULL,31/52] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks [PULL,32/52] target/arm: Use isar_feature function for testing AA32HPD feature [PULL,33/52] target/arm: Use FIELD_EX32 for testing 32-bit fields [PULL,34/52] target/arm: Correctly implement ACTLR2, HACTLR2 [PULL,35/52] hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file [PULL,36/52] hcd-ehci: Introduce "companion-enable" sysbus property [PULL,37/52] arm: allwinner: Wire up USB ports [PULL,38/52] target/arm: Vectorize USHL and SSHL [PULL,39/52] target/arm: Convert PMUL.8 to gvec [PULL,40/52] target/arm: Convert PMULL.64 to gvec [PULL,41/52] target/arm: Convert PMULL.8 to gvec [PULL,42/52] xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd [PULL,43/52] sh4: Fix PCI ISA IO memory subregion [PULL,44/52] target/arm: Rename isar_feature_aa32_simd_r32 [PULL,45/52] target/arm: Use isar_feature_aa32_simd_r32 more places [PULL,46/52] target/arm: Set MVFR0.FPSP for ARMv5 cpus [PULL,47/52] target/arm: Add isar_feature_aa32_simd_r16 [PULL,48/52] target/arm: Rename isar_feature_aa32_fpdp_v2 [PULL,49/52] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} [PULL,50/52] target/arm: Perform fpdp_v2 check first [PULL,51/52] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 [PULL,52/52] target/arm: Add missing checks for fpsp_v2

Commit Message

Peter Maydell Feb. 21, 2020, 1:07 p.m. UTC

Set the ID register bits to provide ARMv8.4-PMU (and implicitly
also ARMv8.1-PMU) in the 'max' CPU.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200214175116.9164-16-peter.maydell@linaro.org
---
 target/arm/cpu64.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff mbox series

Patch

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f8f74a7ecda..c9452894035 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -703,6 +703,14 @@  static void aarch64_max_initfn(Object *obj)
         u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
         cpu->id_mmfr3 = u;
 
+        u = cpu->isar.id_aa64dfr0;
+        u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
+        cpu->isar.id_aa64dfr0 = u;
+
+        u = cpu->isar.id_dfr0;
+        u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+        cpu->isar.id_dfr0 = u;
+
         /*
          * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
          * so do not set MVFR1.FPHP.  Strictly speaking this is not legal,