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Thu, 27 Feb 2020 11:27:11 +0000 Received: from DOMINUS.corp.kimin.kr (1.214.196.86) by HK2PR03CA0063.apcprd03.prod.outlook.com (2603:1096:202:17::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.11 via Frontend Transport; Thu, 27 Feb 2020 11:27:09 +0000 From: Stephanos Ioannidis Subject: [PATCH 2/2] hw/arm/armv7m: Downgrade CPU reset handler priority Thread-Topic: [PATCH 2/2] hw/arm/armv7m: Downgrade CPU reset handler priority Thread-Index: AQHV7WDamNGXYjwsUEm9K1g4p+T2pA== Date: Thu, 27 Feb 2020 11:27:10 +0000 Message-ID: <20200227112617.66044-2-root@stephanos.io> References: <20200227112617.66044-1-root@stephanos.io> In-Reply-To: <20200227112617.66044-1-root@stephanos.io> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR03CA0063.apcprd03.prod.outlook.com (2603:1096:202:17::33) To SLXP216MB0285.KORP216.PROD.OUTLOOK.COM (2603:1096:100:9::8) x-mailer: git-send-email 2.17.1 authentication-results: spf=none (sender IP is ) smtp.mailfrom=root@stephanos.io; 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x-microsoft-antispam-message-info: hWYO4gQIr2y19K0zXGZItOpmAAROlo9lJtFQgiIGO9mXwTnfTkWqK0xSAAPCEiqZOhenD5yXpsHa0dbeze/3ppFNEBW0oJXKVrhagEsmMORGYH09z2lp5KeKQnQmohS+L4z+EBKDMssuhAiI0NJ9bJqqrfmdu+bQ/pW0lJ61LGYRnJiKWZV3cx1Qrenj/M3m7CtgKKXX8P49VFRmBbtqsXeVBJgeie5cQ85j6BL1AcD32+PWUf3tn15zS+XOWg/vbeEpTP/8mXPbBcoFZd6e1xKjv3Pq0vNMffe/NKzkAAKbJjKtBbqOLvE5ub6vhpGFoi8wEi6cdkebK7wUWZEchZBhwragWCrYqNb3OnQzPkkgqfzZyCEXqn1CInqUQs6IgraLQ/Ii8lw5BsfqJyWGxQpjVt3HPxqwtvnoHRgGHafpppCQqfDmb5/BwSRcXaALNxSVz8o0npwx6so813JZz8Fo+n8o8QwNzDHE4+SpyXIkqtH6IDMOc70H+sqW9gvYHws3vciiUnfUoV9FSi8FFA== x-ms-exchange-antispam-messagedata: CvBObwq0Lwcc9II0LN/fW0N7GSduRbeqTfJibRLclRsceSabHnZ/ic49YTGXjEDkDSuHC45t5W165rr8qplRXmN1ckD0EJCIGwbigzYt0msh985N8GR2cge9N6o5qiMIen5hHYl8EOwVsa2rJGBhWw== MIME-Version: 1.0 X-OriginatorOrg: stephanos.io X-MS-Exchange-CrossTenant-Network-Message-Id: f5a23963-5b5e-4f05-5988-08d7bb77fc7a X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Feb 2020 11:27:11.0472 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: c98113d8-f05d-4479-8605-bfc8e93dc16d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: iw4AYUkIIiW5Nk9jPQmEsYPVorXz8pqFR+10p6FNZGAdC8jjBdfmqNIbH0bVBowmqddzzBJKgp26IqmV4XkeVg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SLXP216MB0031 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.128.101 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:ARM TCG CPUs" , Stephanos Ioannidis , "open list:All patches CC here" Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The ARMv7-M CPU reset handler, which loads the initial SP and PC register values from the vector table, is currently executed before the ROM reset handler (rom_reset), and this causes the devices that alias low memory region (e.g. STM32F405 that aliases the flash memory located at 0x8000000 to 0x0) to load an invalid reset vector of 0 when the kernel image is linked to be loaded at the high memory address. For instance, it is norm for the STM32F405 firmware ELF image to have the text and rodata sections linked at 0x8000000, as this facilitates proper image loading by the firmware burning utility, and the processor can execute in place from the high flash memory address region as well. In order to resolve this issue, this commit downgrades the ARMCPU reset handler invocation priority level to -1 such that it is always executed after the ROM reset handler, which has a priority level of 0. Signed-off-by: Stephanos Ioannidis --- hw/arm/armv7m.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 7531b97ccd..8b7c4b12a6 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -352,7 +352,8 @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) * way A-profile does it. Note that this means that every M profile * board must call this function! */ - qemu_register_reset(armv7m_reset, cpu); + qemu_register_reset_with_priority( + QEMU_RESET_PRIORITY_LEVEL(-1), armv7m_reset, cpu); } static Property bitband_properties[] = {