diff mbox series

[v2,3/3] hw/riscv/spike: Allow more than one CPUs

Message ID 20200303140037.85311-4-anup.patel@wdc.com (mailing list archive)
State New, archived
Headers show
Series RISC-V Spike machine improvements | expand

Commit Message

Anup Patel March 3, 2020, 2 p.m. UTC 
Currently, the upstream Spike ISA simulator allows more than
one CPUs so we update QEMU Spike machine on similar lines to
allow more than one CPUs.

The maximum number of CPUs for QEMU Spike machine is kept
same as QEMU Virt machine.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 hw/riscv/spike.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index b0395e227c..1799b9291c 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -472,7 +472,7 @@  static void spike_machine_init(MachineClass *mc)
 {
     mc->desc = "RISC-V Spike Board";
     mc->init = spike_board_init;
-    mc->max_cpus = 1;
+    mc->max_cpus = 8;
     mc->is_default = true;
     mc->default_cpu_type = SPIKE_V1_10_0_CPU;
 }