From patchwork Fri Mar 13 03:49:49 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yifei Jiang X-Patchwork-Id: 11435969 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C3C3D1392 for ; Fri, 13 Mar 2020 03:57:42 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6183B206E2 for ; Fri, 13 Mar 2020 03:57:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6183B206E2 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:53465 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbS9-0000ne-DF for patchwork-qemu-devel@patchwork.kernel.org; Thu, 12 Mar 2020 23:57:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47983) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbML-0006uR-Cp for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jCbMK-0000gU-6x for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:41 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:3202 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jCbMJ-0000Za-RH; Thu, 12 Mar 2020 23:51:40 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 8BC5E364828BCADEAA05; Fri, 13 Mar 2020 11:51:36 +0800 (CST) Received: from huawei.com (10.133.201.158) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Fri, 13 Mar 2020 11:51:25 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC 9/9] target/riscv: add host riscv64 cpu type Date: Fri, 13 Mar 2020 11:49:49 +0800 Message-ID: <20200313034949.3028-10-jiangyifei@huawei.com> X-Mailer: git-send-email 2.23.0.windows.1 In-Reply-To: <20200313034949.3028-1-jiangyifei@huawei.com> References: <20200313034949.3028-1-jiangyifei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.201.158] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: anup.patel@wdc.com, zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, Yifei Jiang , dengkai1@huawei.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Currently, host cpu is inherited simply. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 5 +++++ target/riscv/cpu.h | 1 + 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3c3264869f..11557719cf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -203,6 +203,10 @@ static void rv64imacu_nommu_cpu_init(Object *obj) set_feature(env, RISCV_FEATURE_PMP); } +static void riscv_host_cpu_init(Object *obj) +{ +} + #endif static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -622,6 +626,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), /* Deprecated */ DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2724eca714..10b053a467 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -39,6 +39,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") /* Deprecated */ #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu") #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")