Message ID | 20200603011317.473934-12-richard.henderson@linaro.org (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v7,01/42] target/arm: Add isar tests for mte | expand |
On Wed, 3 Jun 2020 at 02:13, Richard Henderson <richard.henderson@linaro.org> wrote: > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > v6: Inline the operation. > --- > target/arm/translate-a64.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a18d71ad98..7d0b7d5b58 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -5325,6 +5325,21 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) cpu_reg_sp(s, rn)); } break; + case 5: /* GMI */ + if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { + goto do_unallocated; + } else { + TCGv_i64 t1 = tcg_const_i64(1); + TCGv_i64 t2 = tcg_temp_new_i64(); + + tcg_gen_extract_i64(t2, cpu_reg_sp(s, rn), 56, 4); + tcg_gen_shl_i64(t1, t1, t2); + tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t1); + + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + } + break; case 8: /* LSLV */ handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd); break;
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v6: Inline the operation. --- target/arm/translate-a64.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)