| Message ID | 20200624185523.762240-3-ppandit@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | memory: assert and define MemoryRegionOps callbacks | expand |
P J P <ppandit@redhat.com> 于2020年6月25日周四 上午2:59写道： > > From: Prasad J Pandit <pjp@fedoraproject.org> > > Add pcie-msi mmio read method to avoid NULL pointer dereference > issue. > > Reported-by: Lei Sun <slei.casper@gmail.com> > Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> Reviewed-by: Li Qiang <liq3ea@gmail.com> > --- > hw/pci-host/designware.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c > index 8492c18991..82262bdfdf 100644 > --- a/hw/pci-host/designware.c > +++ b/hw/pci-host/designware.c > @@ -21,6 +21,7 @@ > #include "qemu/osdep.h" > #include "qapi/error.h" > #include "qemu/module.h" > +#include "qemu/log.h" > #include "hw/pci/msi.h" > #include "hw/pci/pci_bridge.h" > #include "hw/pci/pci_host.h" > @@ -63,6 +64,13 @@ designware_pcie_root_to_host(DesignwarePCIERoot *root) > return DESIGNWARE_PCIE_HOST(bus->parent); > } > > +static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr, > + unsigned size) > +{ > + qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); > + return 0; > +} > + > static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, > uint64_t val, unsigned len) > { > @@ -77,6 +85,7 @@ static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, > } > > static const MemoryRegionOps designware_pci_host_msi_ops = { > + .read = designware_pcie_root_msi_read, > .write = designware_pcie_root_msi_write, > .endianness = DEVICE_LITTLE_ENDIAN, > .valid = { > -- > 2.26.2 >
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 8492c18991..82262bdfdf 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" +#include "qemu/log.h" #include "hw/pci/msi.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_host.h" @@ -63,6 +64,13 @@ designware_pcie_root_to_host(DesignwarePCIERoot *root) return DESIGNWARE_PCIE_HOST(bus->parent); } +static uint64_t designware_pcie_root_msi_read(void *opaque, hwaddr addr, + unsigned size) +{ + qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__); + return 0; +} + static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) { @@ -77,6 +85,7 @@ static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, } static const MemoryRegionOps designware_pci_host_msi_ops = { + .read = designware_pcie_root_msi_read, .write = designware_pcie_root_msi_write, .endianness = DEVICE_LITTLE_ENDIAN, .valid = {