diff mbox series

[1/1] tcg/tcg-op: nonatomic_op should work with smaller memop

Message ID 20200701152156.1147-1-zhiwei_liu@c-sky.com (mailing list archive)
State New, archived
Headers show
Series [1/1] tcg/tcg-op: nonatomic_op should work with smaller memop | expand

Commit Message

LIU Zhiwei July 1, 2020, 3:21 p.m. UTC
Reserve MO_SIGN in load and extend another operator val according to memop.
Thus, we can call tcg_gen_atomic_*_tl with a smaller memop.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 tcg/tcg-op.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Richard Henderson July 1, 2020, 4:25 p.m. UTC | #1
On 7/1/20 8:21 AM, LIU Zhiwei wrote:
> -    tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN);
> +    tcg_gen_qemu_ld_i32(t1, addr, idx, memop);
> +    tcg_gen_ext_i32(val, val, memop);
>      gen(t2, t1, val);

I was just about to post a simiar patch.
The difference with mine is that I do not modify val:

-    gen(t2, t1, val);
+    tcg_gen_ext_i32(t2, val, memop);
+    gen(t2, t1, t2);


r~
LIU Zhiwei July 1, 2020, 11:44 p.m. UTC | #2
On 2020/7/2 0:25, Richard Henderson wrote:
> On 7/1/20 8:21 AM, LIU Zhiwei wrote:
>> -    tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN);
>> +    tcg_gen_qemu_ld_i32(t1, addr, idx, memop);
>> +    tcg_gen_ext_i32(val, val, memop);
>>       gen(t2, t1, val);
> I was just about to post a simiar patch.
> The difference with mine is that I do not modify val:
>
> -    gen(t2, t1, val);
> +    tcg_gen_ext_i32(t2, val, memop);
> +    gen(t2, t1, t2);
I see. So just ignore this patch.:-)

Zhiwei
>
> r~
diff mbox series

Patch

diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index e60b74fb82..9a0870cb18 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -3189,7 +3189,8 @@  static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
 
     memop = tcg_canonicalize_memop(memop, 0, 0);
 
-    tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN);
+    tcg_gen_qemu_ld_i32(t1, addr, idx, memop);
+    tcg_gen_ext_i32(val, val, memop);
     gen(t2, t1, val);
     tcg_gen_qemu_st_i32(t2, addr, idx, memop);
 
@@ -3232,7 +3233,8 @@  static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
 
     memop = tcg_canonicalize_memop(memop, 1, 0);
 
-    tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN);
+    tcg_gen_qemu_ld_i64(t1, addr, idx, memop);
+    tcg_gen_ext_i64(val, val, memop);
     gen(t2, t1, val);
     tcg_gen_qemu_st_i64(t2, addr, idx, memop);