| Message ID | 20200701234344.91843-4-ljp@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add several Power ISA 3.1 32/64-bit vector instructions | expand |
On Wed, Jul 01, 2020 at 06:43:38PM -0500, Lijun Pan wrote: > POWER ISA 3.1 introduces following byte-reverse instructions: > brd: Byte-Reverse Doubleword X-form > brw: Byte-Reverse Word X-form > brh: Byte-Reverse Halfword X-form > > Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Applied to ppc-for-5.2. > --- > v4: make it compile on all targets > v3: fix the store issue in br[dwh] > simplify brw implementation > add "if defined(TARGET_PPC64)" > v2: fix coding style > use Power ISA 3.1 flag > > target/ppc/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 4ce3d664b5..590c3e3bc7 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -6971,7 +6971,47 @@ static void gen_dform3D(DisasContext *ctx) > return gen_invalid(ctx); > } > > +#if defined(TARGET_PPC64) > +/* brd */ > +static void gen_brd(DisasContext *ctx) > +{ > + tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); > +} > + > +/* brw */ > +static void gen_brw(DisasContext *ctx) > +{ > + tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); > + tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); > + > +} > + > +/* brh */ > +static void gen_brh(DisasContext *ctx) > +{ > + TCGv_i64 t0 = tcg_temp_new_i64(); > + TCGv_i64 t1 = tcg_temp_new_i64(); > + TCGv_i64 t2 = tcg_temp_new_i64(); > + > + tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); > + tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); > + tcg_gen_and_i64(t2, t1, t0); > + tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); > + tcg_gen_shli_i64(t1, t1, 8); > + tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); > + > + tcg_temp_free_i64(t0); > + tcg_temp_free_i64(t1); > + tcg_temp_free_i64(t2); > +} > +#endif > + > static opcode_t opcodes[] = { > +#if defined(TARGET_PPC64) > +GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), > +GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), > +GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), > +#endif > GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), > GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), > GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 4ce3d664b5..590c3e3bc7 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6971,7 +6971,47 @@ static void gen_dform3D(DisasContext *ctx) return gen_invalid(ctx); } +#if defined(TARGET_PPC64) +/* brd */ +static void gen_brd(DisasContext *ctx) +{ + tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); +} + +/* brw */ +static void gen_brw(DisasContext *ctx) +{ + tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); + tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32); + +} + +/* brh */ +static void gen_brh(DisasContext *ctx) +{ + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 t2 = tcg_temp_new_i64(); + + tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull); + tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8); + tcg_gen_and_i64(t2, t1, t0); + tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0); + tcg_gen_shli_i64(t1, t1, 8); + tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); +} +#endif + static opcode_t opcodes[] = { +#if defined(TARGET_PPC64) +GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310), +GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310), +GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310), +#endif GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
POWER ISA 3.1 introduces following byte-reverse instructions: brd: Byte-Reverse Doubleword X-form brw: Byte-Reverse Word X-form brh: Byte-Reverse Halfword X-form Signed-off-by: Lijun Pan <ljp@linux.ibm.com> --- v4: make it compile on all targets v3: fix the store issue in br[dwh] simplify brw implementation add "if defined(TARGET_PPC64)" v2: fix coding style use Power ISA 3.1 flag target/ppc/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+)