| Message ID | 20200701234344.91843-6-ljp@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add several Power ISA 3.1 32/64-bit vector instructions | expand |
On Wed, Jul 01, 2020 at 06:43:40PM -0500, Lijun Pan wrote: > vmulld: Vector Multiply Low Doubleword. > > Signed-off-by: Lijun Pan <ljp@linux.ibm.com> Applied to ppc-for-5.2. > --- > v4: add missing changes, and split to 5/11, 6/11, 7/11 > v3: use tcg_gen_gvec_mul() > v2: fix coding style > use Power ISA 3.1 flag > > target/ppc/translate/vmx-impl.inc.c | 1 + > target/ppc/translate/vmx-ops.inc.c | 4 ++++ > 2 files changed, 5 insertions(+) > > diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c > index 6e79ffa650..8c89738552 100644 > --- a/target/ppc/translate/vmx-impl.inc.c > +++ b/target/ppc/translate/vmx-impl.inc.c > @@ -807,6 +807,7 @@ GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE, > GEN_VXFORM(vmulosb, 4, 4); > GEN_VXFORM(vmulosh, 4, 5); > GEN_VXFORM(vmulosw, 4, 6); > +GEN_VXFORM_V(vmulld, MO_64, tcg_gen_gvec_mul, 4, 7); > GEN_VXFORM(vmuleub, 4, 8); > GEN_VXFORM(vmuleuh, 4, 9); > GEN_VXFORM(vmuleuw, 4, 10); > diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c > index 84e05fb827..b49787ac97 100644 > --- a/target/ppc/translate/vmx-ops.inc.c > +++ b/target/ppc/translate/vmx-ops.inc.c > @@ -48,6 +48,9 @@ GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300) > GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \ > PPC2_ISA300) > > +#define GEN_VXFORM_310(name, opc2, opc3) \ > +GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA310) > + > #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \ > GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1) > > @@ -104,6 +107,7 @@ GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE), > GEN_VXFORM(vmulosb, 4, 4), > GEN_VXFORM(vmulosh, 4, 5), > GEN_VXFORM_207(vmulosw, 4, 6), > +GEN_VXFORM_310(vmulld, 4, 7), > GEN_VXFORM(vmuleub, 4, 8), > GEN_VXFORM(vmuleuh, 4, 9), > GEN_VXFORM_207(vmuleuw, 4, 10),
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c index 6e79ffa650..8c89738552 100644 --- a/target/ppc/translate/vmx-impl.inc.c +++ b/target/ppc/translate/vmx-impl.inc.c @@ -807,6 +807,7 @@ GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE, GEN_VXFORM(vmulosb, 4, 4); GEN_VXFORM(vmulosh, 4, 5); GEN_VXFORM(vmulosw, 4, 6); +GEN_VXFORM_V(vmulld, MO_64, tcg_gen_gvec_mul, 4, 7); GEN_VXFORM(vmuleub, 4, 8); GEN_VXFORM(vmuleuh, 4, 9); GEN_VXFORM(vmuleuw, 4, 10); diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c index 84e05fb827..b49787ac97 100644 --- a/target/ppc/translate/vmx-ops.inc.c +++ b/target/ppc/translate/vmx-ops.inc.c @@ -48,6 +48,9 @@ GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300) GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \ PPC2_ISA300) +#define GEN_VXFORM_310(name, opc2, opc3) \ +GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA310) + #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \ GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1) @@ -104,6 +107,7 @@ GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM(vmulosb, 4, 4), GEN_VXFORM(vmulosh, 4, 5), GEN_VXFORM_207(vmulosw, 4, 6), +GEN_VXFORM_310(vmulld, 4, 7), GEN_VXFORM(vmuleub, 4, 8), GEN_VXFORM(vmuleuh, 4, 9), GEN_VXFORM_207(vmuleuw, 4, 10),
vmulld: Vector Multiply Low Doubleword. Signed-off-by: Lijun Pan <ljp@linux.ibm.com> --- v4: add missing changes, and split to 5/11, 6/11, 7/11 v3: use tcg_gen_gvec_mul() v2: fix coding style use Power ISA 3.1 flag target/ppc/translate/vmx-impl.inc.c | 1 + target/ppc/translate/vmx-ops.inc.c | 4 ++++ 2 files changed, 5 insertions(+)