diff mbox series

[v4,07/11] target/ppc: add vmulld to INDEX_op_mul_vec case

Message ID 20200701234344.91843-8-ljp@linux.ibm.com (mailing list archive)
State New, archived
Headers show
Series Add several Power ISA 3.1 32/64-bit vector instructions | expand

Commit Message

Lijun Pan July 1, 2020, 11:43 p.m. UTC 
Group vmuluwm and vmulld. Make vmulld-specific
changes since it belongs to new ISA 3.1.

Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
    use Power ISA 3.1 flag

 tcg/ppc/tcg-target.h     |  2 ++
 tcg/ppc/tcg-target.inc.c | 12 ++++++++++--
 2 files changed, 12 insertions(+), 2 deletions(-)

Comments

Lijun Pan July 13, 2020, 7:40 p.m. UTC | #1 
> On Jul 1, 2020, at 6:43 PM, Lijun Pan <ljp@linux.ibm.com> wrote:
> 
> Group vmuluwm and vmulld. Make vmulld-specific
> changes since it belongs to new ISA 3.1.
> 
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
> ---
> v4: add missing changes, and split to 5/11, 6/11, 7/11
> v3: use tcg_gen_gvec_mul()
> v2: fix coding style
>    use Power ISA 3.1 flag
> 

Richard,
Do you have any opinion on this one?
Thanks,
Lijun


> tcg/ppc/tcg-target.h     |  2 ++
> tcg/ppc/tcg-target.inc.c | 12 ++++++++++--
> 2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
> index 4fa21f0e71..ff1249ef8e 100644
> --- a/tcg/ppc/tcg-target.h
> +++ b/tcg/ppc/tcg-target.h
> @@ -63,6 +63,7 @@ typedef enum {
>     tcg_isa_2_06,
>     tcg_isa_2_07,
>     tcg_isa_3_00,
> +    tcg_isa_3_10,
> } TCGPowerISA;
> 
> extern TCGPowerISA have_isa;
> @@ -72,6 +73,7 @@ extern bool have_vsx;
> #define have_isa_2_06  (have_isa >= tcg_isa_2_06)
> #define have_isa_2_07  (have_isa >= tcg_isa_2_07)
> #define have_isa_3_00  (have_isa >= tcg_isa_3_00)
> +#define have_isa_3_10  (have_isa >= tcg_isa_3_10)
> 
> /* optional instructions automatically implemented */
> #define TCG_TARGET_HAS_ext8u_i32        0 /* andi */
> diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
> index ee1f9227c1..caa8985b46 100644
> --- a/tcg/ppc/tcg-target.inc.c
> +++ b/tcg/ppc/tcg-target.inc.c
> @@ -564,6 +564,7 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
> #define VMULOUH    VX4(72)
> #define VMULOUW    VX4(136)       /* v2.07 */
> #define VMULUWM    VX4(137)       /* v2.07 */
> +#define VMULLD     VX4(457)       /* v3.10 */
> #define VMSUMUHM   VX4(38)
> 
> #define VMRGHB     VX4(12)
> @@ -3015,6 +3016,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
>             return -1;
>         case MO_32:
>             return have_isa_2_07 ? 1 : -1;
> +        case MO_64:
> +            return have_isa_3_10;
>         }
>         return 0;
>     case INDEX_op_bitsel_vec:
> @@ -3149,6 +3152,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
>     static const uint32_t
>         add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
>         sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
> +        mul_op[4] = { 0, 0, VMULUWM, VMULLD },
>         neg_op[4] = { 0, 0, VNEGW, VNEGD },
>         eq_op[4]  = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
>         ne_op[4]  = { VCMPNEB, VCMPNEH, VCMPNEW, 0 },
> @@ -3199,8 +3203,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
>         a1 = 0;
>         break;
>     case INDEX_op_mul_vec:
> -        tcg_debug_assert(vece == MO_32 && have_isa_2_07);
> -        insn = VMULUWM;
> +        insn = mul_op[vece];
>         break;
>     case INDEX_op_ssadd_vec:
>         insn = ssadd_op[vece];
> @@ -3709,6 +3712,11 @@ static void tcg_target_init(TCGContext *s)
>         have_isa = tcg_isa_3_00;
>     }
> #endif
> +#ifdef PPC_FEATURE2_ARCH_3_10
> +    if (hwcap2 & PPC_FEATURE2_ARCH_3_10) {
> +        have_isa = tcg_isa_3_10;
> +    }
> +#endif
> 
> #ifdef PPC_FEATURE2_HAS_ISEL
>     /* Prefer explicit instruction from the kernel. */
> -- 
> 2.23.0
> 
>
diff mbox series

Patch

diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 4fa21f0e71..ff1249ef8e 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -63,6 +63,7 @@  typedef enum {
     tcg_isa_2_06,
     tcg_isa_2_07,
     tcg_isa_3_00,
+    tcg_isa_3_10,
 } TCGPowerISA;
 
 extern TCGPowerISA have_isa;
@@ -72,6 +73,7 @@  extern bool have_vsx;
 #define have_isa_2_06  (have_isa >= tcg_isa_2_06)
 #define have_isa_2_07  (have_isa >= tcg_isa_2_07)
 #define have_isa_3_00  (have_isa >= tcg_isa_3_00)
+#define have_isa_3_10  (have_isa >= tcg_isa_3_10)
 
 /* optional instructions automatically implemented */
 #define TCG_TARGET_HAS_ext8u_i32        0 /* andi */
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index ee1f9227c1..caa8985b46 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -564,6 +564,7 @@  static int tcg_target_const_match(tcg_target_long val, TCGType type,
 #define VMULOUH    VX4(72)
 #define VMULOUW    VX4(136)       /* v2.07 */
 #define VMULUWM    VX4(137)       /* v2.07 */
+#define VMULLD     VX4(457)       /* v3.10 */
 #define VMSUMUHM   VX4(38)
 
 #define VMRGHB     VX4(12)
@@ -3015,6 +3016,8 @@  int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
             return -1;
         case MO_32:
             return have_isa_2_07 ? 1 : -1;
+        case MO_64:
+            return have_isa_3_10;
         }
         return 0;
     case INDEX_op_bitsel_vec:
@@ -3149,6 +3152,7 @@  static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     static const uint32_t
         add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
         sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
+        mul_op[4] = { 0, 0, VMULUWM, VMULLD },
         neg_op[4] = { 0, 0, VNEGW, VNEGD },
         eq_op[4]  = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
         ne_op[4]  = { VCMPNEB, VCMPNEH, VCMPNEW, 0 },
@@ -3199,8 +3203,7 @@  static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
         a1 = 0;
         break;
     case INDEX_op_mul_vec:
-        tcg_debug_assert(vece == MO_32 && have_isa_2_07);
-        insn = VMULUWM;
+        insn = mul_op[vece];
         break;
     case INDEX_op_ssadd_vec:
         insn = ssadd_op[vece];
@@ -3709,6 +3712,11 @@  static void tcg_target_init(TCGContext *s)
         have_isa = tcg_isa_3_00;
     }
 #endif
+#ifdef PPC_FEATURE2_ARCH_3_10
+    if (hwcap2 & PPC_FEATURE2_ARCH_3_10) {
+        have_isa = tcg_isa_3_10;
+    }
+#endif
 
 #ifdef PPC_FEATURE2_HAS_ISEL
     /* Prefer explicit instruction from the kernel. */