From patchwork Thu Jul 2 15:26:57 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Auger X-Patchwork-Id: 11639331 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E634A6C1 for ; Thu, 2 Jul 2020 15:35:19 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BCB8520737 for ; Thu, 2 Jul 2020 15:35:19 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="cpqD+rhH" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BCB8520737 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:46390 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jr1F9-0006M4-00 for patchwork-qemu-devel@patchwork.kernel.org; Thu, 02 Jul 2020 11:35:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43622) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jr188-00023Y-O4 for qemu-devel@nongnu.org; Thu, 02 Jul 2020 11:28:04 -0400 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:38622 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1jr186-0006TW-P9 for qemu-devel@nongnu.org; Thu, 02 Jul 2020 11:28:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1593703682; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HN2Tg6cktWjfVh/Lr05cfnKD1TEiS0BORvWfwZryVgo=; b=cpqD+rhHOb6ksLZnHQjGuEFkBXN9PBTSpjx/Z6nVUjtesoil5Q08TdsBB4jj56V8ukHUCr HpVvMH5s2/vbtpcunKAUrhlQMwuTyd8G3pHWvaohxAYJWxq4B66/zt0d/eK0GHPdTKTIUs c9oxAZ7XIW+DP0WudDXc4mxxWApu+/U= Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-477-3SCKL8uuPJu_nBRKr58w_Q-1; Thu, 02 Jul 2020 11:28:00 -0400 X-MC-Unique: 3SCKL8uuPJu_nBRKr58w_Q-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 73D7519253C0; Thu, 2 Jul 2020 15:27:58 +0000 (UTC) Received: from laptop.redhat.com (ovpn-112-70.ams2.redhat.com [10.36.112.70]) by smtp.corp.redhat.com (Postfix) with ESMTP id 08D7B5DD61; Thu, 2 Jul 2020 15:27:46 +0000 (UTC) From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, peterx@redhat.com Subject: [PATCH v2 7/9] hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper Date: Thu, 2 Jul 2020 17:26:57 +0200 Message-Id: <20200702152659.8522-8-eric.auger@redhat.com> In-Reply-To: <20200702152659.8522-1-eric.auger@redhat.com> References: <20200702152659.8522-1-eric.auger@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=eric.auger@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=207.211.31.81; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/02 04:18:28 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jean-philippe@linaro.org, robh@kernel.org, robin.murphy@arm.com, mst@redhat.com, zhangfei.gao@foxmail.com, shameerali.kolothum.thodi@huawei.com, will@kernel.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Let's introduce an helper for S1 IOVA range invalidation. This will be used for NH_VA and NH_VAA commands. It decodes the same fields, trace, calls the UNMAP notifiers and invalidate the corresponding IOTLB entries. At the moment, we do not support 3.2 range invalidation yet. So it reduces to a single IOVA invalidation. Note the leaf bit now is also decoded for the CMD_TLBI_NH_VAA command. At the moment it is only used for tracing. Signed-off-by: Eric Auger Reviewed-by: Peter Maydell --- v1 -> v2: - added comment about leaf bit and added Peter's R-b --- hw/arm/smmuv3.c | 36 +++++++++++++++++------------------- hw/arm/trace-events | 3 +-- 2 files changed, 18 insertions(+), 21 deletions(-) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index b717bde832..e4a2cea7ad 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -836,6 +836,22 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova) } } +static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd) +{ + dma_addr_t addr = CMD_ADDR(cmd); + uint8_t type = CMD_TYPE(cmd); + uint16_t vmid = CMD_VMID(cmd); + bool leaf = CMD_LEAF(cmd); + int asid = -1; + + if (type == SMMU_CMD_TLBI_NH_VA) { + asid = CMD_ASID(cmd); + } + trace_smmuv3_s1_range_inval(vmid, asid, addr, leaf); + smmuv3_inv_notifiers_iova(s, asid, addr); + smmu_iotlb_inv_iova(s, asid, addr); +} + static int smmuv3_cmdq_consume(SMMUv3State *s) { SMMUState *bs = ARM_SMMU(s); @@ -966,27 +982,9 @@ static int smmuv3_cmdq_consume(SMMUv3State *s) smmu_iotlb_inv_all(bs); break; case SMMU_CMD_TLBI_NH_VAA: - { - dma_addr_t addr = CMD_ADDR(&cmd); - uint16_t vmid = CMD_VMID(&cmd); - - trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr); - smmuv3_inv_notifiers_iova(bs, -1, addr); - smmu_iotlb_inv_iova(bs, -1, addr); - break; - } case SMMU_CMD_TLBI_NH_VA: - { - uint16_t asid = CMD_ASID(&cmd); - uint16_t vmid = CMD_VMID(&cmd); - dma_addr_t addr = CMD_ADDR(&cmd); - bool leaf = CMD_LEAF(&cmd); - - trace_smmuv3_cmdq_tlbi_nh_va(vmid, asid, addr, leaf); - smmuv3_inv_notifiers_iova(bs, asid, addr); - smmu_iotlb_inv_iova(bs, asid, addr); + smmuv3_s1_range_inval(bs, &cmd); break; - } case SMMU_CMD_TLBI_EL3_ALL: case SMMU_CMD_TLBI_EL3_VA: case SMMU_CMD_TLBI_EL2_ALL: diff --git a/hw/arm/trace-events b/hw/arm/trace-events index f74d3e920f..c219fe9e82 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -45,8 +45,7 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%d - end=0x%d" smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d" smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid %d (hits=%d, misses=%d, hit rate=%d)" smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid %d (hits=%d, misses=%d, hit rate=%d)" -smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr, bool leaf) "vmid =%d asid =%d addr=0x%"PRIx64" leaf=%d" -smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =%d addr=0x%"PRIx64 +smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, bool leaf) "vmid =%d asid =%d addr=0x%"PRIx64" leaf=%d" smmuv3_cmdq_tlbi_nh(void) "" smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d" smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d"