[PULL,v2,61/64] target/riscv: vector slide instructions

Message ID	20200702162354.928528-62-alistair.francis@wdc.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=VsHw=AN=nongnu.org=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CA80220720 IronPort-SDR: GBKUzTDmOKF0RQV4hSrMrHTM9Tn5f3n53uy8NHSUSOzqqHC45n40k/aD8b+6cmp4HOjJR4xXTz k7RB88GUB7utJ4SMGR6nMraOlKSaMKdyALtZQlVjiB/fyV5L0EmfUYLQ25Cg7if+LJv8JQXDc9 r/yicpuTZgmL8Ihd2PILo2ImZv9qrfknS3eM/v3bZy+MtYaeG29yJi0J8bQaw4tyl8WcRpjA6/ ZZtbjXCwOPXQ8JYrVKizErufB1A6QHpjZMfcS+FnU1kXcUbDa3kll2t77n+Ihac31iNVRiS9Pl /Yc= IronPort-SDR: kdAkEMGZMQ8bgSU/bC+yH3ceDuj/VuSYi90P9epWoP+VUQKsWUMUY2btkdJqKXyMZwpQsd+8cX GFEZKDFeXvqDpGAQjBrpvXIW67eTNKliA= IronPort-SDR: MPzNCSauQ4ChUyhySncp1sPsY1z4b/HgdR9JABFsJtbkgMX7D/a4/4un2xF+1+M7A9lOeRZW12 9SVDrjXBusgQ== WDCIronportException: Internal From: Alistair Francis <alistair.francis@wdc.com> To: peter.maydell@linaro.org, qemu-devel@nongnu.org Subject: [PULL v2 61/64] target/riscv: vector slide instructions Date: Thu, 2 Jul 2020 09:23:51 -0700 Message-Id: <20200702162354.928528-62-alistair.francis@wdc.com> In-Reply-To: <20200702162354.928528-1-alistair.francis@wdc.com> References: <20200702162354.928528-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=4451fe355=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com Precedence: list Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>, Richard Henderson <richard.henderson@linaro.org>, LIU Zhiwei <zhiwei_liu@c-sky.com> Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	[PULL,v2,01/64] riscv: plic: Honour source priorities \| expand [PULL,v2,01/64] riscv: plic: Honour source priorities [PULL,v2,02/64] riscv: plic: Add a couple of mising sifive_plic_update calls [PULL,v2,03/64] hw/riscv: Allow 64 bit access to SiFive CLINT [PULL,v2,04/64] target/riscv: add vector extension field in CPURISCVState [PULL,v2,05/64] target/riscv: implementation-defined constant parameters [PULL,v2,06/64] target/riscv: support vector extension csr [PULL,v2,07/64] target/riscv: add vector configure instruction [PULL,v2,08/64] target/riscv: add an internals.h header [PULL,v2,09/64] target/riscv: add vector stride load and store instructions [PULL,v2,10/64] target/riscv: add vector index load and store instructions [PULL,v2,11/64] target/riscv: add fault-only-first unit stride load [PULL,v2,12/64] target/riscv: add vector amo operations [PULL,v2,13/64] target/riscv: vector single-width integer add and subtract [PULL,v2,14/64] target/riscv: vector widening integer add and subtract [PULL,v2,15/64] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions [PULL,v2,16/64] target/riscv: vector bitwise logical instructions [PULL,v2,17/64] target/riscv: vector single-width bit shift instructions [PULL,v2,18/64] target/riscv: vector narrowing integer right shift instructions [PULL,v2,19/64] target/riscv: vector integer comparison instructions [PULL,v2,20/64] target/riscv: vector integer min/max instructions [PULL,v2,21/64] target/riscv: vector single-width integer multiply instructions [PULL,v2,22/64] target/riscv: vector integer divide instructions [PULL,v2,23/64] target/riscv: vector widening integer multiply instructions [PULL,v2,24/64] target/riscv: vector single-width integer multiply-add instructions [PULL,v2,25/64] target/riscv: vector widening integer multiply-add instructions [PULL,v2,26/64] target/riscv: vector integer merge and move instructions [PULL,v2,27/64] target/riscv: vector single-width saturating add and subtract [PULL,v2,28/64] target/riscv: vector single-width averaging add and subtract [PULL,v2,29/64] target/riscv: vector single-width fractional multiply with rounding and saturation [PULL,v2,30/64] target/riscv: vector widening saturating scaled multiply-add [PULL,v2,31/64] target/riscv: vector single-width scaling shift instructions [PULL,v2,32/64] target/riscv: vector narrowing fixed-point clip instructions [PULL,v2,33/64] target/riscv: vector single-width floating-point add/subtract instructions [PULL,v2,34/64] target/riscv: vector widening floating-point add/subtract instructions [PULL,v2,35/64] target/riscv: vector single-width floating-point multiply/divide instructions [PULL,v2,36/64] target/riscv: vector widening floating-point multiply [PULL,v2,37/64] target/riscv: vector single-width floating-point fused multiply-add instructions [PULL,v2,38/64] target/riscv: vector widening floating-point fused multiply-add instructions [PULL,v2,39/64] target/riscv: vector floating-point square-root instruction [PULL,v2,40/64] target/riscv: vector floating-point min/max instructions [PULL,v2,41/64] target/riscv: vector floating-point sign-injection instructions [PULL,v2,42/64] target/riscv: vector floating-point compare instructions [PULL,v2,43/64] target/riscv: vector floating-point classify instructions [PULL,v2,44/64] target/riscv: vector floating-point merge instructions [PULL,v2,45/64] target/riscv: vector floating-point/integer type-convert instructions [PULL,v2,46/64] target/riscv: widening floating-point/integer type-convert instructions [PULL,v2,47/64] target/riscv: narrowing floating-point/integer type-convert instructions [PULL,v2,48/64] target/riscv: vector single-width integer reduction instructions [PULL,v2,49/64] target/riscv: vector wideing integer reduction instructions [PULL,v2,50/64] target/riscv: vector single-width floating-point reduction instructions [PULL,v2,51/64] target/riscv: vector widening floating-point reduction instructions [PULL,v2,52/64] target/riscv: vector mask-register logical instructions [PULL,v2,53/64] target/riscv: vector mask population count vmpopc [PULL,v2,54/64] target/riscv: vmfirst find-first-set mask bit [PULL,v2,55/64] target/riscv: set-X-first mask bit [PULL,v2,56/64] target/riscv: vector iota instruction [PULL,v2,57/64] target/riscv: vector element index instruction [PULL,v2,58/64] target/riscv: integer extract instruction [PULL,v2,59/64] target/riscv: integer scalar move instruction [PULL,v2,60/64] target/riscv: floating-point scalar move instructions [PULL,v2,61/64] target/riscv: vector slide instructions [PULL,v2,62/64] target/riscv: vector register gather instruction [PULL,v2,63/64] target/riscv: vector compress instruction [PULL,v2,64/64] target/riscv: configure and turn on vector extension from command line

Message ID

20200702162354.928528-62-alistair.francis@wdc.com (mailing list archive)

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WDCIronportException: Internal
From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org,
	qemu-devel@nongnu.org
Subject: [PULL v2 61/64] target/riscv: vector slide instructions
Date: Thu,  2 Jul 2020 09:23:51 -0700
Message-Id: <20200702162354.928528-62-alistair.francis@wdc.com>
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Series

[PULL,v2,01/64] riscv: plic: Honour source priorities | expand

Commit Message

Alistair Francis July 2, 2020, 4:23 p.m. UTC

From: LIU Zhiwei <zhiwei_liu@c-sky.com>

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-59-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/helper.h                   |  17 ++++
 target/riscv/insn32.decode              |   6 ++
 target/riscv/insn_trans/trans_rvv.inc.c |  18 ++++
 target/riscv/vector_helper.c            | 114 ++++++++++++++++++++++++
 4 files changed, 155 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c6695ea7a8..29a5eb7049 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1119,3 +1119,20 @@  DEF_HELPER_4(vid_v_b, void, ptr, ptr, env, i32)
 DEF_HELPER_4(vid_v_h, void, ptr, ptr, env, i32)
 DEF_HELPER_4(vid_v_w, void, ptr, ptr, env, i32)
 DEF_HELPER_4(vid_v_d, void, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vslideup_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslideup_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslideup_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslideup_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslidedown_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslidedown_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslidedown_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslidedown_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1up_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1up_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1up_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1up_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1down_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1down_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1down_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vslide1down_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 17288a3c95..36123f71b9 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -568,6 +568,12 @@  vext_x_v        001100 1 ..... ..... 010 ..... 1010111 @r
 vmv_s_x         001101 1 00000 ..... 110 ..... 1010111 @r2
 vfmv_f_s        001100 1 ..... 00000 001 ..... 1010111 @r2rd
 vfmv_s_f        001101 1 00000 ..... 101 ..... 1010111 @r2
+vslideup_vx     001110 . ..... ..... 100 ..... 1010111 @r_vm
+vslideup_vi     001110 . ..... ..... 011 ..... 1010111 @r_vm
+vslide1up_vx    001110 . ..... ..... 110 ..... 1010111 @r_vm
+vslidedown_vx   001111 . ..... ..... 100 ..... 1010111 @r_vm
+vslidedown_vi   001111 . ..... ..... 011 ..... 1010111 @r_vm
+vslide1down_vx  001111 . ..... ..... 110 ..... 1010111 @r_vm
 
 vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
 vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 7af16ce0a8..4ed6d1ee2e 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2758,3 +2758,21 @@  static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
     }
     return false;
 }
+
+/* Vector Slide Instructions */
+static bool slideup_check(DisasContext *s, arg_rmrr *a)
+{
+    return (vext_check_isa_ill(s) &&
+            vext_check_overlap_mask(s, a->rd, a->vm, true) &&
+            vext_check_reg(s, a->rd, false) &&
+            vext_check_reg(s, a->rs2, false) &&
+            (a->rd != a->rs2));
+}
+
+GEN_OPIVX_TRANS(vslideup_vx, slideup_check)
+GEN_OPIVX_TRANS(vslide1up_vx, slideup_check)
+GEN_OPIVI_TRANS(vslideup_vi, 1, vslideup_vx, slideup_check)
+
+GEN_OPIVX_TRANS(vslidedown_vx, opivx_check)
+GEN_OPIVX_TRANS(vslide1down_vx, opivx_check)
+GEN_OPIVI_TRANS(vslidedown_vi, 1, vslidedown_vx, opivx_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 0fa899b6ff..51c4bc5756 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4697,3 +4697,117 @@  GEN_VEXT_VID_V(vid_v_b, uint8_t, H1, clearb)
 GEN_VEXT_VID_V(vid_v_h, uint16_t, H2, clearh)
 GEN_VEXT_VID_V(vid_v_w, uint32_t, H4, clearl)
 GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq)
+
+/*
+ *** Vector Permutation Instructions
+ */
+
+/* Vector Slide Instructions */
+#define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H, CLEAR_FN)                    \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
+                  CPURISCVState *env, uint32_t desc)                      \
+{                                                                         \
+    uint32_t mlen = vext_mlen(desc);                                      \
+    uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;                   \
+    uint32_t vm = vext_vm(desc);                                          \
+    uint32_t vl = env->vl;                                                \
+    target_ulong offset = s1, i;                                          \
+                                                                          \
+    for (i = offset; i < vl; i++) {                                       \
+        if (!vm && !vext_elem_mask(v0, mlen, i)) {                        \
+            continue;                                                     \
+        }                                                                 \
+        *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset));          \
+    }                                                                     \
+    CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE));          \
+}
+
+/* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1, clearb)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2, clearh)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4, clearl)
+GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8, clearq)
+
+#define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H, CLEAR_FN)                  \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
+                  CPURISCVState *env, uint32_t desc)                      \
+{                                                                         \
+    uint32_t mlen = vext_mlen(desc);                                      \
+    uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;                   \
+    uint32_t vm = vext_vm(desc);                                          \
+    uint32_t vl = env->vl;                                                \
+    target_ulong offset = s1, i;                                          \
+                                                                          \
+    for (i = 0; i < vl; ++i) {                                            \
+        target_ulong j = i + offset;                                      \
+        if (!vm && !vext_elem_mask(v0, mlen, i)) {                        \
+            continue;                                                     \
+        }                                                                 \
+        *((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j));  \
+    }                                                                     \
+    CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE));          \
+}
+
+/* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1, clearb)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2, clearh)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4, clearl)
+GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8, clearq)
+
+#define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H, CLEAR_FN)                   \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
+                  CPURISCVState *env, uint32_t desc)                      \
+{                                                                         \
+    uint32_t mlen = vext_mlen(desc);                                      \
+    uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;                   \
+    uint32_t vm = vext_vm(desc);                                          \
+    uint32_t vl = env->vl;                                                \
+    uint32_t i;                                                           \
+                                                                          \
+    for (i = 0; i < vl; i++) {                                            \
+        if (!vm && !vext_elem_mask(v0, mlen, i)) {                        \
+            continue;                                                     \
+        }                                                                 \
+        if (i == 0) {                                                     \
+            *((ETYPE *)vd + H(i)) = s1;                                   \
+        } else {                                                          \
+            *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1));           \
+        }                                                                 \
+    }                                                                     \
+    CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE));          \
+}
+
+/* vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] */
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1, clearb)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2, clearh)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4, clearl)
+GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8, clearq)
+
+#define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H, CLEAR_FN)                 \
+void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2,         \
+                  CPURISCVState *env, uint32_t desc)                      \
+{                                                                         \
+    uint32_t mlen = vext_mlen(desc);                                      \
+    uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen;                   \
+    uint32_t vm = vext_vm(desc);                                          \
+    uint32_t vl = env->vl;                                                \
+    uint32_t i;                                                           \
+                                                                          \
+    for (i = 0; i < vl; i++) {                                            \
+        if (!vm && !vext_elem_mask(v0, mlen, i)) {                        \
+            continue;                                                     \
+        }                                                                 \
+        if (i == vl - 1) {                                                \
+            *((ETYPE *)vd + H(i)) = s1;                                   \
+        } else {                                                          \
+            *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1));           \
+        }                                                                 \
+    }                                                                     \
+    CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE));          \
+}
+
+/* vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] */
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1, clearb)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2, clearh)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4, clearl)
+GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq)

[PULL,v2,61/64] target/riscv: vector slide instructions

Commit Message

Patch