[RFC,20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns

Message ID	20200710104920.13550-21-frank.chang@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=OzId=AV=nongnu.org=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5C6CD20720 From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC 20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns Date: Fri, 10 Jul 2020 18:48:34 +0800 Message-Id: <20200710104920.13550-21-frank.chang@sifive.com> In-Reply-To: <20200710104920.13550-1-frank.chang@sifive.com> References: <20200710104920.13550-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::544; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x544.google.com Precedence: list Cc: Frank Chang <frank.chang@sifive.com>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	target/riscv: support vector extension v0.9 \| expand [RFC,00/65] target/riscv: support vector extension v0.9 [RFC,01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion [RFC,02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() [RFC,03/65] target/riscv: fix return value of do_opivx_widen() [RFC,04/65] target/riscv: fix vill bit index in vtype register [RFC,05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec [RFC,06/65] target/riscv: rvv-0.9: add vcsr register [RFC,07/65] target/riscv: rvv-0.9: add vector context status [RFC,08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags [RFC,09/65] target/riscv: rvv-0.9: add vlenb register [RFC,10/65] target/riscv: rvv-0.9: remove MLEN calculations [RFC,11/65] target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA [RFC,12/65] target/riscv: rvv-0.9: update check functions [RFC,13/65] target/riscv: rvv-0.9: configure instructions [RFC,14/65] target/riscv: rvv-0.9: stride load and store instructions [RFC,15/65] target/riscv: rvv-0.9: index load and store instructions [RFC,16/65] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns [RFC,17/65] target/riscv: rvv-0.9: fault-only-first unit stride load [RFC,18/65] target/riscv: rvv-0.9: amo operations [RFC,19/65] target/riscv: rvv-0.9: load/store whole register instructions [RFC,20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns [RFC,21/65] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation [RFC,22/65] target/riscv: rvv-0.9: floating-point square-root instruction [RFC,23/65] target/riscv: rvv-0.9: floating-point classify instructions [RFC,24/65] target/riscv: rvv-0.9: mask population count instruction [RFC,25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction [RFC,26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions [RFC,27/65] target/riscv: rvv-0.9: iota instruction [RFC,28/65] target/riscv: rvv-0.9: element index instruction [RFC,29/65] target/riscv: rvv-0.9: integer scalar move instructions [RFC,30/65] target/riscv: rvv-0.9: floating-point scalar move instructions [RFC,31/65] target/riscv: rvv-0.9: whole register move instructions [RFC,32/65] target/riscv: rvv-0.9: integer extension instructions [RFC,33/65] target/riscv: rvv-0.9: single-width averaging add and subtract instructions [RFC,34/65] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow [RFC,35/65] target/riscv: rvv-0.9: narrowing integer right shift instructions [RFC,36/65] target/riscv: rvv-0.9: widening integer multiply-add instructions [RFC,37/65] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions [RFC,38/65] target/riscv: rvv-0.9: integer merge and move instructions [RFC,39/65] target/riscv: rvv-0.9: single-width saturating add and subtract instructions [RFC,40/65] target/riscv: rvv-0.9: integer comparison instructions [RFC,41/65] target/riscv: rvv-0.9: floating-point compare instructions [RFC,42/65] target/riscv: rvv-0.9: single-width integer reduction instructions [RFC,43/65] target/riscv: rvv-0.9: widening integer reduction instructions [RFC,44/65] target/riscv: rvv-0.9: mask-register logical instructions [RFC,45/65] target/riscv: rvv-0.9: register gather instructions [RFC,46/65] target/riscv: rvv-0.9: slide instructions [RFC,47/65] target/riscv: rvv-0.9: floating-point slide instructions [RFC,48/65] target/riscv: rvv-0.9: narrowing fixed-point clip instructions [RFC,49/65] target/riscv: rvv-0.9: floating-point move instructions [RFC,50/65] target/riscv: rvv-0.9: floating-point/integer type-convert instructions [RFC,51/65] target/riscv: rvv-0.9: single-width floating-point reduction [RFC,52/65] target/riscv: rvv-0.9: widening floating-point reduction instructions [RFC,53/65] target/riscv: rvv-0.9: single-width scaling shift instructions [RFC,54/65] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add [RFC,55/65] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf [RFC,56/65] target/riscv: rvv-0.9: remove integer extract instruction [RFC,57/65] target/riscv: rvv-0.9: floating-point min/max instructions [RFC,58/65] target/riscv: rvv-0.9: widening floating-point/integer type-convert [RFC,59/65] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert [RFC,60/65] softfloat: add fp16 and uint8/int8 interconvert functions [RFC,61/65] fpu: fix float16 nan check [RFC,62/65] fpu: add api to handle alternative sNaN propagation [RFC,63/65] fpu: implement full set compare for fp16 [RFC,64/65] target/riscv: use softfloat lib float16 comparison functions [RFC,65/65] target/riscv: bump to RVV 0.9

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 39b9a462ab..2a006f956c 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -129,14 +129,32 @@ static inline uint32_t vext_vma(uint32_t desc) } /* - * Get vector group length in bytes. Its range is [64, 2048]. - * - * As simd_desc support at most 256, the max vlen is 512 bits. - * So vlen in bytes is encoded as maxsz. + * Get the maximum number of elements can be operated. */ -static inline uint32_t vext_maxsz(uint32_t desc) +static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz, bool is_ldst) { - return simd_maxsz(desc) << vext_lmul(desc); + /* + * As simd_desc support at most 256, the max vlen is 512 bits, + * so vlen in bytes (vlenb) is encoded as maxsz. + */ + uint32_t vlenb = simd_maxsz(desc); + + if (is_ldst) { + /* + * Vector load/store instructions have the EEW encoded + * directly in the instructions. The maximum vector size is + * calculated with EMUL rather than LMUL. + */ + uint32_t eew = esz << 3; + uint32_t sew = vext_sew(desc); + float flmul = vext_vflmul(desc); + float emul = (float)eew / sew * flmul; + uint32_t emul_r = emul < 1 ? 1 : emul; + return vlenb * emul_r / esz; + } else { + /* Return VLMAX */ + return vlenb * vext_vflmul(desc) / esz; + } } /* @@ -296,7 +314,7 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, { uint32_t i, k; uint32_t nf = vext_nf(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t max_elems = vext_max_elems(desc, esz, true); uint32_t vta = vext_vta(desc); /* probe every access*/ @@ -314,15 +332,15 @@ vext_ldst_stride(void *vd, void *v0, target_ulong base, } while (k < nf) { target_ulong addr = base + stride * i + k * esz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } /* clear tail elements */ if (clear_elem) { for (k = 0; k < nf; k++) { - clear_elem(vd, vta, env->vl + k * vlmax, - env->vl * esz, vlmax * esz); + clear_elem(vd, vta, env->vl + k * max_elems, + env->vl * esz, max_elems * esz); } } } @@ -371,7 +389,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, { uint32_t i, k; uint32_t nf = vext_nf(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t max_elems = vext_max_elems(desc, esz, true); uint32_t vta = vext_vta(desc); /* probe every access */ @@ -381,15 +399,15 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, k = 0; while (k < nf) { target_ulong addr = base + (i * nf + k) * esz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } /* clear tail elements */ if (clear_elem) { for (k = 0; k < nf; k++) { - clear_elem(vd, vta, env->vl + k * vlmax, - env->vl * esz, vlmax * esz); + clear_elem(vd, vta, env->vl + k * max_elems, + env->vl * esz, max_elems * esz); } } } @@ -472,7 +490,7 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, uint32_t i, k; uint32_t nf = vext_nf(desc); uint32_t vm = vext_vm(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t max_elems = vext_max_elems(desc, esz, true); uint32_t vta = vext_vta(desc); /* probe every access*/ @@ -491,15 +509,15 @@ vext_ldst_index(void *vd, void *v0, target_ulong base, } while (k < nf) { abi_ptr addr = get_index_addr(base, i, vs2) + k * esz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } /* clear tail elements */ if (clear_elem) { for (k = 0; k < nf; k++) { - clear_elem(vd, vta, env->vl + k * vlmax, - env->vl * esz, vlmax * esz); + clear_elem(vd, vta, env->vl + k * max_elems, + env->vl * esz, max_elems * esz); } } } @@ -570,7 +588,7 @@ vext_ldff(void *vd, void *v0, target_ulong base, uint32_t i, k, vl = 0; uint32_t nf = vext_nf(desc); uint32_t vm = vext_vm(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t max_elems = vext_max_elems(desc, esz, true); uint32_t vta = vext_vta(desc); target_ulong addr, offset, remain; @@ -622,7 +640,7 @@ ProbeSuccess: } while (k < nf) { target_ulong addr = base + (i * nf + k) * esz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } @@ -631,8 +649,8 @@ ProbeSuccess: return; } for (k = 0; k < nf; k++) { - clear_elem(vd, vta, env->vl + k * vlmax, - env->vl * esz, vlmax * esz); + clear_elem(vd, vta, env->vl + k * max_elems, + env->vl * esz, max_elems * esz); } } @@ -659,7 +677,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, { uint32_t i, k; uint32_t nf = vext_nf(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t max_elems = vext_max_elems(desc, esz, true); /* probe every access */ probe_pages(env, base, env->vlenb * nf * esz, ra, access_type); @@ -669,7 +687,7 @@ vext_ldst_whole(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, k = 0; while (k < nf) { target_ulong addr = base + (i * nf + k) * esz; - ldst_elem(env, addr, i + k * vlmax, vd, ra); + ldst_elem(env, addr, i + k * max_elems, vd, ra); k++; } } @@ -812,7 +830,7 @@ vext_amo_noatomic(void *vs3, void *v0, target_ulong base, target_long addr; uint32_t wd = vext_wd(desc); uint32_t vm = vext_vm(desc); - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t vlmax = vext_max_elems(desc, esz, false); uint32_t vta = vext_vta(desc); for (i = 0; i < env->vl; i++) { @@ -983,7 +1001,7 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, uint32_t esz, uint32_t dsz, opivv2_fn *fn, clear_fn *clearfn) { - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t vlmax = vext_max_elems(desc, esz, false); uint32_t vm = vext_vm(desc); uint32_t vta = vext_vta(desc); uint32_t vl = env->vl; @@ -995,7 +1013,7 @@ static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, } fn(vd, vs1, vs2, i); } - clearfn(vd, vta, vl, vl * dsz, vlmax * dsz); + clearfn(vd, vta, vl, vl * dsz, vlmax * dsz); } /* generate the helpers for OPIVV */ @@ -1048,7 +1066,7 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, uint32_t esz, uint32_t dsz, opivx2_fn fn, clear_fn *clearfn) { - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t vlmax = vext_max_elems(desc, esz, false); uint32_t vm = vext_vm(desc); uint32_t vta = vext_vta(desc); uint32_t vl = env->vl; @@ -1060,7 +1078,7 @@ static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, } fn(vd, s1, vs2, i); } - clearfn(vd, vta, vl, vl * dsz, vlmax * dsz); + clearfn(vd, vta, vl, vl * dsz, vlmax * dsz); } /* generate the helpers for OPIVX */ @@ -1247,7 +1265,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ { \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ + uint32_t vlmax = vext_max_elems(desc, esz, false); \ uint32_t vta = vext_vta(desc); \ uint32_t i; \ \ @@ -1277,7 +1295,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ { \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ + uint32_t vlmax = vext_max_elems(desc, esz, false); \ uint32_t vta = vext_vta(desc); \ uint32_t i; \ \ @@ -1339,7 +1357,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ void *vs2, CPURISCVState *env, uint32_t desc) \ { \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ + uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false);\ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -1427,7 +1445,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(TS1); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ + uint32_t vlmax = vext_max_elems(desc, esz, false); \ uint32_t vta = vext_vta(desc); \ uint32_t i; \ \ @@ -1465,7 +1483,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(TD); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ + uint32_t vlmax = vext_max_elems(desc, esz, false); \ uint32_t vta = vext_vta(desc); \ uint32_t i; \ \ @@ -2108,7 +2126,7 @@ void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \ { \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ + uint32_t vlmax = vext_max_elems(desc, esz, false); \ uint32_t vta = vext_vta(desc); \ uint32_t i; \ \ @@ -2130,7 +2148,7 @@ void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \ { \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ + uint32_t vlmax = vext_max_elems(desc, esz, false); \ uint32_t vta = vext_vta(desc); \ uint32_t i; \ \ @@ -2151,7 +2169,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ { \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ + uint32_t vlmax = vext_max_elems(desc, esz, false); \ uint32_t vta = vext_vta(desc); \ uint32_t i; \ \ @@ -2173,7 +2191,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ { \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ + uint32_t vlmax = vext_max_elems(desc, esz, false); \ uint32_t vta = vext_vta(desc); \ uint32_t i; \ \ @@ -2234,7 +2252,7 @@ vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2, uint32_t desc, uint32_t esz, uint32_t dsz, opivv2_rm_fn *fn, clear_fn *clearfn) { - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t vlmax = vext_max_elems(desc, esz, false); uint32_t vm = vext_vm(desc); uint32_t vta = vext_vta(desc); uint32_t vl = env->vl; @@ -2354,7 +2372,7 @@ vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2, uint32_t desc, uint32_t esz, uint32_t dsz, opivx2_rm_fn *fn, clear_fn *clearfn) { - uint32_t vlmax = vext_maxsz(desc) / esz; + uint32_t vlmax = vext_max_elems(desc, esz, false); uint32_t vm = vext_vm(desc); uint32_t vta = vext_vta(desc); uint32_t vl = env->vl; @@ -3258,7 +3276,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t vlmax = vext_maxsz(desc) / ESZ; \ + uint32_t vlmax = vext_max_elems(desc, ESZ, false); \ uint32_t vm = vext_vm(desc); \ uint32_t vta = vext_vta(desc); \ uint32_t vl = env->vl; \ @@ -3293,7 +3311,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \ void *vs2, CPURISCVState *env, \ uint32_t desc) \ { \ - uint32_t vlmax = vext_maxsz(desc) / ESZ; \ + uint32_t vlmax = vext_max_elems(desc, ESZ, false); \ uint32_t vm = vext_vm(desc); \ uint32_t vta = vext_vta(desc); \ uint32_t vl = env->vl; \ @@ -3864,7 +3882,7 @@ static void do_##NAME(void *vd, void *vs2, int i, \ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = vext_maxsz(desc) / ESZ; \ + uint32_t vlmax = vext_max_elems(desc, ESZ, false); \ uint32_t vm = vext_vm(desc); \ uint32_t vta = vext_vta(desc); \ uint32_t vl = env->vl; \ @@ -4041,7 +4059,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ { \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ + uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -4185,7 +4203,7 @@ static void do_##NAME(void *vd, void *vs2, int i) \ void HELPER(NAME)(void *vd, void *v0, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = vext_maxsz(desc) / ESZ; \ + uint32_t vlmax = vext_max_elems(desc, ESZ, false); \ uint32_t vm = vext_vm(desc); \ uint32_t vta = vext_vta(desc); \ uint32_t vl = env->vl; \ @@ -4272,7 +4290,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t esz = sizeof(ETYPE); \ - uint32_t vlmax = vext_maxsz(desc) / esz; \ + uint32_t vlmax = vext_max_elems(desc, esz, false); \ uint32_t vta = vext_vta(desc); \ uint32_t i; \ \ @@ -4772,7 +4790,7 @@ GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ + uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \ uint32_t vm = vext_vm(desc); \ uint32_t vta = vext_vta(desc); \ uint32_t vl = env->vl; \ @@ -4882,7 +4900,7 @@ GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ + uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \ uint32_t vm = vext_vm(desc); \ uint32_t vta = vext_vta(desc); \ uint32_t vl = env->vl; \ @@ -4912,7 +4930,7 @@ GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ + uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \ uint32_t vm = vext_vm(desc); \ uint32_t vta = vext_vta(desc); \ uint32_t vl = env->vl; \ @@ -4942,7 +4960,7 @@ GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8, clearq) void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ CPURISCVState *env, uint32_t desc) \ { \ - uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ + uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \ uint32_t vta = vext_vta(desc); \ uint32_t vl = env->vl; \ uint32_t num = 0, i; \

[RFC,20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns

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Patch