[RFC,29/65] target/riscv: rvv-0.9: integer scalar move instructions

Commit Message

Frank Chang July 10, 2020, 10:48 a.m. UTC

From: Frank Chang <[e-mail]>

Signed-off-by: Frank Chang <[e-mail]>
---
 target/riscv/insn32.decode              |  3 +-
 target/riscv/insn_trans/trans_rvv.inc.c | 59 +++++++++++++++++--------
 2 files changed, 43 insertions(+), 19 deletions(-)

Patch

diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 01316c908d..ef53df7c73 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -580,8 +580,9 @@  vmsif_m         010100 . ..... 00011 010 ..... 1010111 @r2_vm
 vmsof_m         010100 . ..... 00010 010 ..... 1010111 @r2_vm
 viota_m         010100 . ..... 10000 010 ..... 1010111 @r2_vm
 vid_v           010100 . 00000 10001 010 ..... 1010111 @r1_vm
+vmv_x_s         010000 1 ..... 00000 010 ..... 1010111 @r2rd
+vmv_s_x         010000 1 00000 ..... 110 ..... 1010111 @r2
 vext_x_v        001100 1 ..... ..... 010 ..... 1010111 @r
-vmv_s_x         001101 1 00000 ..... 110 ..... 1010111 @r2
 vfmv_f_s        001100 1 ..... 00000 001 ..... 1010111 @r2rd
 vfmv_s_f        001101 1 00000 ..... 101 ..... 1010111 @r2
 vslideup_vx     001110 . ..... ..... 100 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index c03f3326cc..801b9319a5 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2986,30 +2986,53 @@  static void vec_element_storei(DisasContext *s, int vreg,
     store_element(val, cpu_env, endian_ofs(s, vreg, idx), s->sew);
 }
 
+/* vmv.x.s rd, vs2 # x[rd] = vs2[0] */
+static bool trans_vmv_x_s(DisasContext *s, arg_vmv_x_s *a)
+{
+    REQUIRE_RVV;
+    VEXT_CHECK_ISA_ILL(s);
+
+    TCGv_i64 t1;
+    TCGv dest;
+
+    t1 = tcg_temp_new_i64();
+    dest = tcg_temp_new();
+    /*
+     * load vreg and sign-extend to 64 bits,
+     * then truncate to XLEN bits before storing to gpr.
+     */
+    vec_element_loadi(s, t1, a->rs2, 0, true);
+    tcg_gen_trunc_i64_tl(dest, t1);
+    gen_set_gpr(a->rd, dest);
+    tcg_temp_free_i64(t1);
+    tcg_temp_free(dest);
+    mark_vs_dirty(s);
+
+    return true;
+}
+
 /* vmv.s.x vd, rs1 # vd[0] = rs1 */
 static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
 {
-    if (vext_check_isa_ill(s)) {
-        /* This instruction ignores LMUL and vector register groups */
-        int maxsz = s->vlen >> 3;
-        TCGv_i64 t1;
-        TCGLabel *over = gen_new_label();
+    REQUIRE_RVV;
+    VEXT_CHECK_ISA_ILL(s);
 
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
-        tcg_gen_gvec_dup_imm(SEW64, vreg_ofs(s, a->rd), maxsz, maxsz, 0);
-        if (a->rs1 == 0) {
-            goto done;
-        }
+    /* This instruction ignores LMUL and vector register groups */
+    TCGv_i64 t1;
+    TCGLabel *over = gen_new_label();
 
-        t1 = tcg_temp_new_i64();
-        tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
-        vec_element_storei(s, a->rd, 0, t1);
-        tcg_temp_free_i64(t1);
-    done:
-        gen_set_label(over);
-        return true;
+    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    if (a->rs1 == 0) {
+        goto done;
     }
-    return false;
+
+    t1 = tcg_temp_new_i64();
+    tcg_gen_extu_tl_i64(t1, cpu_gpr[a->rs1]);
+    vec_element_storei(s, a->rd, 0, t1);
+    tcg_temp_free_i64(t1);
+done:
+    gen_set_label(over);
+    return true;
 }
 
 /* Floating-Point Scalar Move Instructions */