diff mbox series

[RFC,38/65] target/riscv: rvv-0.9: integer merge and move instructions

Message ID 20200710104920.13550-39-frank.chang@sifive.com (mailing list archive)
State New, archived
Headers show
Series target/riscv: support vector extension v0.9 | expand

Commit Message

Frank Chang July 10, 2020, 10:48 a.m. UTC 
From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.inc.c | 179 ++++++++++++------------
 1 file changed, 90 insertions(+), 89 deletions(-)
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 89718fdbc7..53c8dce159 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2008,121 +2008,122 @@  GEN_OPIVX_QUAD_WIDEN_TRANS(vqmacc_vx)
 GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccsu_vx)
 GEN_OPIVX_QUAD_WIDEN_TRANS(vqmaccus_vx)
 
+/* Vector Integer Move Instructions */
 static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
 {
-    if (vext_check_isa_ill(s) &&
-        vext_check_reg(s, a->rd, false) &&
-        vext_check_reg(s, a->rs1, false)) {
+    REQUIRE_RVV;
+    VEXT_CHECK_ISA_ILL(s);
+    /* vmv.v.v has rs2 = 0 and vm = 1 */
+    VEXT_CHECK_SSS(s, a->rd, a->rs1, 0, 1, true);
 
-        if (s->vl_eq_vlmax) {
-            tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
-                             vreg_ofs(s, a->rs1),
-                             MAXSZ(s), MAXSZ(s));
-        } else {
-            uint32_t data = 0;
-            data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-            data = FIELD_DP32(data, VDATA, VTA, s->vta);
-            static gen_helper_gvec_2_ptr * const fns[4] = {
-                gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
-                gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
-            };
-            TCGLabel *over = gen_new_label();
-            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    if (s->vl_eq_vlmax) {
+        tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
+                         vreg_ofs(s, a->rs1),
+                         MAXSZ(s), MAXSZ(s));
+    } else {
+        uint32_t data = 0;
+        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);
+        static gen_helper_gvec_2_ptr * const fns[4] = {
+            gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
+            gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
+        };
+        TCGLabel *over = gen_new_label();
+        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 
-            tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
-                               cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
-            gen_set_label(over);
-        }
-        return true;
+        tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
+                           cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+        gen_set_label(over);
     }
-    return false;
+    return true;
 }
 
 typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32);
 static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
 {
-    if (vext_check_isa_ill(s) &&
-        vext_check_reg(s, a->rd, false)) {
-
-        TCGv s1;
-        TCGLabel *over = gen_new_label();
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    REQUIRE_RVV;
+    VEXT_CHECK_ISA_ILL(s);
+    /* vmv.v.x has rs2 = 0 and vm = 1 */
+    VEXT_CHECK_SSS(s, a->rd, a->rs1, 0, 1, false);
 
-        s1 = tcg_temp_new();
-        gen_get_gpr(s1, a->rs1);
+    TCGv s1;
+    TCGLabel *over = gen_new_label();
+    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 
-        if (s->vl_eq_vlmax) {
-            tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
-                                MAXSZ(s), MAXSZ(s), s1);
-        } else {
-            TCGv_i32 desc ;
-            TCGv_i64 s1_i64 = tcg_temp_new_i64();
-            TCGv_ptr dest = tcg_temp_new_ptr();
-            uint32_t data = 0;
-            data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-            data = FIELD_DP32(data, VDATA, VTA, s->vta);
-            static gen_helper_vmv_vx * const fns[4] = {
-                gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
-                gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
-            };
+    s1 = tcg_temp_new();
+    gen_get_gpr(s1, a->rs1);
 
-            tcg_gen_ext_tl_i64(s1_i64, s1);
-            desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-            tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
-            fns[s->sew](dest, s1_i64, cpu_env, desc);
+    if (s->vl_eq_vlmax) {
+        tcg_gen_gvec_dup_tl(s->sew, vreg_ofs(s, a->rd),
+                            MAXSZ(s), MAXSZ(s), s1);
+    } else {
+        TCGv_i32 desc ;
+        TCGv_i64 s1_i64 = tcg_temp_new_i64();
+        TCGv_ptr dest = tcg_temp_new_ptr();
+        uint32_t data = 0;
+        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);
+        static gen_helper_vmv_vx * const fns[4] = {
+            gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
+            gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
+        };
 
-            tcg_temp_free_ptr(dest);
-            tcg_temp_free_i32(desc);
-            tcg_temp_free_i64(s1_i64);
-        }
+        tcg_gen_ext_tl_i64(s1_i64, s1);
+        desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+        tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+        fns[s->sew](dest, s1_i64, cpu_env, desc);
 
-        tcg_temp_free(s1);
-        gen_set_label(over);
-        return true;
+        tcg_temp_free_ptr(dest);
+        tcg_temp_free_i32(desc);
+        tcg_temp_free_i64(s1_i64);
     }
-    return false;
+
+    tcg_temp_free(s1);
+    gen_set_label(over);
+    return true;
 }
 
 static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
 {
-    if (vext_check_isa_ill(s) &&
-        vext_check_reg(s, a->rd, false)) {
+    REQUIRE_RVV;
+    VEXT_CHECK_ISA_ILL(s);
+    /* vmv.v.i has rs2 = 0 and vm = 1 */
+    VEXT_CHECK_SSS(s, a->rd, a->rs1, 0, 1, false);
 
-        int64_t simm = sextract64(a->rs1, 0, 5);
-        if (s->vl_eq_vlmax) {
-            tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
-                                 MAXSZ(s), MAXSZ(s), simm);
-        } else {
-            TCGv_i32 desc;
-            TCGv_i64 s1;
-            TCGv_ptr dest;
-            uint32_t data = 0;
-            data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
-            data = FIELD_DP32(data, VDATA, VTA, s->vta);
-            data = FIELD_DP32(data, VDATA, VMA, s->vma);
-            static gen_helper_vmv_vx * const fns[4] = {
-                gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
-                gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
-            };
-            TCGLabel *over = gen_new_label();
-            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    int64_t simm = sextract64(a->rs1, 0, 5);
+    if (s->vl_eq_vlmax) {
+        tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
+                             MAXSZ(s), MAXSZ(s), simm);
+    } else {
+        TCGv_i32 desc;
+        TCGv_i64 s1;
+        TCGv_ptr dest;
+        uint32_t data = 0;
+        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+        data = FIELD_DP32(data, VDATA, VTA, s->vta);
+        data = FIELD_DP32(data, VDATA, VMA, s->vma);
+        static gen_helper_vmv_vx * const fns[4] = {
+            gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
+            gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
+        };
+        TCGLabel *over = gen_new_label();
+        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
 
-            s1 = tcg_const_i64(simm);
-            dest = tcg_temp_new_ptr();
-            desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
-            tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
-            fns[s->sew](dest, s1, cpu_env, desc);
+        s1 = tcg_const_i64(simm);
+        dest = tcg_temp_new_ptr();
+        desc = tcg_const_i32(simd_desc(0, s->vlen / 8, data));
+        tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, a->rd));
+        fns[s->sew](dest, s1, cpu_env, desc);
 
-            tcg_temp_free_ptr(dest);
-            tcg_temp_free_i32(desc);
-            tcg_temp_free_i64(s1);
-            gen_set_label(over);
-        }
-        return true;
+        tcg_temp_free_ptr(dest);
+        tcg_temp_free_i32(desc);
+        tcg_temp_free_i64(s1);
+        gen_set_label(over);
     }
-    return false;
+    return true;
 }
 
+/* Vector Integer Merge Instructions */
 GEN_OPIVV_TRANS(vmerge_vvm, opivv_vadc_check)
 GEN_OPIVX_TRANS(vmerge_vxm, opivx_vadc_check)
 GEN_OPIVI_TRANS(vmerge_vim, 0, vmerge_vxm, opivx_vadc_check)