diff mbox series

[RFC,61/65] fpu: fix float16 nan check

Message ID	20200710104920.13550-62-frank.chang@sifive.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=OzId=AV=nongnu.org=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6B57320578 From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC 61/65] fpu: fix float16 nan check Date: Fri, 10 Jul 2020 18:49:15 +0800 Message-Id: <20200710104920.13550-62-frank.chang@sifive.com> In-Reply-To: <20200710104920.13550-1-frank.chang@sifive.com> References: <20200710104920.13550-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1041.google.com Precedence: list Cc: Frank Chang <frank.chang@sifive.com>, Chih-Min Chao <chihmin.chao@sifive.com>, =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>, Aurelien Jarno <aurelien@aurel32.net>, Peter Maydell <peter.maydell@linaro.org> Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org>
Series	target/riscv: support vector extension v0.9 \| expand [RFC,00/65] target/riscv: support vector extension v0.9 [RFC,01/65] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion [RFC,02/65] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() [RFC,03/65] target/riscv: fix return value of do_opivx_widen() [RFC,04/65] target/riscv: fix vill bit index in vtype register [RFC,05/65] target/riscv: remove vsll.vi, vsrl.vi, vsra.vi insns from using gvec [RFC,06/65] target/riscv: rvv-0.9: add vcsr register [RFC,07/65] target/riscv: rvv-0.9: add vector context status [RFC,08/65] target/riscv: rvv-0.9: update mstatus_vs by tb_flags [RFC,09/65] target/riscv: rvv-0.9: add vlenb register [RFC,10/65] target/riscv: rvv-0.9: remove MLEN calculations [RFC,11/65] target/riscv: rvv-0.9: add fractional LMUL, VTA and VMA [RFC,12/65] target/riscv: rvv-0.9: update check functions [RFC,13/65] target/riscv: rvv-0.9: configure instructions [RFC,14/65] target/riscv: rvv-0.9: stride load and store instructions [RFC,15/65] target/riscv: rvv-0.9: index load and store instructions [RFC,16/65] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns [RFC,17/65] target/riscv: rvv-0.9: fault-only-first unit stride load [RFC,18/65] target/riscv: rvv-0.9: amo operations [RFC,19/65] target/riscv: rvv-0.9: load/store whole register instructions [RFC,20/65] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns [RFC,21/65] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation [RFC,22/65] target/riscv: rvv-0.9: floating-point square-root instruction [RFC,23/65] target/riscv: rvv-0.9: floating-point classify instructions [RFC,24/65] target/riscv: rvv-0.9: mask population count instruction [RFC,25/65] target/riscv: rvv-0.9: find-first-set mask bit instruction [RFC,26/65] target/riscv: rvv-0.9: set-X-first mask bit instructions [RFC,27/65] target/riscv: rvv-0.9: iota instruction [RFC,28/65] target/riscv: rvv-0.9: element index instruction [RFC,29/65] target/riscv: rvv-0.9: integer scalar move instructions [RFC,30/65] target/riscv: rvv-0.9: floating-point scalar move instructions [RFC,31/65] target/riscv: rvv-0.9: whole register move instructions [RFC,32/65] target/riscv: rvv-0.9: integer extension instructions [RFC,33/65] target/riscv: rvv-0.9: single-width averaging add and subtract instructions [RFC,34/65] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow [RFC,35/65] target/riscv: rvv-0.9: narrowing integer right shift instructions [RFC,36/65] target/riscv: rvv-0.9: widening integer multiply-add instructions [RFC,37/65] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions [RFC,38/65] target/riscv: rvv-0.9: integer merge and move instructions [RFC,39/65] target/riscv: rvv-0.9: single-width saturating add and subtract instructions [RFC,40/65] target/riscv: rvv-0.9: integer comparison instructions [RFC,41/65] target/riscv: rvv-0.9: floating-point compare instructions [RFC,42/65] target/riscv: rvv-0.9: single-width integer reduction instructions [RFC,43/65] target/riscv: rvv-0.9: widening integer reduction instructions [RFC,44/65] target/riscv: rvv-0.9: mask-register logical instructions [RFC,45/65] target/riscv: rvv-0.9: register gather instructions [RFC,46/65] target/riscv: rvv-0.9: slide instructions [RFC,47/65] target/riscv: rvv-0.9: floating-point slide instructions [RFC,48/65] target/riscv: rvv-0.9: narrowing fixed-point clip instructions [RFC,49/65] target/riscv: rvv-0.9: floating-point move instructions [RFC,50/65] target/riscv: rvv-0.9: floating-point/integer type-convert instructions [RFC,51/65] target/riscv: rvv-0.9: single-width floating-point reduction [RFC,52/65] target/riscv: rvv-0.9: widening floating-point reduction instructions [RFC,53/65] target/riscv: rvv-0.9: single-width scaling shift instructions [RFC,54/65] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add [RFC,55/65] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf [RFC,56/65] target/riscv: rvv-0.9: remove integer extract instruction [RFC,57/65] target/riscv: rvv-0.9: floating-point min/max instructions [RFC,58/65] target/riscv: rvv-0.9: widening floating-point/integer type-convert [RFC,59/65] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert [RFC,60/65] softfloat: add fp16 and uint8/int8 interconvert functions [RFC,61/65] fpu: fix float16 nan check [RFC,62/65] fpu: add api to handle alternative sNaN propagation [RFC,63/65] fpu: implement full set compare for fp16 [RFC,64/65] target/riscv: use softfloat lib float16 comparison functions [RFC,65/65] target/riscv: bump to RVV 0.9

Commit Message

Frank Chang July 10, 2020, 10:49 a.m. UTC

From: Chih-Min Chao <chihmin.chao@sifive.com>

      16     15       10         0
       |sign  |  exp  | mantissa |
  qNaN   x      11111   1x_xxxx_xxxx

  The mask should check  exp + msb of mantissa

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 fpu/softfloat-specialize.inc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff mbox series

Patch

diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.inc.c
index 44f5b661f8..fe7a5e79e4 100644
--- a/fpu/softfloat-specialize.inc.c
+++ b/fpu/softfloat-specialize.inc.c
@@ -254,7 +254,7 @@  bool float16_is_quiet_nan(float16 a_, float_status *status)
     if (snan_bit_is_one(status)) {
         return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
     } else {
-        return ((a & ~0x8000) >= 0x7C80);
+        return ((a & ~0x8000) >= 0x7E00);
     }
 #endif
 }
@@ -271,7 +271,7 @@  bool float16_is_signaling_nan(float16 a_, float_status *status)
 #else
     uint16_t a = float16_val(a_);
     if (snan_bit_is_one(status)) {
-        return ((a & ~0x8000) >= 0x7C80);
+        return ((a & ~0x8000) >= 0x7E00);
     } else {
         return (((a >> 9) & 0x3F) == 0x3E) && (a & 0x1FF);
     }