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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.18.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:18:52 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper Date: Wed, 22 Jul 2020 17:15:42 +0800 Message-Id: <20200722091641.8834-20-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x630.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang For floating-point operations, the scalar can be taken from a scalar f register. If FLEN > SEW, the value in the f registers is checked for a valid NaN-boxed value, in which case the least-significant SEW bits of the f register are used, else the canonical NaN value is used. Add helper to generate the correspond NaN-boxed value or the SEW-bit canonical NaN for floating-point operations. Signed-off-by: Frank Chang --- target/riscv/helper.h | 2 ++ target/riscv/vector_helper.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index acc298219d..3cbd66a887 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1150,3 +1150,5 @@ DEF_HELPER_6(vcompress_vm_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_3(narrower_nanbox_fpr, i64, i64, i32, env) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 83e317c500..fb689ab3f9 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3207,6 +3207,38 @@ GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4, clearl) /* *** Vector Float Point Arithmetic Instructions */ + +/* + * For SEW < FLEN, + * if f is not correctly NaN-boxed for SEW bits, + * canonical SEW-bit NaN is returned. + * Otherwise, original f is returned. + */ +static uint64_t narrower_nanbox_fpr(uint64_t f, uint32_t sew, float_status *s) +{ + uint64_t mask = MAKE_64BIT_MASK(sew, 64 - sew); + if ((f & mask) == mask) { + return f; + } else { + switch (sew) { + case 16: + return float16_default_nan(s); + case 32: + return float32_default_nan(s); + case 64: + return float64_default_nan(s); + default: + g_assert_not_reached(); + } + } +} + +uint64_t HELPER(narrower_nanbox_fpr)(uint64_t f, uint32_t sew, + CPURISCVState *env) +{ + return narrower_nanbox_fpr(f, sew, &env->fp_status); +} + /* Vector Single-Width Floating-Point Add/Subtract Instructions */ #define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \