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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id c125sm22301879pfa.119.2020.07.22.02.21.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2020 02:21:25 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 54/76] target/riscv: rvv-0.9: floating-point compare instructions Date: Wed, 22 Jul 2020 17:16:17 +0800 Message-Id: <20200722091641.8834-55-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x42b.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Clear tail elements only if VTA is agnostic. Signed-off-by: Frank Chang --- target/riscv/vector_helper.c | 52 ++++++++++++++++++++---------------- 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 95cce063d0..8dccec4e04 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4174,27 +4174,30 @@ GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4, clearl) GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq) /* Vector Floating-Point Compare Instructions */ -#define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP) \ -void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t vm = vext_vm(desc); \ - uint32_t vl = env->vl; \ - uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ - uint32_t i; \ - \ - for (i = 0; i < vl; i++) { \ - ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ - ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ - if (!vm && !vext_elem_mask(v0, i)) { \ - continue; \ - } \ - vext_set_elem_mask(vd, i, \ - DO_OP(s2, s1, &env->fp_status)); \ - } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ - } \ +#define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \ + uint32_t vta = vext_vta(desc); \ + uint32_t i; \ + \ + for (i = 0; i < vl; i++) { \ + ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ + ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ + if (!vm && !vext_elem_mask(v0, i)) { \ + continue; \ + } \ + vext_set_elem_mask(vd, i, \ + DO_OP(s2, s1, &env->fp_status)); \ + } \ + if (vta == 1) { \ + for (; i < vlmax; i++) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ + } \ } GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet) @@ -4208,6 +4211,7 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ uint32_t vm = vext_vm(desc); \ uint32_t vl = env->vl; \ uint32_t vlmax = vext_max_elems(desc, sizeof(ETYPE), false); \ + uint32_t vta = vext_vta(desc); \ uint32_t i; \ \ for (i = 0; i < vl; i++) { \ @@ -4218,8 +4222,10 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ vext_set_elem_mask(vd, i, \ DO_OP(s2, (ETYPE)s1, &env->fp_status)); \ } \ - for (; i < vlmax; i++) { \ - vext_set_elem_mask(vd, i, 0); \ + if (vta == 1) { \ + for (; i < vlmax; i++) { \ + vext_set_elem_mask(vd, i, 1); \ + } \ } \ }