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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id f18sm6567309pgv.84.2020.08.06.03.48.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2020 03:48:39 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v3 32/71] target/riscv: rvv-1.0: set-X-first mask bit instructions Date: Thu, 6 Aug 2020 18:46:29 +0800 Message-Id: <20200806104709.13235-33-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200806104709.13235-1-frank.chang@sifive.com> References: <20200806104709.13235-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/insn32.decode | 6 +++--- target/riscv/insn_trans/trans_rvv.inc.c | 5 ++++- target/riscv/vector_helper.c | 4 ---- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index d72120cfd85..0992d6ac86d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -593,9 +593,9 @@ vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r vpopc_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm -vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm -vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm -vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm +vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm +vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm +vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c index 3b781252df0..62c6b469364 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2955,7 +2955,10 @@ static bool trans_vfirst_m(DisasContext *s, arg_rmr *a) #define GEN_M_TRANS(NAME) \ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ - if (vext_check_isa_ill(s)) { \ + if (require_rvv(s) && \ + vext_check_isa_ill(s) && \ + require_vm(a->vm, a->rd) && \ + (a->rd != a->rs2)) { \ uint32_t data = 0; \ gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \ TCGLabel *over = gen_new_label(); \ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 52902b680d7..13ce6f33a9e 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4511,7 +4511,6 @@ enum set_mask_type { static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, uint32_t desc, enum set_mask_type type) { - uint32_t vlmax = env_archcpu(env)->cfg.vlen; uint32_t vm = vext_vm(desc); uint32_t vl = env->vl; int i; @@ -4541,9 +4540,6 @@ static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, } } } - for (; i < vlmax; i++) { - vext_set_elem_mask(vd, i, 0); - } } void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,