@@ -213,7 +213,6 @@ static uint32_t pflash_devid_query(PFlashCFI01 *pfl, hwaddr offset)
default:
trace_pflash_device_info(offset);
return 0;
- break;
}
/* Replicate responses for each device in bank. */
if (pfl->device_width < pfl->bank_width) {
@@ -1637,7 +1637,6 @@ static int cirrus_vga_read_cr(CirrusVGAState * s, unsigned reg_index)
return s->vga.cr[s->vga.cr_index];
case 0x26: // Attribute Controller Index Readback (R)
return s->vga.ar_index & 0x3f;
- break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"cirrus: inport cr_index 0x%02x\n", reg_index);
@@ -161,7 +161,6 @@ static int qxl_log_cmd_draw(PCIQXLDevice *qxl, QXLDrawable *draw, int group_id)
switch (draw->type) {
case QXL_DRAW_COPY:
return qxl_log_cmd_draw_copy(qxl, &draw->u.copy, group_id);
- break;
}
return 0;
}
@@ -180,7 +179,6 @@ static int qxl_log_cmd_draw_compat(PCIQXLDevice *qxl, QXLCompatDrawable *draw,
switch (draw->type) {
case QXL_DRAW_COPY:
return qxl_log_cmd_draw_copy(qxl, &draw->u.copy, group_id);
- break;
}
return 0;
}
@@ -51,11 +51,9 @@ static uint8_t max7310_rx(I2CSlave *i2c)
switch (s->command) {
case 0x00: /* Input port */
return s->level ^ s->polarity;
- break;
case 0x01: /* Output port */
return s->level & ~s->direction;
- break;
case 0x02: /* Polarity inversion */
return s->polarity;
@@ -65,7 +63,6 @@ static uint8_t max7310_rx(I2CSlave *i2c)
case 0x04: /* Timeout */
return s->status;
- break;
case 0xff: /* Reserved */
return 0xff;
@@ -3168,7 +3168,6 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
index, entry->irte.sid_vtype);
/* Take this as verification failure. */
return -VTD_FR_IR_SID_ERR;
- break;
}
}
@@ -192,10 +192,8 @@ static uint64_t pxa2xx_keypad_read(void *opaque, hwaddr offset,
s->kpc &= ~(KPC_DI);
qemu_irq_lower(s->irq);
return tmp;
- break;
case KPDK:
return s->kpdk;
- break;
case KPREC:
tmp = s->kprec;
if(tmp & KPREC_OF1)
@@ -207,31 +205,23 @@ static uint64_t pxa2xx_keypad_read(void *opaque, hwaddr offset,
if(tmp & KPREC_UF0)
s->kprec &= ~(KPREC_UF0);
return tmp;
- break;
case KPMK:
tmp = s->kpmk;
if(tmp & KPMK_MKP)
s->kpmk &= ~(KPMK_MKP);
return tmp;
- break;
case KPAS:
return s->kpas;
- break;
case KPASMKP0:
return s->kpasmkp[0];
- break;
case KPASMKP1:
return s->kpasmkp[1];
- break;
case KPASMKP2:
return s->kpasmkp[2];
- break;
case KPASMKP3:
return s->kpasmkp[3];
- break;
case KPKDI:
return s->kpkdi;
- break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
@@ -1290,7 +1290,6 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
case 0xd90: /* MPU_TYPE */
/* Unified MPU; if the MPU is not present this value is zero */
return cpu->pmsav7_dregion << 8;
- break;
case 0xd94: /* MPU_CTRL */
return cpu->env.v7m.mpu_ctrl[attrs.secure];
case 0xd98: /* MPU_RNR */
@@ -931,10 +931,8 @@ static uint32_t do_mac_read(lan9118_state *s, int reg)
| (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24);
case MAC_HASHH:
return s->mac_hashh;
- break;
case MAC_HASHL:
return s->mac_hashl;
- break;
case MAC_MII_ACC:
return s->mac_mii_acc;
case MAC_MII_DATA:
@@ -350,7 +350,6 @@ static void *event_thread(void *arg)
case VEVENT_LAST: /* quit */
vevent_delete(event);
return NULL;
- break;
default:
break;
}