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Thu, 03 Sep 2020 18:07:50 +0200 From: Helge Deller To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 02/10] hw/hppa: Make number of TLB and BTLB entries configurable Date: Thu, 3 Sep 2020 18:07:38 +0200 Message-Id: <20200903160746.27491-3-deller@gmx.de> X-Mailer: git-send-email 2.21.3 In-Reply-To: <20200903160746.27491-1-deller@gmx.de> References: <20200903160746.27491-1-deller@gmx.de> MIME-Version: 1.0 X-Provags-ID: V03:K1:iB8h5gi8tl0fVeIS1JY1XRWwQfA1kd7ZOufl1NKc8AgCG67iYzI fDPlqMJ3G0qTVr+6Ts0vP1BPQ67bva4aqzqiKp6K2uXusC+IHm/xV5wKcWvfvWWSSdH7qbb +ENODaQZ0ednydBfPOXIJFp5v9vLKX57mFkaBeyrWZTQAV26Tn3CX+AOq3I64EfvsWmX/9J byNcYAFPForKgWSuRhnWg== X-UI-Out-Filterresults: notjunk:1;V03:K0:W2E1ejVb5Wc=:Ynb22IXx3pMKbcwAWnLGn2 lke3/YKV866iCvPyugTrhaavHO8ZzWXI+rEzucKp+8YYz0ji8SCuPIMB7BhBmBSsbV7LQrhTv xS2pTf7tio/lZ6JtRWW2gSQ4h3W9Xtwf5ZO4IEeEy/xtJaySb2Ql8KwJ7l6wL+GhttpSyUhL4 y/YoBTG77v9XHGkVZnqu8x4EVMddX2oqlx2rxSVNW0xfxQt+PjtHwZBUlIE9Lyg84XdGOf+AM gxiJrFb/ONy1pGvKyt7W/RpuxyZ9fUmcRv5dnJXhiJWzVxLbXE3DeRnSEjHE+Prpo2qVtbfHT cm1OMRjTEgoKWGiXu4kYv6D1KlJpSbGCFpknkn7uQZtYrbGvDfOzNdSjDwz+K1A53+b46EDWx NMScTvg3SnW8mlS2pVKC+5yXVjCDaawcwgTzm6Y+wneBX9Pva92rWhr5jsTJPc9iySf2DRH3P Bw9I7TThwZlYliK/oLw5CXcqF0wO8vJ8IfIB+/aBCSjjrX6XUK3CjaX8PY7/q8aOBuPNdeg+0 zpYPCczRIxEhEyw71YPQU+rk0c61RI3ZpOHB2mUVf30VhnV4wjr2cYVRl8nMw6ATHqdKVN7N5 0VtNlIg+fprBMToK9j4SRWxGDiE0a3xiw5hl0E1tsC/4AoimrCDOdbrk1YX+unmvZVYrplsyn /NQClELKkIi1jYWPBJlpGenG2QFqWxPmmz1nVvpMnMKMR9XYpsWzSKBe+5C4wxIQGXdOZ8IO/ wzcOhE/Wc9h0uYWOXpTwbeQASIl3Hd86AexqobjlqmUjfnIgbC+AubVCj4lQuMPmTYukb+n0R loUMZUgEX6w83hnQDyWf5WJzl8lJDnyBWZ0QvAj+FshiLTN5z52XSEIffhzhIzmUA+FndqwJQ ec+hXQeqNvF5f3vrze3e1+eFxQrsO3LEeacXSvpHAoMXqKS1G2A6jEPGWfIje+twqDogOY1jo Oexo9BrWJYL2vxy6iIKKL0yqAb8oMI+x/W8mGB3Du+a0deR/qeRtqAFIqufIX/7PG/3W/PqGV fhES+vnJi+XNdaCzioyit9YeLMKaG5oOVdGSuscuJ2bE5ZXyI38cD3zhOHdT5L8suYlCrUDfb wpFuJhNFGjVzszIyv03goDY2b1zmrGNIu/nNlD7e0zHeG+/IaIn0uhRvUAQOHA1mQHBoX3/BQ NkRoEr3+uNaVEdFKeT7j9MSbambMJitJZUVqMfkWqLM4b5lCkG67r4b/+s1j32BxwW0PGQrxb 6U9wBzyT5tdYiyDtp Received-SPF: pass client-ip=212.227.17.21; envelope-from=deller@gmx.de; helo=mout.gmx.net X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/03 12:08:05 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Helge Deller , Richard Henderson Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Until now the TLB size was fixed at 256 entries. To allow operating systems to utilize more TLB entries in the future, we need to tell firmware how many TLB entries we actually support in the emulation. Firmware then reports this to the operating system via the PDC_CACHE_INFO call. This patch simply does the preparation to allow more TLB entries. Signed-off-by: Helge Deller --- hw/hppa/machine.c | 8 ++++++++ target/hppa/cpu.h | 5 ++++- 2 files changed, 12 insertions(+), 1 deletion(-) -- 2.21.3 diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 90aeefe2a4..e9d84d0f03 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -72,6 +72,14 @@ static FWCfgState *create_fw_cfg(MachineState *ms) fw_cfg_add_file(fw_cfg, "/etc/firmware-min-version", g_memdup(&val, sizeof(val)), sizeof(val)); + val = cpu_to_le64(HPPA_TLB_ENTRIES); + fw_cfg_add_file(fw_cfg, "/etc/cpu/tlb_entries", + g_memdup(&val, sizeof(val)), sizeof(val)); + + val = cpu_to_le64(HPPA_BTLB_ENTRIES); + fw_cfg_add_file(fw_cfg, "/etc/cpu/btlb_entries", + g_memdup(&val, sizeof(val)), sizeof(val)); + return fw_cfg; } diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 801a4fb1ba..fb6c59d075 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -196,9 +196,12 @@ struct CPUHPPAState { target_ureg shadow[7]; /* shadow registers */ /* ??? The number of entries isn't specified by the architecture. */ +#define HPPA_TLB_ENTRIES 256 +#define HPPA_BTLB_ENTRIES 0 + /* ??? Implement a unified itlb/dtlb for the moment. */ /* ??? We should use a more intelligent data structure. */ - hppa_tlb_entry tlb[256]; + hppa_tlb_entry tlb[HPPA_TLB_ENTRIES]; uint32_t tlb_last; };