From patchwork Fri Sep 25 10:17:27 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luc Michel X-Patchwork-Id: 11799481 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 465E6618 for ; Fri, 25 Sep 2020 10:21:57 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E6DD621D91 for ; Fri, 25 Sep 2020 10:21:56 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=lmichel.fr header.i=@lmichel.fr header.b="G2msWkse" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E6DD621D91 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=lmichel.fr Authentication-Results: mail.kernel.org; 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t=1601029040; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YOuCNbOOvSsStZNfbQT6hnxWhxzA58znlB/MmjZ2y5Y=; b=G2msWksehXz8+B/Ovvn/E5LRViL4pvyLW1sALYAcTxj/PZimXJtVomTYV9Soz80kz0jWpl 99USxdF3nWyh7ZQbcdPxoP0X6sPmeNkiDtJBAt2Iygu17s62FX2v7wMxk0TIJEhPc41y/e hhTG7Rhr5hI1f683WUkbsLJoYChY87cpEcAtM/xn5kR3rtJM/FYSmBVSwNCKoRszooNlBH 7mFE+lUzE4sRlAIvS0HGD6NOd+fkjASL3r48PXvcU4jhaRSu1Gt48zkzuW0FjopmBN4Gtn qd/rw6q2AWoOWVlVAdo38mcs4Xkw8LeU3eDLDJuqnFvlJcbNqnXGlzldoR0Luw== From: Luc Michel To: qemu-devel@nongnu.org Subject: [PATCH 10/14] hw/misc/bcm2835_cprman: implement clock mux behaviour Date: Fri, 25 Sep 2020 12:17:27 +0200 Message-Id: <20200925101731.2159827-11-luc@lmichel.fr> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200925101731.2159827-1-luc@lmichel.fr> References: <20200925101731.2159827-1-luc@lmichel.fr> MIME-Version: 1.0 ARC-Message-Signature: i=1; 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pharaoh.lmichel.fr Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/25 06:17:20 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" A clock mux can be configured to select one of its 10 sources through the cm_ctl register. It also embeds yet another clock divider, composed of an integer part and a fractionnal part. The number of bits of each part is mux dependant. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé --- hw/misc/bcm2835_cprman.c | 43 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index 8df2db0fd9..75bc11939b 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -229,19 +229,60 @@ static const TypeInfo cprman_pll_channel_info = { }; /* clock mux */ +static bool clock_mux_is_enabled(CprmanClockMuxState *mux) +{ + return FIELD_EX32(*mux->reg_cm, CM_CLOCKx_CTL, ENABLE); +} + static void clock_mux_update(CprmanClockMuxState *mux) { - clock_update(mux->out, 0); + uint64_t freq, div; + uint32_t src = FIELD_EX32(*mux->reg_cm, CM_CLOCKx_CTL, SRC); + bool enabled = clock_mux_is_enabled(mux); + + *mux->reg_cm = FIELD_DP32(*mux->reg_cm, CM_CLOCKx_CTL, BUSY, enabled); + + if (!enabled) { + clock_update(mux->out, 0); + return; + } + + freq = clock_get_hz(mux->srcs[src]); + + if (mux->int_bits == 0 && mux->frac_bits == 0) { + clock_update_hz(mux->out, freq); + return; + } + + /* + * The divider has an integer and a fractional part. The size of each part + * varies with the muxes (int_bits and frac_bits). Both parts are + * concatenated, with the integer part always starting at bit 12. + */ + div = mux->reg_cm[1] >> (R_CM_CLOCKx_DIV_FRAC_LENGTH - mux->frac_bits); + div &= (1 << (mux->int_bits + mux->frac_bits)) - 1; + + freq = (freq << mux->frac_bits) / div; + + clock_update_hz(mux->out, freq); } static void clock_mux_src_update(void *opaque) { CprmanClockMuxState **backref = opaque; CprmanClockMuxState *s = *backref; + CprmanClockMuxSource src = backref - s->backref; + uint32_t current_src; + + current_src = FIELD_EX32(*s->reg_cm, CM_CLOCKx_CTL, SRC); + + if (current_src != src) { + return; + } clock_mux_update(s); } static void clock_mux_init(Object *obj)