From patchwork Fri Sep 25 10:17:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luc Michel X-Patchwork-Id: 11799475 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 335DA112E for ; Fri, 25 Sep 2020 10:20:04 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6A7D021775 for ; Fri, 25 Sep 2020 10:20:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=lmichel.fr header.i=@lmichel.fr header.b="bQh+xYff" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6A7D021775 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=lmichel.fr Authentication-Results: mail.kernel.org; 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t=1601029040; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FcBIzmQAZtEmj8qCZRpqLApGyCCP0+6Pwhqm+5t6clU=; b=bQh+xYffT7DzsX3tbkSjp6Whl4VXzh71EhhJjvDnZ6MR7F6aT/RYhphYo7IGk2Pq2ULAHf JW0GZkNLT8vn7SHIMVkTgvt8uoYAEC1i3jMGNHnWRWERguzHZCP2za1hmiG7F5PRf6Enxy 2S3l+W82/8VM0XqihegViKe/i+BrCBCvo3D5jIRJEcXve6Cjf7kPurWAcfAd+ocestfSlS r/nLRimb7+c2aBJao2FQ7cxZO+OOiHGS4iDUOJQd71AoYoOPpdut5+hUy6CRmaAZtPhFmH iG8MdWHfFIW+D6B+bH9bDe5Q+o757jriRGk5nHL4NJ6mmkuJjzJC87i+mZlFag== From: Luc Michel To: qemu-devel@nongnu.org Subject: [PATCH 06/14] hw/misc/bcm2835_cprman: implement PLLs behaviour Date: Fri, 25 Sep 2020 12:17:23 +0200 Message-Id: <20200925101731.2159827-7-luc@lmichel.fr> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200925101731.2159827-1-luc@lmichel.fr> References: <20200925101731.2159827-1-luc@lmichel.fr> MIME-Version: 1.0 ARC-Message-Signature: i=1; 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pharaoh.lmichel.fr Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/25 06:17:20 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" The cprman PLLs generate a clock based on a prescaler, a multiplier and a divider. The prescaler doubles the parent (xosc) frequency, then the multiplier/divider are applied. The multiplier has an integer and a fractionnal part. This commit also implements the cprman CM_LOCK register. This register reports which PLL is currently locked. We consider a PLL has being locked as soon as it is enabled (on real hardware, there is a delay after turning a PLL on, for it to stabilise). Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daudé --- include/hw/misc/bcm2835_cprman_internals.h | 8 +++ hw/misc/bcm2835_cprman.c | 64 +++++++++++++++++++++- 2 files changed, 71 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/bcm2835_cprman_internals.h index 5cfa849492..22a2500ab0 100644 --- a/include/hw/misc/bcm2835_cprman_internals.h +++ b/include/hw/misc/bcm2835_cprman_internals.h @@ -98,10 +98,18 @@ REG32(A2W_PLLA_FRAC, 0x1200) REG32(A2W_PLLC_FRAC, 0x1220) REG32(A2W_PLLD_FRAC, 0x1240) REG32(A2W_PLLH_FRAC, 0x1260) REG32(A2W_PLLB_FRAC, 0x12e0) +/* misc registers */ +REG32(CM_LOCK, 0x114) + FIELD(CM_LOCK, FLOCKH, 12, 1) + FIELD(CM_LOCK, FLOCKD, 11, 1) + FIELD(CM_LOCK, FLOCKC, 10, 1) + FIELD(CM_LOCK, FLOCKB, 9, 1) + FIELD(CM_LOCK, FLOCKA, 8, 1) + /* * This field is common to all registers. Each register write value must match * the CPRMAN_PASSWORD magic value in its 8 MSB. */ FIELD(CPRMAN, PASSWORD, 24, 8) diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index ad71d30a86..ba82522eb1 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -48,13 +48,51 @@ #include "hw/misc/bcm2835_cprman_internals.h" #include "trace.h" /* PLL */ +static bool pll_is_locked(const CprmanPLLState *pll) +{ + return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN) + && !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST); +} + static void pll_update(CprmanPLLState *pll) { - clock_update(pll->out, 0); + uint64_t freq, ndiv, fdiv, pdiv; + + if (!pll_is_locked(pll)) { + clock_update(pll->out, 0); + return; + } + + pdiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV); + + if (!pdiv) { + clock_update(pll->out, 0); + return; + } + + ndiv = FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, NDIV); + fdiv = FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC); + + if (pll->reg_a2w_ana[1] & pll->prediv_mask) { + /* The prescaler doubles the parent frequency */ + ndiv *= 2; + fdiv *= 2; + } + + /* + * We have a multiplier with an integer part (ndiv) and a fractional part + * (fdiv), and a divider (pdiv). + */ + freq = clock_get_hz(pll->xosc_in) * + ((ndiv << R_A2W_PLLx_FRAC_FRAC_LENGTH) + fdiv); + freq /= pdiv; + freq >>= R_A2W_PLLx_FRAC_FRAC_LENGTH; + + clock_update_hz(pll->out, freq); } static void pll_xosc_update(void *opaque) { pll_update(CPRMAN_PLL(opaque)); @@ -94,18 +132,42 @@ static const TypeInfo cprman_pll_info = { }; /* CPRMAN "top level" model */ +static uint32_t get_cm_lock(const BCM2835CprmanState *s) +{ + static const int CM_LOCK_MAPPING[] = { + [CPRMAN_PLLA] = R_CM_LOCK_FLOCKA_SHIFT, + [CPRMAN_PLLC] = R_CM_LOCK_FLOCKC_SHIFT, + [CPRMAN_PLLD] = R_CM_LOCK_FLOCKD_SHIFT, + [CPRMAN_PLLH] = R_CM_LOCK_FLOCKH_SHIFT, + [CPRMAN_PLLB] = R_CM_LOCK_FLOCKB_SHIFT, + }; + + uint32_t r = 0; + size_t i; + + for (i = 0; i < CPRMAN_NUM_PLL; i++) { + r |= pll_is_locked(&s->plls[i]) << CM_LOCK_MAPPING[i]; + } + + return r; +} + static uint64_t cprman_read(void *opaque, hwaddr offset, unsigned size) { BCM2835CprmanState *s = CPRMAN(opaque); uint64_t r = 0; size_t idx = offset / sizeof(uint32_t); switch (idx) { + case R_CM_LOCK: + r = get_cm_lock(s); + break; + default: r = s->regs[idx]; } trace_bcm2835_cprman_read(offset, r);