@@ -1,11 +1 @@
/* List of comma-separated changed AML files to ignore */
-"tests/data/acpi/q35/DSDT",
-"tests/data/acpi/q35/DSDT.acpihmat",
-"tests/data/acpi/q35/DSDT.bridge",
-"tests/data/acpi/q35/DSDT.cphp",
-"tests/data/acpi/q35/DSDT.dimmpxm",
-"tests/data/acpi/q35/DSDT.ipmibt",
-"tests/data/acpi/q35/DSDT.memhp",
-"tests/data/acpi/q35/DSDT.mmio64",
-"tests/data/acpi/q35/DSDT.numamem",
-"tests/data/acpi/q35/DSDT.tis",
new file mode 100644
@@ -0,0 +1,198 @@
+/* AUTOMATICALLY GENERATED, DO NOT MODIFY */
+
+/*
+ * schema-defined QAPI event functions
+ *
+ * Copyright (c) 2014 Wenchao Xia
+ *
+ * Authors:
+ * Wenchao Xia <wenchaoqemu@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
+ * See the COPYING.LIB file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "test-qapi-event.h"
+#include "test-qapi-visit.h"
+#include "qapi/qmp-output-visitor.h"
+#include "qapi/qmp-event.h"
+
+
+void qapi_event_send_event_a(Error **errp)
+{
+ QDict *qmp;
+ Error *err = NULL;
+ QMPEventFuncEmit emit;
+
+ emit = qmp_event_get_func_emit();
+ if (!emit) {
+ return;
+ }
+
+ qmp = qmp_event_build_dict("EVENT_A");
+
+ emit(TEST_QAPI_EVENT_EVENT_A, qmp, &err);
+
+ error_propagate(errp, err);
+ QDECREF(qmp);
+}
+
+void qapi_event_send_event_b(Error **errp)
+{
+ QDict *qmp;
+ Error *err = NULL;
+ QMPEventFuncEmit emit;
+
+ emit = qmp_event_get_func_emit();
+ if (!emit) {
+ return;
+ }
+
+ qmp = qmp_event_build_dict("EVENT_B");
+
+ emit(TEST_QAPI_EVENT_EVENT_B, qmp, &err);
+
+ error_propagate(errp, err);
+ QDECREF(qmp);
+}
+
+void qapi_event_send_event_c(bool has_a, int64_t a, bool has_b, UserDefOne *b, const char *c, Error **errp)
+{
+ QDict *qmp;
+ Error *err = NULL;
+ QMPEventFuncEmit emit;
+ QmpOutputVisitor *qov;
+ Visitor *v;
+ q_obj_EVENT_C_arg param = {
+ has_a, a, has_b, b, (char *)c
+ };
+
+ emit = qmp_event_get_func_emit();
+ if (!emit) {
+ return;
+ }
+
+ qmp = qmp_event_build_dict("EVENT_C");
+
+ qov = qmp_output_visitor_new();
+ v = qmp_output_get_visitor(qov);
+
+ visit_start_struct(v, "EVENT_C", NULL, 0, &err);
+ if (err) {
+ goto out;
+ }
+ visit_type_q_obj_EVENT_C_arg_members(v, ¶m, &err);
+ if (!err) {
+ visit_check_struct(v, &err);
+ }
+ visit_end_struct(v);
+ if (err) {
+ goto out;
+ }
+
+ qdict_put_obj(qmp, "data", qmp_output_get_qobject(qov));
+ emit(TEST_QAPI_EVENT_EVENT_C, qmp, &err);
+
+out:
+ qmp_output_visitor_cleanup(qov);
+ error_propagate(errp, err);
+ QDECREF(qmp);
+}
+
+void qapi_event_send_event_d(EventStructOne *a, const char *b, bool has_c, const char *c, bool has_enum3, EnumOne enum3, Error **errp)
+{
+ QDict *qmp;
+ Error *err = NULL;
+ QMPEventFuncEmit emit;
+ QmpOutputVisitor *qov;
+ Visitor *v;
+ q_obj_EVENT_D_arg param = {
+ a, (char *)b, has_c, (char *)c, has_enum3, enum3
+ };
+
+ emit = qmp_event_get_func_emit();
+ if (!emit) {
+ return;
+ }
+
+ qmp = qmp_event_build_dict("EVENT_D");
+
+ qov = qmp_output_visitor_new();
+ v = qmp_output_get_visitor(qov);
+
+ visit_start_struct(v, "EVENT_D", NULL, 0, &err);
+ if (err) {
+ goto out;
+ }
+ visit_type_q_obj_EVENT_D_arg_members(v, ¶m, &err);
+ if (!err) {
+ visit_check_struct(v, &err);
+ }
+ visit_end_struct(v);
+ if (err) {
+ goto out;
+ }
+
+ qdict_put_obj(qmp, "data", qmp_output_get_qobject(qov));
+ emit(TEST_QAPI_EVENT_EVENT_D, qmp, &err);
+
+out:
+ qmp_output_visitor_cleanup(qov);
+ error_propagate(errp, err);
+ QDECREF(qmp);
+}
+
+void qapi_event_send___org_qemu_x_event(__org_qemu_x_Enum __org_qemu_x_member1, const char *__org_qemu_x_member2, bool has_q_wchar_t, int64_t q_wchar_t, Error **errp)
+{
+ QDict *qmp;
+ Error *err = NULL;
+ QMPEventFuncEmit emit;
+ QmpOutputVisitor *qov;
+ Visitor *v;
+ __org_qemu_x_Struct param = {
+ __org_qemu_x_member1, (char *)__org_qemu_x_member2, has_q_wchar_t, q_wchar_t
+ };
+
+ emit = qmp_event_get_func_emit();
+ if (!emit) {
+ return;
+ }
+
+ qmp = qmp_event_build_dict("__ORG.QEMU_X-EVENT");
+
+ qov = qmp_output_visitor_new();
+ v = qmp_output_get_visitor(qov);
+
+ visit_start_struct(v, "__ORG.QEMU_X-EVENT", NULL, 0, &err);
+ if (err) {
+ goto out;
+ }
+ visit_type___org_qemu_x_Struct_members(v, ¶m, &err);
+ if (!err) {
+ visit_check_struct(v, &err);
+ }
+ visit_end_struct(v);
+ if (err) {
+ goto out;
+ }
+
+ qdict_put_obj(qmp, "data", qmp_output_get_qobject(qov));
+ emit(TEST_QAPI_EVENT___ORG_QEMU_X_EVENT, qmp, &err);
+
+out:
+ qmp_output_visitor_cleanup(qov);
+ error_propagate(errp, err);
+ QDECREF(qmp);
+}
+
+const char *const test_QAPIEvent_lookup[] = {
+ [TEST_QAPI_EVENT_EVENT_A] = "EVENT_A",
+ [TEST_QAPI_EVENT_EVENT_B] = "EVENT_B",
+ [TEST_QAPI_EVENT_EVENT_C] = "EVENT_C",
+ [TEST_QAPI_EVENT_EVENT_D] = "EVENT_D",
+ [TEST_QAPI_EVENT___ORG_QEMU_X_EVENT] = "__ORG.QEMU_X-EVENT",
+ [TEST_QAPI_EVENT__MAX] = NULL,
+};
new file mode 100644
@@ -0,0 +1,58 @@
+/* AUTOMATICALLY GENERATED, DO NOT MODIFY */
+
+/*
+ * QAPI/QMP schema introspection
+ *
+ * Copyright (C) 2015 Red Hat, Inc.
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
+ * See the COPYING.LIB file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "test-qmp-introspect.h"
+
+const char test_qmp_schema_json[] = "["
+ "{\"arg-type\": \"0\", \"meta-type\": \"event\", \"name\": \"EVENT_A\"}, "
+ "{\"arg-type\": \"0\", \"meta-type\": \"event\", \"name\": \"EVENT_B\"}, "
+ "{\"arg-type\": \"1\", \"meta-type\": \"event\", \"name\": \"EVENT_C\"}, "
+ "{\"arg-type\": \"2\", \"meta-type\": \"event\", \"name\": \"EVENT_D\"}, "
+ "{\"arg-type\": \"3\", \"meta-type\": \"event\", \"name\": \"__ORG.QEMU_X-EVENT\"}, "
+ "{\"arg-type\": \"4\", \"meta-type\": \"command\", \"name\": \"__org.qemu_x-command\", \"ret-type\": \"5\"}, "
+ "{\"arg-type\": \"6\", \"meta-type\": \"command\", \"name\": \"guest-get-time\", \"ret-type\": \"int\"}, "
+ "{\"arg-type\": \"7\", \"meta-type\": \"command\", \"name\": \"guest-sync\", \"ret-type\": \"any\"}, "
+ "{\"arg-type\": \"0\", \"meta-type\": \"command\", \"name\": \"user_def_cmd\", \"ret-type\": \"0\"}, "
+ "{\"arg-type\": \"8\", \"meta-type\": \"command\", \"name\": \"user_def_cmd0\", \"ret-type\": \"8\"}, "
+ "{\"arg-type\": \"9\", \"meta-type\": \"command\", \"name\": \"user_def_cmd1\", \"ret-type\": \"0\"}, "
+ "{\"arg-type\": \"10\", \"meta-type\": \"command\", \"name\": \"user_def_cmd2\", \"ret-type\": \"11\"}, "
+ "{\"members\": [], \"meta-type\": \"object\", \"name\": \"0\"}, "
+ "{\"members\": [{\"default\": null, \"name\": \"a\", \"type\": \"int\"}, {\"default\": null, \"name\": \"b\", \"type\": \"12\"}, {\"name\": \"c\", \"type\": \"str\"}], \"meta-type\": \"object\", \"name\": \"1\"}, "
+ "{\"members\": [{\"name\": \"a\", \"type\": \"13\"}, {\"name\": \"b\", \"type\": \"str\"}, {\"default\": null, \"name\": \"c\", \"type\": \"str\"}, {\"default\": null, \"name\": \"enum3\", \"type\": \"14\"}], \"meta-type\": \"object\", \"name\": \"2\"}, "
+ "{\"members\": [{\"name\": \"__org.qemu_x-member1\", \"type\": \"15\"}, {\"name\": \"__org.qemu_x-member2\", \"type\": \"str\"}, {\"default\": null, \"name\": \"wchar-t\", \"type\": \"int\"}], \"meta-type\": \"object\", \"name\": \"3\"}, "
+ "{\"members\": [{\"name\": \"a\", \"type\": \"[15]\"}, {\"name\": \"b\", \"type\": \"[3]\"}, {\"name\": \"c\", \"type\": \"16\"}, {\"name\": \"d\", \"type\": \"17\"}], \"meta-type\": \"object\", \"name\": \"4\"}, "
+ "{\"members\": [{\"name\": \"type\", \"type\": \"18\"}], \"meta-type\": \"object\", \"name\": \"5\", \"tag\": \"type\", \"variants\": [{\"case\": \"__org.qemu_x-branch\", \"type\": \"19\"}]}, "
+ "{\"members\": [{\"name\": \"a\", \"type\": \"int\"}, {\"default\": null, \"name\": \"b\", \"type\": \"int\"}], \"meta-type\": \"object\", \"name\": \"6\"}, "
+ "{\"json-type\": \"int\", \"meta-type\": \"builtin\", \"name\": \"int\"}, "
+ "{\"members\": [{\"name\": \"arg\", \"type\": \"any\"}], \"meta-type\": \"object\", \"name\": \"7\"}, "
+ "{\"json-type\": \"value\", \"meta-type\": \"builtin\", \"name\": \"any\"}, "
+ "{\"members\": [], \"meta-type\": \"object\", \"name\": \"8\"}, "
+ "{\"members\": [{\"name\": \"ud1a\", \"type\": \"12\"}], \"meta-type\": \"object\", \"name\": \"9\"}, "
+ "{\"members\": [{\"name\": \"ud1a\", \"type\": \"12\"}, {\"default\": null, \"name\": \"ud1b\", \"type\": \"12\"}], \"meta-type\": \"object\", \"name\": \"10\"}, "
+ "{\"members\": [{\"name\": \"string0\", \"type\": \"str\"}, {\"name\": \"dict1\", \"type\": \"20\"}], \"meta-type\": \"object\", \"name\": \"11\"}, "
+ "{\"members\": [{\"name\": \"integer\", \"type\": \"int\"}, {\"name\": \"string\", \"type\": \"str\"}, {\"default\": null, \"name\": \"enum1\", \"type\": \"14\"}], \"meta-type\": \"object\", \"name\": \"12\"}, "
+ "{\"json-type\": \"string\", \"meta-type\": \"builtin\", \"name\": \"str\"}, "
+ "{\"members\": [{\"name\": \"struct1\", \"type\": \"12\"}, {\"name\": \"string\", \"type\": \"str\"}, {\"default\": null, \"name\": \"enum2\", \"type\": \"14\"}], \"meta-type\": \"object\", \"name\": \"13\"}, "
+ "{\"meta-type\": \"enum\", \"name\": \"14\", \"values\": [\"value1\", \"value2\", \"value3\"]}, "
+ "{\"meta-type\": \"enum\", \"name\": \"15\", \"values\": [\"__org.qemu_x-value\"]}, "
+ "{\"element-type\": \"15\", \"meta-type\": \"array\", \"name\": \"[15]\"}, "
+ "{\"element-type\": \"3\", \"meta-type\": \"array\", \"name\": \"[3]\"}, "
+ "{\"members\": [{\"name\": \"__org.qemu_x-member1\", \"type\": \"15\"}], \"meta-type\": \"object\", \"name\": \"16\", \"tag\": \"__org.qemu_x-member1\", \"variants\": [{\"case\": \"__org.qemu_x-value\", \"type\": \"21\"}]}, "
+ "{\"members\": [{\"type\": \"str\"}, {\"type\": \"22\"}], \"meta-type\": \"alternate\", \"name\": \"17\"}, "
+ "{\"meta-type\": \"enum\", \"name\": \"18\", \"values\": [\"__org.qemu_x-branch\"]}, "
+ "{\"members\": [{\"name\": \"data\", \"type\": \"str\"}], \"meta-type\": \"object\", \"name\": \"19\"}, "
+ "{\"members\": [{\"name\": \"string1\", \"type\": \"str\"}, {\"name\": \"dict2\", \"type\": \"23\"}, {\"default\": null, \"name\": \"dict3\", \"type\": \"23\"}], \"meta-type\": \"object\", \"name\": \"20\"}, "
+ "{\"members\": [{\"name\": \"array\", \"type\": \"[5]\"}], \"meta-type\": \"object\", \"name\": \"21\"}, "
+ "{\"members\": [{\"name\": \"__org.qemu_x-member1\", \"type\": \"15\"}], \"meta-type\": \"object\", \"name\": \"22\"}, "
+ "{\"members\": [{\"name\": \"userdef\", \"type\": \"12\"}, {\"name\": \"string\", \"type\": \"str\"}], \"meta-type\": \"object\", \"name\": \"23\"}, "
+ "{\"element-type\": \"5\", \"meta-type\": \"array\", \"name\": \"[5]\"}]";
new file mode 100644
@@ -0,0 +1,383 @@
+/* AUTOMATICALLY GENERATED, DO NOT MODIFY */
+
+/*
+ * schema-defined QMP->QAPI command dispatch
+ *
+ * Copyright IBM, Corp. 2011
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
+ * See the COPYING.LIB file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "qemu/module.h"
+#include "qapi/qmp/types.h"
+#include "qapi/qmp/dispatch.h"
+#include "qapi/visitor.h"
+#include "qapi/qmp-output-visitor.h"
+#include "qapi/qmp-input-visitor.h"
+#include "qapi/dealloc-visitor.h"
+#include "test-qapi-types.h"
+#include "test-qapi-visit.h"
+#include "test-qmp-commands.h"
+
+
+static void qmp_marshal_output___org_qemu_x_Union1(__org_qemu_x_Union1 *ret_in, QObject **ret_out, Error **errp)
+{
+ Error *err = NULL;
+ QmpOutputVisitor *qov = qmp_output_visitor_new();
+ QapiDeallocVisitor *qdv;
+ Visitor *v;
+
+ v = qmp_output_get_visitor(qov);
+ visit_type___org_qemu_x_Union1(v, "unused", &ret_in, &err);
+ if (err) {
+ goto out;
+ }
+ *ret_out = qmp_output_get_qobject(qov);
+
+out:
+ error_propagate(errp, err);
+ qmp_output_visitor_cleanup(qov);
+ qdv = qapi_dealloc_visitor_new();
+ v = qapi_dealloc_get_visitor(qdv);
+ visit_type___org_qemu_x_Union1(v, "unused", &ret_in, NULL);
+ qapi_dealloc_visitor_cleanup(qdv);
+}
+
+static void qmp_marshal___org_qemu_x_command(QDict *args, QObject **ret, Error **errp)
+{
+ Error *err = NULL;
+ __org_qemu_x_Union1 *retval;
+ QmpInputVisitor *qiv = qmp_input_visitor_new(QOBJECT(args), true);
+ QapiDeallocVisitor *qdv;
+ Visitor *v;
+ q_obj___org_qemu_x_command_arg arg = {0};
+
+ v = qmp_input_get_visitor(qiv);
+ visit_start_struct(v, NULL, NULL, 0, &err);
+ if (err) {
+ goto out;
+ }
+ visit_type_q_obj___org_qemu_x_command_arg_members(v, &arg, &err);
+ if (!err) {
+ visit_check_struct(v, &err);
+ }
+ visit_end_struct(v);
+ if (err) {
+ goto out;
+ }
+
+ retval = qmp___org_qemu_x_command(arg.a, arg.b, arg.c, arg.d, &err);
+ if (err) {
+ goto out;
+ }
+
+ qmp_marshal_output___org_qemu_x_Union1(retval, ret, &err);
+
+out:
+ error_propagate(errp, err);
+ qmp_input_visitor_cleanup(qiv);
+ qdv = qapi_dealloc_visitor_new();
+ v = qapi_dealloc_get_visitor(qdv);
+ visit_start_struct(v, NULL, NULL, 0, NULL);
+ visit_type_q_obj___org_qemu_x_command_arg_members(v, &arg, NULL);
+ visit_end_struct(v);
+ qapi_dealloc_visitor_cleanup(qdv);
+}
+
+static void qmp_marshal_output_int(int64_t ret_in, QObject **ret_out, Error **errp)
+{
+ Error *err = NULL;
+ QmpOutputVisitor *qov = qmp_output_visitor_new();
+ QapiDeallocVisitor *qdv;
+ Visitor *v;
+
+ v = qmp_output_get_visitor(qov);
+ visit_type_int(v, "unused", &ret_in, &err);
+ if (err) {
+ goto out;
+ }
+ *ret_out = qmp_output_get_qobject(qov);
+
+out:
+ error_propagate(errp, err);
+ qmp_output_visitor_cleanup(qov);
+ qdv = qapi_dealloc_visitor_new();
+ v = qapi_dealloc_get_visitor(qdv);
+ visit_type_int(v, "unused", &ret_in, NULL);
+ qapi_dealloc_visitor_cleanup(qdv);
+}
+
+static void qmp_marshal_guest_get_time(QDict *args, QObject **ret, Error **errp)
+{
+ Error *err = NULL;
+ int64_t retval;
+ QmpInputVisitor *qiv = qmp_input_visitor_new(QOBJECT(args), true);
+ QapiDeallocVisitor *qdv;
+ Visitor *v;
+ q_obj_guest_get_time_arg arg = {0};
+
+ v = qmp_input_get_visitor(qiv);
+ visit_start_struct(v, NULL, NULL, 0, &err);
+ if (err) {
+ goto out;
+ }
+ visit_type_q_obj_guest_get_time_arg_members(v, &arg, &err);
+ if (!err) {
+ visit_check_struct(v, &err);
+ }
+ visit_end_struct(v);
+ if (err) {
+ goto out;
+ }
+
+ retval = qmp_guest_get_time(arg.a, arg.has_b, arg.b, &err);
+ if (err) {
+ goto out;
+ }
+
+ qmp_marshal_output_int(retval, ret, &err);
+
+out:
+ error_propagate(errp, err);
+ qmp_input_visitor_cleanup(qiv);
+ qdv = qapi_dealloc_visitor_new();
+ v = qapi_dealloc_get_visitor(qdv);
+ visit_start_struct(v, NULL, NULL, 0, NULL);
+ visit_type_q_obj_guest_get_time_arg_members(v, &arg, NULL);
+ visit_end_struct(v);
+ qapi_dealloc_visitor_cleanup(qdv);
+}
+
+static void qmp_marshal_output_any(QObject *ret_in, QObject **ret_out, Error **errp)
+{
+ Error *err = NULL;
+ QmpOutputVisitor *qov = qmp_output_visitor_new();
+ QapiDeallocVisitor *qdv;
+ Visitor *v;
+
+ v = qmp_output_get_visitor(qov);
+ visit_type_any(v, "unused", &ret_in, &err);
+ if (err) {
+ goto out;
+ }
+ *ret_out = qmp_output_get_qobject(qov);
+
+out:
+ error_propagate(errp, err);
+ qmp_output_visitor_cleanup(qov);
+ qdv = qapi_dealloc_visitor_new();
+ v = qapi_dealloc_get_visitor(qdv);
+ visit_type_any(v, "unused", &ret_in, NULL);
+ qapi_dealloc_visitor_cleanup(qdv);
+}
+
+static void qmp_marshal_guest_sync(QDict *args, QObject **ret, Error **errp)
+{
+ Error *err = NULL;
+ QObject *retval;
+ QmpInputVisitor *qiv = qmp_input_visitor_new(QOBJECT(args), true);
+ QapiDeallocVisitor *qdv;
+ Visitor *v;
+ q_obj_guest_sync_arg arg = {0};
+
+ v = qmp_input_get_visitor(qiv);
+ visit_start_struct(v, NULL, NULL, 0, &err);
+ if (err) {
+ goto out;
+ }
+ visit_type_q_obj_guest_sync_arg_members(v, &arg, &err);
+ if (!err) {
+ visit_check_struct(v, &err);
+ }
+ visit_end_struct(v);
+ if (err) {
+ goto out;
+ }
+
+ retval = qmp_guest_sync(arg.arg, &err);
+ if (err) {
+ goto out;
+ }
+
+ qmp_marshal_output_any(retval, ret, &err);
+
+out:
+ error_propagate(errp, err);
+ qmp_input_visitor_cleanup(qiv);
+ qdv = qapi_dealloc_visitor_new();
+ v = qapi_dealloc_get_visitor(qdv);
+ visit_start_struct(v, NULL, NULL, 0, NULL);
+ visit_type_q_obj_guest_sync_arg_members(v, &arg, NULL);
+ visit_end_struct(v);
+ qapi_dealloc_visitor_cleanup(qdv);
+}
+
+static void qmp_marshal_user_def_cmd(QDict *args, QObject **ret, Error **errp)
+{
+ Error *err = NULL;
+
+ (void)args;
+
+ qmp_user_def_cmd(&err);
+ error_propagate(errp, err);
+}
+
+static void qmp_marshal_output_Empty2(Empty2 *ret_in, QObject **ret_out, Error **errp)
+{
+ Error *err = NULL;
+ QmpOutputVisitor *qov = qmp_output_visitor_new();
+ QapiDeallocVisitor *qdv;
+ Visitor *v;
+
+ v = qmp_output_get_visitor(qov);
+ visit_type_Empty2(v, "unused", &ret_in, &err);
+ if (err) {
+ goto out;
+ }
+ *ret_out = qmp_output_get_qobject(qov);
+
+out:
+ error_propagate(errp, err);
+ qmp_output_visitor_cleanup(qov);
+ qdv = qapi_dealloc_visitor_new();
+ v = qapi_dealloc_get_visitor(qdv);
+ visit_type_Empty2(v, "unused", &ret_in, NULL);
+ qapi_dealloc_visitor_cleanup(qdv);
+}
+
+static void qmp_marshal_user_def_cmd0(QDict *args, QObject **ret, Error **errp)
+{
+ Error *err = NULL;
+ Empty2 *retval;
+
+ (void)args;
+
+ retval = qmp_user_def_cmd0(&err);
+ if (err) {
+ goto out;
+ }
+
+ qmp_marshal_output_Empty2(retval, ret, &err);
+
+out:
+ error_propagate(errp, err);
+}
+
+static void qmp_marshal_user_def_cmd1(QDict *args, QObject **ret, Error **errp)
+{
+ Error *err = NULL;
+ QmpInputVisitor *qiv = qmp_input_visitor_new(QOBJECT(args), true);
+ QapiDeallocVisitor *qdv;
+ Visitor *v;
+ q_obj_user_def_cmd1_arg arg = {0};
+
+ v = qmp_input_get_visitor(qiv);
+ visit_start_struct(v, NULL, NULL, 0, &err);
+ if (err) {
+ goto out;
+ }
+ visit_type_q_obj_user_def_cmd1_arg_members(v, &arg, &err);
+ if (!err) {
+ visit_check_struct(v, &err);
+ }
+ visit_end_struct(v);
+ if (err) {
+ goto out;
+ }
+
+ qmp_user_def_cmd1(arg.ud1a, &err);
+
+out:
+ error_propagate(errp, err);
+ qmp_input_visitor_cleanup(qiv);
+ qdv = qapi_dealloc_visitor_new();
+ v = qapi_dealloc_get_visitor(qdv);
+ visit_start_struct(v, NULL, NULL, 0, NULL);
+ visit_type_q_obj_user_def_cmd1_arg_members(v, &arg, NULL);
+ visit_end_struct(v);
+ qapi_dealloc_visitor_cleanup(qdv);
+}
+
+static void qmp_marshal_output_UserDefTwo(UserDefTwo *ret_in, QObject **ret_out, Error **errp)
+{
+ Error *err = NULL;
+ QmpOutputVisitor *qov = qmp_output_visitor_new();
+ QapiDeallocVisitor *qdv;
+ Visitor *v;
+
+ v = qmp_output_get_visitor(qov);
+ visit_type_UserDefTwo(v, "unused", &ret_in, &err);
+ if (err) {
+ goto out;
+ }
+ *ret_out = qmp_output_get_qobject(qov);
+
+out:
+ error_propagate(errp, err);
+ qmp_output_visitor_cleanup(qov);
+ qdv = qapi_dealloc_visitor_new();
+ v = qapi_dealloc_get_visitor(qdv);
+ visit_type_UserDefTwo(v, "unused", &ret_in, NULL);
+ qapi_dealloc_visitor_cleanup(qdv);
+}
+
+static void qmp_marshal_user_def_cmd2(QDict *args, QObject **ret, Error **errp)
+{
+ Error *err = NULL;
+ UserDefTwo *retval;
+ QmpInputVisitor *qiv = qmp_input_visitor_new(QOBJECT(args), true);
+ QapiDeallocVisitor *qdv;
+ Visitor *v;
+ q_obj_user_def_cmd2_arg arg = {0};
+
+ v = qmp_input_get_visitor(qiv);
+ visit_start_struct(v, NULL, NULL, 0, &err);
+ if (err) {
+ goto out;
+ }
+ visit_type_q_obj_user_def_cmd2_arg_members(v, &arg, &err);
+ if (!err) {
+ visit_check_struct(v, &err);
+ }
+ visit_end_struct(v);
+ if (err) {
+ goto out;
+ }
+
+ retval = qmp_user_def_cmd2(arg.ud1a, arg.has_ud1b, arg.ud1b, &err);
+ if (err) {
+ goto out;
+ }
+
+ qmp_marshal_output_UserDefTwo(retval, ret, &err);
+
+out:
+ error_propagate(errp, err);
+ qmp_input_visitor_cleanup(qiv);
+ qdv = qapi_dealloc_visitor_new();
+ v = qapi_dealloc_get_visitor(qdv);
+ visit_start_struct(v, NULL, NULL, 0, NULL);
+ visit_type_q_obj_user_def_cmd2_arg_members(v, &arg, NULL);
+ visit_end_struct(v);
+ qapi_dealloc_visitor_cleanup(qdv);
+}
+
+static void qmp_init_marshal(void)
+{
+ qmp_register_command("__org.qemu_x-command", qmp_marshal___org_qemu_x_command, QCO_NO_OPTIONS);
+ qmp_register_command("guest-get-time", qmp_marshal_guest_get_time, QCO_NO_OPTIONS);
+ qmp_register_command("guest-sync", qmp_marshal_guest_sync, QCO_NO_OPTIONS);
+ qmp_register_command("user_def_cmd", qmp_marshal_user_def_cmd, QCO_NO_OPTIONS);
+ qmp_register_command("user_def_cmd0", qmp_marshal_user_def_cmd0, QCO_NO_OPTIONS);
+ qmp_register_command("user_def_cmd1", qmp_marshal_user_def_cmd1, QCO_NO_OPTIONS);
+ qmp_register_command("user_def_cmd2", qmp_marshal_user_def_cmd2, QCO_NO_OPTIONS);
+}
+
+qapi_init(qmp_init_marshal);
new file mode 100644
GIT binary patch
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HcmV?d00001
new file mode 100644
@@ -0,0 +1,1012 @@
+
+.PHONY: check-help
+check-help:
+ @echo "Regression testing targets:"
+ @echo
+ @echo " $(MAKE) check Run all tests"
+ @echo " $(MAKE) check-qtest-TARGET Run qtest tests for given target"
+ @echo " $(MAKE) check-qtest Run qtest tests"
+ @echo " $(MAKE) check-unit Run qobject tests"
+ @echo " $(MAKE) check-speed Run qobject speed tests"
+ @echo " $(MAKE) check-qapi-schema Run QAPI schema tests"
+ @echo " $(MAKE) check-block Run block tests"
+ @echo " $(MAKE) check-tcg Run TCG tests"
+ @echo " $(MAKE) check-acceptance Run all acceptance (functional) tests"
+ @echo " $(MAKE) check-report.html Generates an HTML test report"
+ @echo " $(MAKE) check-venv Creates a Python venv for tests"
+ @echo " $(MAKE) check-clean Clean the tests"
+ @echo
+ @echo "Please note that HTML reports do not regenerate if the unit tests"
+ @echo "has not changed."
+ @echo
+ @echo "The variable SPEED can be set to control the gtester speed setting."
+ @echo "Default options are -k and (for $(MAKE) V=1) --verbose; they can be"
+ @echo "changed with variable GTESTER_OPTIONS."
+
+ifneq ($(wildcard config-host.mak),)
+export SRC_PATH
+
+# TODO don't duplicate $(SRC_PATH)/Makefile's qapi-py here
+qapi-py = $(SRC_PATH)/scripts/qapi/commands.py \
+$(SRC_PATH)/scripts/qapi/events.py \
+$(SRC_PATH)/scripts/qapi/introspect.py \
+$(SRC_PATH)/scripts/qapi/types.py \
+$(SRC_PATH)/scripts/qapi/visit.py \
+$(SRC_PATH)/scripts/qapi/common.py \
+$(SRC_PATH)/scripts/qapi/doc.py \
+$(SRC_PATH)/scripts/qapi-gen.py
+
+# Get the list of all supported sysemu targets
+SYSEMU_TARGET_LIST := $(subst -softmmu.mak,,$(notdir \
+ $(wildcard $(SRC_PATH)/default-configs/*-softmmu.mak)))
+
+check-unit-y += tests/check-qdict$(EXESUF)
+check-unit-y += tests/check-block-qdict$(EXESUF)
+check-unit-y += tests/test-char$(EXESUF)
+check-unit-y += tests/check-qnum$(EXESUF)
+check-unit-y += tests/check-qstring$(EXESUF)
+check-unit-y += tests/check-qlist$(EXESUF)
+check-unit-y += tests/check-qnull$(EXESUF)
+check-unit-y += tests/check-qobject$(EXESUF)
+check-unit-y += tests/check-qjson$(EXESUF)
+check-unit-y += tests/check-qlit$(EXESUF)
+check-unit-y += tests/test-qobject-output-visitor$(EXESUF)
+check-unit-y += tests/test-clone-visitor$(EXESUF)
+check-unit-y += tests/test-qobject-input-visitor$(EXESUF)
+check-unit-y += tests/test-qmp-cmds$(EXESUF)
+check-unit-y += tests/test-string-input-visitor$(EXESUF)
+check-unit-y += tests/test-string-output-visitor$(EXESUF)
+check-unit-y += tests/test-qmp-event$(EXESUF)
+check-unit-y += tests/test-opts-visitor$(EXESUF)
+check-unit-y += tests/test-coroutine$(EXESUF)
+check-unit-y += tests/test-visitor-serialization$(EXESUF)
+check-unit-y += tests/test-iov$(EXESUF)
+check-unit-y += tests/test-aio$(EXESUF)
+check-unit-y += tests/test-aio-multithread$(EXESUF)
+check-unit-y += tests/test-throttle$(EXESUF)
+check-unit-y += tests/test-thread-pool$(EXESUF)
+check-unit-y += tests/test-hbitmap$(EXESUF)
+check-unit-y += tests/test-bdrv-drain$(EXESUF)
+check-unit-y += tests/test-blockjob$(EXESUF)
+check-unit-y += tests/test-blockjob-txn$(EXESUF)
+check-unit-y += tests/test-block-backend$(EXESUF)
+check-unit-y += tests/test-image-locking$(EXESUF)
+check-unit-y += tests/test-x86-cpuid$(EXESUF)
+# all code tested by test-x86-cpuid is inside topology.h
+ifeq ($(CONFIG_SOFTMMU),y)
+check-unit-y += tests/test-xbzrle$(EXESUF)
+check-unit-$(CONFIG_POSIX) += tests/test-vmstate$(EXESUF)
+endif
+check-unit-y += tests/test-cutils$(EXESUF)
+check-unit-y += tests/test-shift128$(EXESUF)
+check-unit-y += tests/test-mul64$(EXESUF)
+check-unit-y += tests/test-int128$(EXESUF)
+# all code tested by test-int128 is inside int128.h
+check-unit-y += tests/rcutorture$(EXESUF)
+check-unit-y += tests/test-rcu-list$(EXESUF)
+check-unit-y += tests/test-rcu-simpleq$(EXESUF)
+check-unit-y += tests/test-rcu-tailq$(EXESUF)
+check-unit-y += tests/test-qdist$(EXESUF)
+check-unit-y += tests/test-qht$(EXESUF)
+# FIXME: {test-qht-par + gprof} often break on Travis CI
+check-unit-$(call lnot,$(CONFIG_GPROF)) += tests/test-qht-par$(EXESUF)
+check-unit-y += tests/test-bitops$(EXESUF)
+check-unit-y += tests/test-bitcnt$(EXESUF)
+check-unit-y += tests/test-qdev-global-props$(EXESUF)
+check-unit-y += tests/check-qom-interface$(EXESUF)
+check-unit-y += tests/check-qom-proplist$(EXESUF)
+check-unit-y += tests/test-qemu-opts$(EXESUF)
+check-unit-y += tests/test-keyval$(EXESUF)
+check-unit-y += tests/test-write-threshold$(EXESUF)
+check-unit-y += tests/test-crypto-hash$(EXESUF)
+check-speed-y += tests/benchmark-crypto-hash$(EXESUF)
+check-unit-y += tests/test-crypto-hmac$(EXESUF)
+check-speed-y += tests/benchmark-crypto-hmac$(EXESUF)
+check-unit-y += tests/test-crypto-cipher$(EXESUF)
+check-speed-y += tests/benchmark-crypto-cipher$(EXESUF)
+check-unit-y += tests/test-crypto-secret$(EXESUF)
+check-unit-$(CONFIG_GNUTLS) += tests/test-crypto-tlscredsx509$(EXESUF)
+check-unit-$(CONFIG_GNUTLS) += tests/test-crypto-tlssession$(EXESUF)
+ifneq (,$(findstring qemu-ga,$(TOOLS)))
+check-unit-$(CONFIG_LINUX) += tests/test-qga$(EXESUF)
+endif
+check-unit-y += tests/test-timed-average$(EXESUF)
+check-unit-y += tests/test-util-sockets$(EXESUF)
+check-unit-y += tests/test-io-task$(EXESUF)
+check-unit-y += tests/test-io-channel-socket$(EXESUF)
+check-unit-y += tests/test-io-channel-file$(EXESUF)
+check-unit-$(CONFIG_GNUTLS) += tests/test-io-channel-tls$(EXESUF)
+check-unit-y += tests/test-io-channel-command$(EXESUF)
+check-unit-y += tests/test-io-channel-buffer$(EXESUF)
+check-unit-y += tests/test-base64$(EXESUF)
+check-unit-$(if $(CONFIG_NETTLE),y,$(CONFIG_GCRYPT)) += tests/test-crypto-pbkdf$(EXESUF)
+check-unit-y += tests/test-crypto-ivgen$(EXESUF)
+check-unit-y += tests/test-crypto-afsplit$(EXESUF)
+check-unit-y += tests/test-crypto-xts$(EXESUF)
+check-unit-y += tests/test-crypto-block$(EXESUF)
+check-unit-y += tests/test-logging$(EXESUF)
+check-unit-$(CONFIG_REPLICATION) += tests/test-replication$(EXESUF)
+check-unit-y += tests/test-bufferiszero$(EXESUF)
+check-unit-y += tests/test-uuid$(EXESUF)
+check-unit-y += tests/ptimer-test$(EXESUF)
+check-unit-y += tests/test-qapi-util$(EXESUF)
+
+check-block-$(CONFIG_POSIX) += tests/qemu-iotests-quick.sh
+
+# All QTests for now are POSIX-only, but the dependencies are
+# really in libqtest, not in the testcases themselves.
+
+check-qtest-generic-y += tests/qmp-test$(EXESUF)
+check-qtest-generic-y += tests/qmp-cmd-test$(EXESUF)
+
+check-qtest-generic-y += tests/device-introspect-test$(EXESUF)
+check-qtest-generic-y += tests/cdrom-test$(EXESUF)
+
+check-qtest-ipack-y += tests/ipoctal232-test$(EXESUF)
+
+check-qtest-virtioserial-y += tests/virtio-console-test$(EXESUF)
+
+check-qtest-virtio-y += tests/virtio-net-test$(EXESUF)
+check-qtest-virtio-$(CONFIG_VIRTIO_BALLOON) += tests/virtio-balloon-test$(EXESUF)
+check-qtest-virtio-y += tests/virtio-blk-test$(EXESUF)
+check-qtest-virtio-$(CONFIG_VIRTIO_RNG) += tests/virtio-rng-test$(EXESUF)
+check-qtest-virtio-$(CONFIG_VIRTIO_SCSI) += tests/virtio-scsi-test$(EXESUF)
+ifeq ($(CONFIG_VIRTIO)$(CONFIG_VIRTFS)$(CONFIG_PCI),yyy)
+check-qtest-virtio-$(CONFIG_VIRTIO_9P) += tests/virtio-9p-test$(EXESUF)
+endif
+check-qtest-virtio-y += tests/virtio-serial-test$(EXESUF)
+check-qtest-virtio-y += $(check-qtest-virtioserial-y)
+
+check-qtest-pci-y += tests/e1000-test$(EXESUF)
+check-qtest-pci-y += tests/e1000e-test$(EXESUF)
+check-qtest-pci-$(CONFIG_RTL8139_PCI) += tests/rtl8139-test$(EXESUF)
+check-qtest-pci-$(CONFIG_PCNET_PCI) += tests/pcnet-test$(EXESUF)
+check-qtest-pci-$(CONFIG_EEPRO100_PCI) += tests/eepro100-test$(EXESUF)
+check-qtest-pci-$(CONFIG_NE2000_PCI) += tests/ne2000-test$(EXESUF)
+check-qtest-pci-$(CONFIG_NVME_PCI) += tests/nvme-test$(EXESUF)
+check-qtest-pci-$(CONFIG_AC97) += tests/ac97-test$(EXESUF)
+check-qtest-pci-$(CONFIG_ES1370) += tests/es1370-test$(EXESUF)
+check-qtest-pci-y += $(check-qtest-virtio-y)
+check-qtest-pci-$(CONFIG_IPACK) += tests/tpci200-test$(EXESUF)
+check-qtest-pci-$(CONFIG_IPACK) += $(check-qtest-ipack-y)
+check-qtest-pci-y += tests/display-vga-test$(EXESUF)
+check-qtest-pci-$(CONFIG_HDA) += tests/intel-hda-test$(EXESUF)
+check-qtest-pci-$(CONFIG_IVSHMEM_DEVICE) += tests/ivshmem-test$(EXESUF)
+check-qtest-pci-y += tests/megasas-test$(EXESUF)
+
+check-qtest-i386-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF)
+check-qtest-i386-y += tests/fdc-test$(EXESUF)
+check-qtest-i386-y += tests/ide-test$(EXESUF)
+check-qtest-i386-y += tests/ahci-test$(EXESUF)
+check-qtest-i386-y += tests/hd-geo-test$(EXESUF)
+check-qtest-i386-y += tests/boot-order-test$(EXESUF)
+check-qtest-i386-y += tests/bios-tables-test$(EXESUF)
+check-qtest-i386-$(CONFIG_SGA) += tests/boot-serial-test$(EXESUF)
+check-qtest-i386-$(CONFIG_SLIRP) += tests/pxe-test$(EXESUF)
+check-qtest-i386-y += tests/rtc-test$(EXESUF)
+check-qtest-i386-y += tests/ipmi-kcs-test$(EXESUF)
+check-qtest-i386-y += tests/ipmi-bt-test$(EXESUF)
+check-qtest-i386-y += tests/i440fx-test$(EXESUF)
+check-qtest-i386-y += tests/fw_cfg-test$(EXESUF)
+check-qtest-i386-y += tests/drive_del-test$(EXESUF)
+check-qtest-i386-$(CONFIG_WDT_IB700) += tests/wdt_ib700-test$(EXESUF)
+check-qtest-i386-y += tests/tco-test$(EXESUF)
+check-qtest-i386-y += $(check-qtest-pci-y)
+check-qtest-i386-$(CONFIG_VMXNET3_PCI) += tests/vmxnet3-test$(EXESUF)
+check-qtest-i386-$(CONFIG_PVPANIC) += tests/pvpanic-test$(EXESUF)
+check-qtest-i386-$(CONFIG_I82801B11) += tests/i82801b11-test$(EXESUF)
+check-qtest-i386-$(CONFIG_IOH3420) += tests/ioh3420-test$(EXESUF)
+check-qtest-i386-$(CONFIG_USB_OHCI) += tests/usb-hcd-ohci-test$(EXESUF)
+check-qtest-i386-$(CONFIG_USB_UHCI) += tests/usb-hcd-uhci-test$(EXESUF)
+ifeq ($(CONFIG_USB_ECHI)$(CONFIG_USB_UHCI),yy)
+check-qtest-i386-y += tests/usb-hcd-ehci-test$(EXESUF)
+endif
+check-qtest-i386-$(CONFIG_USB_XHCI_NEC) += tests/usb-hcd-xhci-test$(EXESUF)
+check-qtest-i386-y += tests/cpu-plug-test$(EXESUF)
+check-qtest-i386-y += tests/q35-test$(EXESUF)
+check-qtest-i386-y += tests/vmgenid-test$(EXESUF)
+check-qtest-i386-$(CONFIG_VHOST_USER_NET_TEST_i386) += tests/vhost-user-test$(EXESUF)
+ifeq ($(CONFIG_VHOST_USER_NET_TEST_i386),)
+check-qtest-x86_64-$(CONFIG_VHOST_USER_NET_TEST_x86_64) += tests/vhost-user-test$(EXESUF)
+endif
+check-qtest-i386-$(CONFIG_TPM_CRB) += tests/tpm-crb-swtpm-test$(EXESUF)
+check-qtest-i386-$(CONFIG_TPM_CRB) += tests/tpm-crb-test$(EXESUF)
+check-qtest-i386-$(CONFIG_TPM_TIS) += tests/tpm-tis-swtpm-test$(EXESUF)
+check-qtest-i386-$(CONFIG_TPM_TIS) += tests/tpm-tis-test$(EXESUF)
+check-qtest-i386-$(CONFIG_SLIRP) += tests/test-netfilter$(EXESUF)
+check-qtest-i386-$(CONFIG_POSIX) += tests/test-filter-mirror$(EXESUF)
+check-qtest-i386-$(CONFIG_RTL8139_PCI) += tests/test-filter-redirector$(EXESUF)
+check-qtest-i386-y += tests/migration-test$(EXESUF)
+check-qtest-i386-y += tests/test-x86-cpuid-compat$(EXESUF)
+check-qtest-i386-y += tests/numa-test$(EXESUF)
+check-qtest-x86_64-y += $(check-qtest-i386-y)
+check-qtest-x86_64-$(CONFIG_SDHCI) += tests/sdhci-test$(EXESUF)
+
+check-qtest-alpha-y += tests/boot-serial-test$(EXESUF)
+check-qtest-alpha-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF)
+
+check-qtest-hppa-y += tests/boot-serial-test$(EXESUF)
+check-qtest-hppa-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF)
+
+check-qtest-m68k-y = tests/boot-serial-test$(EXESUF)
+
+check-qtest-microblaze-y += tests/boot-serial-test$(EXESUF)
+
+check-qtest-mips-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF)
+check-qtest-mips-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF)
+
+check-qtest-mips64-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF)
+check-qtest-mips64-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF)
+
+check-qtest-mips64el-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF)
+check-qtest-mips64el-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF)
+
+check-qtest-moxie-y += tests/boot-serial-test$(EXESUF)
+
+check-qtest-ppc-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF)
+check-qtest-ppc-y += tests/boot-order-test$(EXESUF)
+check-qtest-ppc-y += tests/prom-env-test$(EXESUF)
+check-qtest-ppc-y += tests/drive_del-test$(EXESUF)
+check-qtest-ppc-y += tests/boot-serial-test$(EXESUF)
+check-qtest-ppc-y += tests/m48t59-test$(EXESUF)
+
+check-qtest-ppc64-y += $(check-qtest-ppc-y)
+check-qtest-ppc64-y += tests/spapr-phb-test$(EXESUF)
+check-qtest-ppc64-y += tests/pnv-xscom-test$(EXESUF)
+check-qtest-ppc64-y += tests/migration-test$(EXESUF)
+check-qtest-ppc64-y += tests/rtas-test$(EXESUF)
+check-qtest-ppc64-$(CONFIG_SLIRP) += tests/pxe-test$(EXESUF)
+check-qtest-ppc64-$(CONFIG_USB_OHCI) += tests/usb-hcd-ohci-test$(EXESUF)
+check-qtest-ppc64-$(CONFIG_USB_UHCI) += tests/usb-hcd-uhci-test$(EXESUF)
+check-qtest-ppc64-$(CONFIG_USB_XHCI_NEC) += tests/usb-hcd-xhci-test$(EXESUF)
+check-qtest-ppc64-y += $(check-qtest-virtio-y)
+check-qtest-ppc64-$(CONFIG_SLIRP) += tests/test-netfilter$(EXESUF)
+check-qtest-ppc64-$(CONFIG_POSIX) += tests/test-filter-mirror$(EXESUF)
+check-qtest-ppc64-$(CONFIG_RTL8139_PCI) += tests/test-filter-redirector$(EXESUF)
+check-qtest-ppc64-y += tests/display-vga-test$(EXESUF)
+check-qtest-ppc64-y += tests/numa-test$(EXESUF)
+check-qtest-ppc64-$(CONFIG_IVSHMEM_DEVICE) += tests/ivshmem-test$(EXESUF)
+check-qtest-ppc64-y += tests/cpu-plug-test$(EXESUF)
+
+check-qtest-sh4-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF)
+
+check-qtest-sh4eb-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF)
+
+check-qtest-sparc-y += tests/prom-env-test$(EXESUF)
+check-qtest-sparc-y += tests/m48t59-test$(EXESUF)
+check-qtest-sparc-y += tests/boot-serial-test$(EXESUF)
+
+check-qtest-sparc64-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF)
+check-qtest-sparc64-y += tests/prom-env-test$(EXESUF)
+check-qtest-sparc64-y += tests/boot-serial-test$(EXESUF)
+
+check-qtest-arm-y += tests/tmp105-test$(EXESUF)
+check-qtest-arm-y += tests/pca9552-test$(EXESUF)
+check-qtest-arm-y += tests/ds1338-test$(EXESUF)
+check-qtest-arm-y += tests/microbit-test$(EXESUF)
+check-qtest-arm-y += tests/m25p80-test$(EXESUF)
+check-qtest-arm-y += tests/virtio-blk-test$(EXESUF)
+check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF)
+check-qtest-arm-y += tests/boot-serial-test$(EXESUF)
+check-qtest-arm-$(CONFIG_SDHCI) += tests/sdhci-test$(EXESUF)
+check-qtest-arm-y += tests/hexloader-test$(EXESUF)
+
+check-qtest-aarch64-y = tests/numa-test$(EXESUF)
+check-qtest-aarch64-$(CONFIG_SDHCI) += tests/sdhci-test$(EXESUF)
+check-qtest-aarch64-y += tests/boot-serial-test$(EXESUF)
+check-qtest-aarch64-y += tests/migration-test$(EXESUF)
+
+check-qtest-microblazeel-y += $(check-qtest-microblaze-y)
+
+check-qtest-xtensaeb-y += $(check-qtest-xtensa-y)
+
+check-qtest-s390x-y = tests/boot-serial-test$(EXESUF)
+check-qtest-s390x-$(CONFIG_SLIRP) += tests/pxe-test$(EXESUF)
+check-qtest-s390x-$(CONFIG_SLIRP) += tests/test-netfilter$(EXESUF)
+check-qtest-s390x-$(CONFIG_POSIX) += tests/test-filter-mirror$(EXESUF)
+check-qtest-s390x-$(CONFIG_POSIX) += tests/test-filter-redirector$(EXESUF)
+check-qtest-s390x-y += tests/drive_del-test$(EXESUF)
+check-qtest-s390x-y += tests/virtio-ccw-test$(EXESUF)
+check-qtest-s390x-y += tests/cpu-plug-test$(EXESUF)
+check-qtest-s390x-y += tests/migration-test$(EXESUF)
+
+check-qtest-generic-y += tests/machine-none-test$(EXESUF)
+check-qtest-generic-y += tests/qom-test$(EXESUF)
+check-qtest-generic-y += tests/test-hmp$(EXESUF)
+
+qapi-schema += alternate-any.json
+qapi-schema += alternate-array.json
+qapi-schema += alternate-base.json
+qapi-schema += alternate-clash.json
+qapi-schema += alternate-conflict-dict.json
+qapi-schema += alternate-conflict-enum-bool.json
+qapi-schema += alternate-conflict-enum-int.json
+qapi-schema += alternate-conflict-string.json
+qapi-schema += alternate-conflict-bool-string.json
+qapi-schema += alternate-conflict-num-string.json
+qapi-schema += alternate-empty.json
+qapi-schema += alternate-invalid-dict.json
+qapi-schema += alternate-nested.json
+qapi-schema += alternate-unknown.json
+qapi-schema += args-alternate.json
+qapi-schema += args-any.json
+qapi-schema += args-array-empty.json
+qapi-schema += args-array-unknown.json
+qapi-schema += args-bad-boxed.json
+qapi-schema += args-boxed-anon.json
+qapi-schema += args-boxed-empty.json
+qapi-schema += args-boxed-string.json
+qapi-schema += args-int.json
+qapi-schema += args-invalid.json
+qapi-schema += args-member-array-bad.json
+qapi-schema += args-member-case.json
+qapi-schema += args-member-unknown.json
+qapi-schema += args-name-clash.json
+qapi-schema += args-union.json
+qapi-schema += args-unknown.json
+qapi-schema += bad-base.json
+qapi-schema += bad-data.json
+qapi-schema += bad-ident.json
+qapi-schema += bad-if.json
+qapi-schema += bad-if-empty.json
+qapi-schema += bad-if-empty-list.json
+qapi-schema += bad-if-list.json
+qapi-schema += bad-type-bool.json
+qapi-schema += bad-type-dict.json
+qapi-schema += bad-type-int.json
+qapi-schema += base-cycle-direct.json
+qapi-schema += base-cycle-indirect.json
+qapi-schema += command-int.json
+qapi-schema += comments.json
+qapi-schema += doc-bad-alternate-member.json
+qapi-schema += doc-bad-command-arg.json
+qapi-schema += doc-bad-section.json
+qapi-schema += doc-bad-symbol.json
+qapi-schema += doc-bad-union-member.json
+qapi-schema += doc-before-include.json
+qapi-schema += doc-before-pragma.json
+qapi-schema += doc-duplicated-arg.json
+qapi-schema += doc-duplicated-return.json
+qapi-schema += doc-duplicated-since.json
+qapi-schema += doc-empty-arg.json
+qapi-schema += doc-empty-section.json
+qapi-schema += doc-empty-symbol.json
+qapi-schema += doc-good.json
+qapi-schema += doc-interleaved-section.json
+qapi-schema += doc-invalid-end.json
+qapi-schema += doc-invalid-end2.json
+qapi-schema += doc-invalid-return.json
+qapi-schema += doc-invalid-section.json
+qapi-schema += doc-invalid-start.json
+qapi-schema += doc-missing-colon.json
+qapi-schema += doc-missing-expr.json
+qapi-schema += doc-missing-space.json
+qapi-schema += doc-missing.json
+qapi-schema += doc-no-symbol.json
+qapi-schema += double-data.json
+qapi-schema += double-type.json
+qapi-schema += duplicate-key.json
+qapi-schema += empty.json
+qapi-schema += enum-bad-member.json
+qapi-schema += enum-bad-name.json
+qapi-schema += enum-bad-prefix.json
+qapi-schema += enum-clash-member.json
+qapi-schema += enum-dict-member-unknown.json
+qapi-schema += enum-if-invalid.json
+qapi-schema += enum-int-member.json
+qapi-schema += enum-member-case.json
+qapi-schema += enum-missing-data.json
+qapi-schema += enum-wrong-data.json
+qapi-schema += escape-outside-string.json
+qapi-schema += escape-too-big.json
+qapi-schema += escape-too-short.json
+qapi-schema += event-boxed-empty.json
+qapi-schema += event-case.json
+qapi-schema += event-member-invalid-dict.json
+qapi-schema += event-nest-struct.json
+qapi-schema += flat-union-array-branch.json
+qapi-schema += flat-union-bad-base.json
+qapi-schema += flat-union-bad-discriminator.json
+qapi-schema += flat-union-base-any.json
+qapi-schema += flat-union-base-union.json
+qapi-schema += flat-union-clash-member.json
+qapi-schema += flat-union-empty.json
+qapi-schema += flat-union-inline.json
+qapi-schema += flat-union-inline-invalid-dict.json
+qapi-schema += flat-union-int-branch.json
+qapi-schema += flat-union-invalid-branch-key.json
+qapi-schema += flat-union-invalid-discriminator.json
+qapi-schema += flat-union-invalid-if-discriminator.json
+qapi-schema += flat-union-no-base.json
+qapi-schema += flat-union-optional-discriminator.json
+qapi-schema += flat-union-string-discriminator.json
+qapi-schema += funny-char.json
+qapi-schema += ident-with-escape.json
+qapi-schema += include-before-err.json
+qapi-schema += include-cycle.json
+qapi-schema += include-extra-junk.json
+qapi-schema += include-format-err.json
+qapi-schema += include-nested-err.json
+qapi-schema += include-no-file.json
+qapi-schema += include-non-file.json
+qapi-schema += include-relpath.json
+qapi-schema += include-repetition.json
+qapi-schema += include-self-cycle.json
+qapi-schema += include-simple.json
+qapi-schema += indented-expr.json
+qapi-schema += leading-comma-list.json
+qapi-schema += leading-comma-object.json
+qapi-schema += missing-colon.json
+qapi-schema += missing-comma-list.json
+qapi-schema += missing-comma-object.json
+qapi-schema += missing-type.json
+qapi-schema += nested-struct-data.json
+qapi-schema += nested-struct-data-invalid-dict.json
+qapi-schema += non-objects.json
+qapi-schema += oob-test.json
+qapi-schema += allow-preconfig-test.json
+qapi-schema += pragma-doc-required-crap.json
+qapi-schema += pragma-extra-junk.json
+qapi-schema += pragma-name-case-whitelist-crap.json
+qapi-schema += pragma-non-dict.json
+qapi-schema += pragma-returns-whitelist-crap.json
+qapi-schema += qapi-schema-test.json
+qapi-schema += quoted-structural-chars.json
+qapi-schema += redefined-builtin.json
+qapi-schema += redefined-command.json
+qapi-schema += redefined-event.json
+qapi-schema += redefined-type.json
+qapi-schema += reserved-command-q.json
+qapi-schema += reserved-enum-q.json
+qapi-schema += reserved-member-has.json
+qapi-schema += reserved-member-q.json
+qapi-schema += reserved-member-u.json
+qapi-schema += reserved-member-underscore.json
+qapi-schema += reserved-type-kind.json
+qapi-schema += reserved-type-list.json
+qapi-schema += returns-alternate.json
+qapi-schema += returns-array-bad.json
+qapi-schema += returns-dict.json
+qapi-schema += returns-unknown.json
+qapi-schema += returns-whitelist.json
+qapi-schema += struct-base-clash-deep.json
+qapi-schema += struct-base-clash.json
+qapi-schema += struct-data-invalid.json
+qapi-schema += struct-member-invalid-dict.json
+qapi-schema += struct-member-invalid.json
+qapi-schema += trailing-comma-list.json
+qapi-schema += trailing-comma-object.json
+qapi-schema += type-bypass-bad-gen.json
+qapi-schema += unclosed-list.json
+qapi-schema += unclosed-object.json
+qapi-schema += unclosed-string.json
+qapi-schema += unicode-str.json
+qapi-schema += union-base-empty.json
+qapi-schema += union-base-no-discriminator.json
+qapi-schema += union-branch-case.json
+qapi-schema += union-branch-invalid-dict.json
+qapi-schema += union-clash-branches.json
+qapi-schema += union-empty.json
+qapi-schema += union-invalid-base.json
+qapi-schema += union-optional-branch.json
+qapi-schema += union-unknown.json
+qapi-schema += unknown-escape.json
+qapi-schema += unknown-expr-key.json
+
+
+check-qapi-schema-y := $(addprefix tests/qapi-schema/, $(qapi-schema))
+
+GENERATED_FILES += tests/test-qapi-types.h tests/test-qapi-visit.h \
+ tests/test-qapi-commands.h tests/test-qapi-events.h \
+ tests/test-qapi-introspect.h
+
+test-obj-y = tests/check-qnum.o tests/check-qstring.o tests/check-qdict.o \
+ tests/check-qlist.o tests/check-qnull.o tests/check-qobject.o \
+ tests/check-qjson.o tests/check-qlit.o \
+ tests/check-block-qtest.o \
+ tests/test-coroutine.o tests/test-string-output-visitor.o \
+ tests/test-string-input-visitor.o tests/test-qobject-output-visitor.o \
+ tests/test-clone-visitor.o \
+ tests/test-qobject-input-visitor.o \
+ tests/test-qmp-cmds.o tests/test-visitor-serialization.o \
+ tests/test-x86-cpuid.o tests/test-mul64.o tests/test-int128.o \
+ tests/test-opts-visitor.o tests/test-qmp-event.o \
+ tests/rcutorture.o tests/test-rcu-list.o \
+ tests/test-rcu-simpleq.o \
+ tests/test-rcu-tailq.o \
+ tests/test-qdist.o tests/test-shift128.o \
+ tests/test-qht.o tests/qht-bench.o tests/test-qht-par.o \
+ tests/atomic_add-bench.o tests/atomic64-bench.o
+
+$(test-obj-y): QEMU_INCLUDES += -Itests
+QEMU_CFLAGS += -I$(SRC_PATH)/tests
+
+
+# Deps that are common to various different sets of tests below
+test-util-obj-y = libqemuutil.a
+test-qom-obj-y = $(qom-obj-y) $(test-util-obj-y)
+test-qapi-obj-y = tests/test-qapi-visit.o tests/test-qapi-types.o \
+ tests/test-qapi-events.o tests/test-qapi-introspect.o \
+ $(test-qom-obj-y)
+benchmark-crypto-obj-y = $(crypto-obj-y) $(test-qom-obj-y)
+test-crypto-obj-y = $(crypto-obj-y) $(test-qom-obj-y)
+test-io-obj-y = $(io-obj-y) $(test-crypto-obj-y)
+test-block-obj-y = $(block-obj-y) $(test-io-obj-y) tests/iothread.o
+
+tests/check-qnum$(EXESUF): tests/check-qnum.o $(test-util-obj-y)
+tests/check-qstring$(EXESUF): tests/check-qstring.o $(test-util-obj-y)
+tests/check-qdict$(EXESUF): tests/check-qdict.o $(test-util-obj-y)
+tests/check-block-qdict$(EXESUF): tests/check-block-qdict.o $(test-util-obj-y)
+tests/check-qlist$(EXESUF): tests/check-qlist.o $(test-util-obj-y)
+tests/check-qnull$(EXESUF): tests/check-qnull.o $(test-util-obj-y)
+tests/check-qobject$(EXESUF): tests/check-qobject.o $(test-util-obj-y)
+tests/check-qjson$(EXESUF): tests/check-qjson.o $(test-util-obj-y)
+tests/check-qlit$(EXESUF): tests/check-qlit.o $(test-util-obj-y)
+tests/check-qom-interface$(EXESUF): tests/check-qom-interface.o $(test-qom-obj-y)
+tests/check-qom-proplist$(EXESUF): tests/check-qom-proplist.o $(test-qom-obj-y)
+
+tests/test-char$(EXESUF): tests/test-char.o $(test-util-obj-y) $(qtest-obj-y) $(test-io-obj-y) $(chardev-obj-y)
+tests/test-coroutine$(EXESUF): tests/test-coroutine.o $(test-block-obj-y)
+tests/test-aio$(EXESUF): tests/test-aio.o $(test-block-obj-y)
+tests/test-aio-multithread$(EXESUF): tests/test-aio-multithread.o $(test-block-obj-y)
+tests/test-throttle$(EXESUF): tests/test-throttle.o $(test-block-obj-y)
+tests/test-bdrv-drain$(EXESUF): tests/test-bdrv-drain.o $(test-block-obj-y) $(test-util-obj-y)
+tests/test-blockjob$(EXESUF): tests/test-blockjob.o $(test-block-obj-y) $(test-util-obj-y)
+tests/test-blockjob-txn$(EXESUF): tests/test-blockjob-txn.o $(test-block-obj-y) $(test-util-obj-y)
+tests/test-block-backend$(EXESUF): tests/test-block-backend.o $(test-block-obj-y) $(test-util-obj-y)
+tests/test-image-locking$(EXESUF): tests/test-image-locking.o $(test-block-obj-y) $(test-util-obj-y)
+tests/test-thread-pool$(EXESUF): tests/test-thread-pool.o $(test-block-obj-y)
+tests/test-iov$(EXESUF): tests/test-iov.o $(test-util-obj-y)
+tests/test-hbitmap$(EXESUF): tests/test-hbitmap.o $(test-util-obj-y) $(test-crypto-obj-y)
+tests/test-x86-cpuid$(EXESUF): tests/test-x86-cpuid.o
+tests/test-xbzrle$(EXESUF): tests/test-xbzrle.o migration/xbzrle.o migration/page_cache.o $(test-util-obj-y)
+tests/test-cutils$(EXESUF): tests/test-cutils.o util/cutils.o $(test-util-obj-y)
+tests/test-int128$(EXESUF): tests/test-int128.o
+tests/rcutorture$(EXESUF): tests/rcutorture.o $(test-util-obj-y)
+tests/test-rcu-list$(EXESUF): tests/test-rcu-list.o $(test-util-obj-y)
+tests/test-rcu-simpleq$(EXESUF): tests/test-rcu-simpleq.o $(test-util-obj-y)
+tests/test-rcu-tailq$(EXESUF): tests/test-rcu-tailq.o $(test-util-obj-y)
+tests/test-qdist$(EXESUF): tests/test-qdist.o $(test-util-obj-y)
+tests/test-qht$(EXESUF): tests/test-qht.o $(test-util-obj-y)
+tests/test-qht-par$(EXESUF): tests/test-qht-par.o tests/qht-bench$(EXESUF) $(test-util-obj-y)
+tests/qht-bench$(EXESUF): tests/qht-bench.o $(test-util-obj-y)
+tests/test-bufferiszero$(EXESUF): tests/test-bufferiszero.o $(test-util-obj-y)
+tests/atomic_add-bench$(EXESUF): tests/atomic_add-bench.o $(test-util-obj-y)
+tests/atomic64-bench$(EXESUF): tests/atomic64-bench.o $(test-util-obj-y)
+
+tests/fp/%:
+ $(MAKE) -C $(dir $@) $(notdir $@)
+
+tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \
+ hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\
+ hw/core/bus.o \
+ hw/core/irq.o \
+ hw/core/fw-path-provider.o \
+ hw/core/reset.o \
+ $(test-qapi-obj-y)
+tests/test-vmstate$(EXESUF): tests/test-vmstate.o \
+ migration/vmstate.o migration/vmstate-types.o migration/qemu-file.o \
+ migration/qemu-file-channel.o migration/qjson.o \
+ $(test-io-obj-y)
+tests/test-timed-average$(EXESUF): tests/test-timed-average.o $(test-util-obj-y)
+tests/test-base64$(EXESUF): tests/test-base64.o $(test-util-obj-y)
+tests/ptimer-test$(EXESUF): tests/ptimer-test.o tests/ptimer-test-stubs.o hw/core/ptimer.o
+
+tests/test-logging$(EXESUF): tests/test-logging.o $(test-util-obj-y)
+
+tests/test-replication$(EXESUF): tests/test-replication.o $(test-util-obj-y) \
+ $(test-block-obj-y)
+
+tests/test-qapi-types.c tests/test-qapi-types.h \
+tests/test-qapi-visit.c tests/test-qapi-visit.h \
+tests/test-qapi-commands.h tests/test-qapi-commands.c \
+tests/test-qapi-events.c tests/test-qapi-events.h \
+tests/test-qapi-introspect.c tests/test-qapi-introspect.h: \
+tests/test-qapi-gen-timestamp ;
+tests/test-qapi-gen-timestamp: $(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(qapi-py)
+ $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-gen.py \
+ -o tests -p "test-" $<, \
+ "GEN","$(@:%-timestamp=%)")
+ @>$@
+
+tests/qapi-schema/doc-good.test.texi: $(SRC_PATH)/tests/qapi-schema/doc-good.json $(qapi-py)
+ $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-gen.py \
+ -o tests/qapi-schema -p "doc-good-" $<, \
+ "GEN","$@")
+ @mv tests/qapi-schema/doc-good-qapi-doc.texi $@
+ @rm -f tests/qapi-schema/doc-good-qapi-*.[ch] tests/qapi-schema/doc-good-qmp-*.[ch]
+
+tests/test-string-output-visitor$(EXESUF): tests/test-string-output-visitor.o $(test-qapi-obj-y)
+tests/test-string-input-visitor$(EXESUF): tests/test-string-input-visitor.o $(test-qapi-obj-y)
+tests/test-qmp-event$(EXESUF): tests/test-qmp-event.o $(test-qapi-obj-y)
+tests/test-qobject-output-visitor$(EXESUF): tests/test-qobject-output-visitor.o $(test-qapi-obj-y)
+tests/test-clone-visitor$(EXESUF): tests/test-clone-visitor.o $(test-qapi-obj-y)
+tests/test-qobject-input-visitor$(EXESUF): tests/test-qobject-input-visitor.o $(test-qapi-obj-y)
+tests/test-qmp-cmds$(EXESUF): tests/test-qmp-cmds.o tests/test-qapi-commands.o $(test-qapi-obj-y)
+tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o $(test-qapi-obj-y)
+tests/test-opts-visitor$(EXESUF): tests/test-opts-visitor.o $(test-qapi-obj-y)
+
+tests/test-shift128$(EXESUF): tests/test-shift128.o $(test-util-obj-y)
+tests/test-mul64$(EXESUF): tests/test-mul64.o $(test-util-obj-y)
+tests/test-bitops$(EXESUF): tests/test-bitops.o $(test-util-obj-y)
+tests/test-bitcnt$(EXESUF): tests/test-bitcnt.o $(test-util-obj-y)
+tests/test-crypto-hash$(EXESUF): tests/test-crypto-hash.o $(test-crypto-obj-y)
+tests/benchmark-crypto-hash$(EXESUF): tests/benchmark-crypto-hash.o $(test-crypto-obj-y)
+tests/test-crypto-hmac$(EXESUF): tests/test-crypto-hmac.o $(test-crypto-obj-y)
+tests/benchmark-crypto-hmac$(EXESUF): tests/benchmark-crypto-hmac.o $(test-crypto-obj-y)
+tests/test-crypto-cipher$(EXESUF): tests/test-crypto-cipher.o $(test-crypto-obj-y)
+tests/benchmark-crypto-cipher$(EXESUF): tests/benchmark-crypto-cipher.o $(test-crypto-obj-y)
+tests/test-crypto-secret$(EXESUF): tests/test-crypto-secret.o $(test-crypto-obj-y)
+tests/test-crypto-xts$(EXESUF): tests/test-crypto-xts.o $(test-crypto-obj-y)
+
+tests/crypto-tls-x509-helpers.o-cflags := $(TASN1_CFLAGS)
+tests/crypto-tls-x509-helpers.o-libs := $(TASN1_LIBS)
+tests/pkix_asn1_tab.o-cflags := $(TASN1_CFLAGS)
+
+tests/test-crypto-tlscredsx509.o-cflags := $(TASN1_CFLAGS)
+tests/test-crypto-tlscredsx509$(EXESUF): tests/test-crypto-tlscredsx509.o \
+ tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o $(test-crypto-obj-y)
+
+tests/test-crypto-tlssession.o-cflags := $(TASN1_CFLAGS)
+tests/test-crypto-tlssession$(EXESUF): tests/test-crypto-tlssession.o \
+ tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o \
+ tests/crypto-tls-psk-helpers.o \
+ $(test-crypto-obj-y)
+tests/test-util-sockets$(EXESUF): tests/test-util-sockets.o \
+ tests/socket-helpers.o $(test-util-obj-y)
+tests/test-io-task$(EXESUF): tests/test-io-task.o $(test-io-obj-y)
+tests/test-io-channel-socket$(EXESUF): tests/test-io-channel-socket.o \
+ tests/io-channel-helpers.o tests/socket-helpers.o $(test-io-obj-y)
+tests/tpm-crb-swtpm-test$(EXESUF): tests/tpm-crb-swtpm-test.o tests/tpm-emu.o \
+ tests/tpm-util.o tests/tpm-tests.o $(test-io-obj-y)
+tests/tpm-crb-test$(EXESUF): tests/tpm-crb-test.o tests/tpm-emu.o $(test-io-obj-y)
+tests/tpm-tis-swtpm-test$(EXESUF): tests/tpm-tis-swtpm-test.o tests/tpm-emu.o \
+ tests/tpm-util.o tests/tpm-tests.o $(test-io-obj-y)
+tests/tpm-tis-test$(EXESUF): tests/tpm-tis-test.o tests/tpm-emu.o $(test-io-obj-y)
+tests/test-io-channel-file$(EXESUF): tests/test-io-channel-file.o \
+ tests/io-channel-helpers.o $(test-io-obj-y)
+tests/test-io-channel-tls$(EXESUF): tests/test-io-channel-tls.o \
+ tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o \
+ tests/io-channel-helpers.o $(test-io-obj-y)
+tests/test-io-channel-command$(EXESUF): tests/test-io-channel-command.o \
+ tests/io-channel-helpers.o $(test-io-obj-y)
+tests/test-io-channel-buffer$(EXESUF): tests/test-io-channel-buffer.o \
+ tests/io-channel-helpers.o $(test-io-obj-y)
+tests/test-crypto-pbkdf$(EXESUF): tests/test-crypto-pbkdf.o $(test-crypto-obj-y)
+tests/test-crypto-ivgen$(EXESUF): tests/test-crypto-ivgen.o $(test-crypto-obj-y)
+tests/test-crypto-afsplit$(EXESUF): tests/test-crypto-afsplit.o $(test-crypto-obj-y)
+tests/test-crypto-block$(EXESUF): tests/test-crypto-block.o $(test-crypto-obj-y)
+
+libqos-obj-y = tests/libqos/pci.o tests/libqos/fw_cfg.o tests/libqos/malloc.o
+libqos-obj-y += tests/libqos/i2c.o tests/libqos/libqos.o
+libqos-spapr-obj-y = $(libqos-obj-y) tests/libqos/malloc-spapr.o
+libqos-spapr-obj-y += tests/libqos/libqos-spapr.o
+libqos-spapr-obj-y += tests/libqos/rtas.o
+libqos-spapr-obj-y += tests/libqos/pci-spapr.o
+libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o
+libqos-pc-obj-y += tests/libqos/malloc-pc.o tests/libqos/libqos-pc.o
+libqos-pc-obj-y += tests/libqos/ahci.o
+libqos-omap-obj-y = $(libqos-obj-y) tests/libqos/i2c-omap.o
+libqos-imx-obj-y = $(libqos-obj-y) tests/libqos/i2c-imx.o
+libqos-usb-obj-y = $(libqos-spapr-obj-y) $(libqos-pc-obj-y) tests/libqos/usb.o
+libqos-virtio-obj-y = $(libqos-spapr-obj-y) $(libqos-pc-obj-y) tests/libqos/virtio.o tests/libqos/virtio-pci.o tests/libqos/virtio-mmio.o tests/libqos/malloc-generic.o
+
+tests/qmp-test$(EXESUF): tests/qmp-test.o
+tests/qmp-cmd-test$(EXESUF): tests/qmp-cmd-test.o
+tests/device-introspect-test$(EXESUF): tests/device-introspect-test.o
+tests/rtc-test$(EXESUF): tests/rtc-test.o
+tests/m48t59-test$(EXESUF): tests/m48t59-test.o
+tests/hexloader-test$(EXESUF): tests/hexloader-test.o
+tests/endianness-test$(EXESUF): tests/endianness-test.o
+tests/spapr-phb-test$(EXESUF): tests/spapr-phb-test.o $(libqos-obj-y)
+tests/prom-env-test$(EXESUF): tests/prom-env-test.o $(libqos-obj-y)
+tests/rtas-test$(EXESUF): tests/rtas-test.o $(libqos-spapr-obj-y)
+tests/fdc-test$(EXESUF): tests/fdc-test.o
+tests/ide-test$(EXESUF): tests/ide-test.o $(libqos-pc-obj-y)
+tests/ahci-test$(EXESUF): tests/ahci-test.o $(libqos-pc-obj-y)
+tests/ipmi-kcs-test$(EXESUF): tests/ipmi-kcs-test.o
+tests/ipmi-bt-test$(EXESUF): tests/ipmi-bt-test.o
+tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
+tests/boot-order-test$(EXESUF): tests/boot-order-test.o $(libqos-obj-y)
+tests/boot-serial-test$(EXESUF): tests/boot-serial-test.o $(libqos-obj-y)
+tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \
+ tests/boot-sector.o tests/acpi-utils.o $(libqos-obj-y)
+tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y)
+tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
+tests/pca9552-test$(EXESUF): tests/pca9552-test.o $(libqos-omap-obj-y)
+tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y)
+tests/microbit-test$(EXESUF): tests/microbit-test.o
+tests/m25p80-test$(EXESUF): tests/m25p80-test.o
+tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
+tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y)
+tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y)
+tests/e1000-test$(EXESUF): tests/e1000-test.o
+tests/e1000e-test$(EXESUF): tests/e1000e-test.o $(libqos-pc-obj-y)
+tests/rtl8139-test$(EXESUF): tests/rtl8139-test.o $(libqos-pc-obj-y)
+tests/pcnet-test$(EXESUF): tests/pcnet-test.o
+tests/pnv-xscom-test$(EXESUF): tests/pnv-xscom-test.o
+tests/eepro100-test$(EXESUF): tests/eepro100-test.o
+tests/vmxnet3-test$(EXESUF): tests/vmxnet3-test.o
+tests/ne2000-test$(EXESUF): tests/ne2000-test.o
+tests/wdt_ib700-test$(EXESUF): tests/wdt_ib700-test.o
+tests/tco-test$(EXESUF): tests/tco-test.o $(libqos-pc-obj-y)
+tests/virtio-balloon-test$(EXESUF): tests/virtio-balloon-test.o $(libqos-virtio-obj-y)
+tests/virtio-blk-test$(EXESUF): tests/virtio-blk-test.o $(libqos-virtio-obj-y)
+tests/virtio-ccw-test$(EXESUF): tests/virtio-ccw-test.o
+tests/virtio-net-test$(EXESUF): tests/virtio-net-test.o $(libqos-pc-obj-y) $(libqos-virtio-obj-y)
+tests/virtio-rng-test$(EXESUF): tests/virtio-rng-test.o $(libqos-pc-obj-y)
+tests/virtio-scsi-test$(EXESUF): tests/virtio-scsi-test.o $(libqos-virtio-obj-y)
+tests/virtio-9p-test$(EXESUF): tests/virtio-9p-test.o $(libqos-virtio-obj-y)
+tests/virtio-serial-test$(EXESUF): tests/virtio-serial-test.o $(libqos-virtio-obj-y)
+tests/virtio-console-test$(EXESUF): tests/virtio-console-test.o $(libqos-virtio-obj-y)
+tests/tpci200-test$(EXESUF): tests/tpci200-test.o
+tests/display-vga-test$(EXESUF): tests/display-vga-test.o
+tests/ipoctal232-test$(EXESUF): tests/ipoctal232-test.o
+tests/qom-test$(EXESUF): tests/qom-test.o
+tests/test-hmp$(EXESUF): tests/test-hmp.o
+tests/machine-none-test$(EXESUF): tests/machine-none-test.o
+tests/drive_del-test$(EXESUF): tests/drive_del-test.o $(libqos-virtio-obj-y)
+tests/qdev-monitor-test$(EXESUF): tests/qdev-monitor-test.o $(libqos-pc-obj-y)
+tests/nvme-test$(EXESUF): tests/nvme-test.o $(libqos-pc-obj-y)
+tests/pvpanic-test$(EXESUF): tests/pvpanic-test.o
+tests/i82801b11-test$(EXESUF): tests/i82801b11-test.o
+tests/ac97-test$(EXESUF): tests/ac97-test.o
+tests/es1370-test$(EXESUF): tests/es1370-test.o
+tests/intel-hda-test$(EXESUF): tests/intel-hda-test.o
+tests/ioh3420-test$(EXESUF): tests/ioh3420-test.o
+tests/usb-hcd-ohci-test$(EXESUF): tests/usb-hcd-ohci-test.o $(libqos-usb-obj-y)
+tests/usb-hcd-uhci-test$(EXESUF): tests/usb-hcd-uhci-test.o $(libqos-usb-obj-y)
+tests/usb-hcd-ehci-test$(EXESUF): tests/usb-hcd-ehci-test.o $(libqos-usb-obj-y)
+tests/usb-hcd-xhci-test$(EXESUF): tests/usb-hcd-xhci-test.o $(libqos-usb-obj-y)
+tests/cpu-plug-test$(EXESUF): tests/cpu-plug-test.o
+tests/migration-test$(EXESUF): tests/migration-test.o
+tests/vhost-user-test$(EXESUF): tests/vhost-user-test.o $(test-util-obj-y) \
+ $(qtest-obj-y) $(test-io-obj-y) $(libqos-virtio-obj-y) $(libqos-pc-obj-y) \
+ $(chardev-obj-y)
+tests/qemu-iotests/socket_scm_helper$(EXESUF): tests/qemu-iotests/socket_scm_helper.o
+tests/test-qemu-opts$(EXESUF): tests/test-qemu-opts.o $(test-util-obj-y)
+tests/test-keyval$(EXESUF): tests/test-keyval.o $(test-util-obj-y) $(test-qapi-obj-y)
+tests/test-write-threshold$(EXESUF): tests/test-write-threshold.o $(test-block-obj-y)
+tests/test-netfilter$(EXESUF): tests/test-netfilter.o $(qtest-obj-y)
+tests/test-filter-mirror$(EXESUF): tests/test-filter-mirror.o $(qtest-obj-y)
+tests/test-filter-redirector$(EXESUF): tests/test-filter-redirector.o $(qtest-obj-y)
+tests/test-x86-cpuid-compat$(EXESUF): tests/test-x86-cpuid-compat.o $(qtest-obj-y)
+tests/ivshmem-test$(EXESUF): tests/ivshmem-test.o contrib/ivshmem-server/ivshmem-server.o $(libqos-pc-obj-y) $(libqos-spapr-obj-y)
+tests/megasas-test$(EXESUF): tests/megasas-test.o $(libqos-spapr-obj-y) $(libqos-pc-obj-y)
+tests/vhost-user-bridge$(EXESUF): tests/vhost-user-bridge.o $(test-util-obj-y) libvhost-user.a
+tests/test-uuid$(EXESUF): tests/test-uuid.o $(test-util-obj-y)
+tests/test-arm-mptimer$(EXESUF): tests/test-arm-mptimer.o
+tests/test-qapi-util$(EXESUF): tests/test-qapi-util.o $(test-util-obj-y)
+tests/numa-test$(EXESUF): tests/numa-test.o
+tests/vmgenid-test$(EXESUF): tests/vmgenid-test.o tests/boot-sector.o tests/acpi-utils.o
+tests/sdhci-test$(EXESUF): tests/sdhci-test.o $(libqos-pc-obj-y)
+tests/cdrom-test$(EXESUF): tests/cdrom-test.o tests/boot-sector.o $(libqos-obj-y)
+
+tests/migration/stress$(EXESUF): tests/migration/stress.o
+ $(call quiet-command, $(LINKPROG) -static -O3 $(PTHREAD_LIB) -o $@ $< ,"LINK","$(TARGET_DIR)$@")
+
+INITRD_WORK_DIR=tests/migration/initrd
+
+tests/migration/initrd-stress.img: tests/migration/stress$(EXESUF)
+ mkdir -p $(INITRD_WORK_DIR)
+ cp $< $(INITRD_WORK_DIR)/init
+ (cd $(INITRD_WORK_DIR) && (find | cpio --quiet -o -H newc | gzip -9)) > $@
+ rm $(INITRD_WORK_DIR)/init
+ rmdir $(INITRD_WORK_DIR)
+
+ifeq ($(CONFIG_POSIX),y)
+LIBS += -lutil
+endif
+
+# QTest rules
+
+TARGETS=$(patsubst %-softmmu,%, $(filter %-softmmu,$(TARGET_DIRS)))
+ifeq ($(CONFIG_POSIX),y)
+QTEST_TARGETS = $(TARGETS)
+check-qtest-y=$(foreach TARGET,$(TARGETS), $(check-qtest-$(TARGET)-y))
+check-qtest-y += $(check-qtest-generic-y)
+else
+QTEST_TARGETS =
+endif
+
+qtest-obj-y = tests/libqtest.o $(test-util-obj-y)
+$(check-qtest-y): $(qtest-obj-y)
+
+tests/test-qga$(EXESUF): qemu-ga$(EXESUF)
+tests/test-qga$(EXESUF): tests/test-qga.o $(qtest-obj-y)
+
+SPEED = quick
+
+# gtester tests, possibly with verbose output
+# do_test_tap runs all tests, even if some of them fail, while do_test_human
+# stops at the first failure unless -k is given on the command line
+
+define do_test_human_k
+ $(quiet-@)rc=0; $(foreach COMMAND, $1, \
+ $(call quiet-command-run, \
+ export MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$(( $${RANDOM:-0} % 255 + 1))} $2; \
+ $(COMMAND) -m=$(SPEED) -k --tap < /dev/null \
+ | ./scripts/tap-driver.pl --test-name="$(notdir $(COMMAND))" $(if $(V),, --show-failures-only) \
+ || rc=$$?;, "TEST", "$@: $(COMMAND)")) exit $$rc
+endef
+define do_test_human_no_k
+ $(foreach COMMAND, $1, \
+ $(call quiet-command, \
+ MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$(( $${RANDOM:-0} % 255 + 1))} $2 \
+ $(COMMAND) -m=$(SPEED) -k --tap < /dev/null \
+ | ./scripts/tap-driver.pl --test-name="$(notdir $(COMMAND))" $(if $(V),, --show-failures-only), \
+ "TEST", "$@: $(COMMAND)")
+)
+endef
+do_test_human = \
+ $(if $(findstring k, $(MAKEFLAGS)), $(do_test_human_k), $(do_test_human_no_k))
+
+define do_test_tap
+ $(call quiet-command, \
+ { export MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$(( $${RANDOM:-0} % 255 + 1))} $2; \
+ $(foreach COMMAND, $1, \
+ $(COMMAND) -m=$(SPEED) -k --tap < /dev/null \
+ | sed "s/^[a-z][a-z]* [0-9]* /&$(notdir $(COMMAND)) /" || true; ) } \
+ | ./scripts/tap-merge.pl | tee "$@" \
+ | ./scripts/tap-driver.pl $(if $(V),, --show-failures-only), \
+ "TAP","$@")
+endef
+
+.PHONY: $(patsubst %, check-qtest-%, $(QTEST_TARGETS))
+$(patsubst %, check-qtest-%, $(QTEST_TARGETS)): check-qtest-%: subdir-%-softmmu $(check-qtest-y)
+ $(call do_test_human,$(check-qtest-$*-y) $(check-qtest-generic-y), \
+ QTEST_QEMU_BINARY=$*-softmmu/qemu-system-$* \
+ QTEST_QEMU_IMG=qemu-img$(EXESUF))
+
+check-unit: $(check-unit-y)
+ $(call do_test_human, $^)
+
+check-speed: $(check-speed-y)
+ $(call do_test_human, $^)
+
+# gtester tests with TAP output
+
+$(patsubst %, check-report-qtest-%.tap, $(QTEST_TARGETS)): check-report-qtest-%.tap: $(check-qtest-y)
+ $(call do_test_tap, $(check-qtest-$*-y) $(check-qtest-generic-y), \
+ QTEST_QEMU_BINARY=$*-softmmu/qemu-system-$* \
+ QTEST_QEMU_IMG=qemu-img$(EXESUF))
+
+check-report-unit.tap: $(check-unit-y)
+ $(call do_test_tap,$^)
+
+# Reports and overall runs
+
+check-report.tap: $(patsubst %,check-report-qtest-%.tap, $(QTEST_TARGETS)) check-report-unit.tap
+ $(call quiet-command,./scripts/tap-merge.py $^ > $@,"GEN","$@")
+
+# Per guest TCG tests
+
+LINUX_USER_TARGETS=$(filter %-linux-user,$(TARGET_DIRS))
+BUILD_TCG_TARGET_RULES=$(patsubst %,build-tcg-tests-%, $(LINUX_USER_TARGETS))
+CLEAN_TCG_TARGET_RULES=$(patsubst %,clean-tcg-tests-%, $(LINUX_USER_TARGETS))
+RUN_TCG_TARGET_RULES=$(patsubst %,run-tcg-tests-%, $(LINUX_USER_TARGETS))
+
+ifeq ($(HAVE_USER_DOCKER),y)
+# Probe for the Docker Builds needed for each build
+$(foreach PROBE_TARGET,$(TARGET_DIRS), \
+ $(eval -include $(SRC_PATH)/tests/tcg/Makefile.probe) \
+ $(if $(DOCKER_PREREQ), \
+ $(eval build-tcg-tests-$(PROBE_TARGET): $(DOCKER_PREREQ))))
+endif
+
+build-tcg-tests-%:
+ $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)" \
+ SKIP_DOCKER_BUILD=1 TARGET_DIR="$*/" guest-tests, \
+ "BUILD", "TCG tests for $*")
+
+run-tcg-tests-%: % build-tcg-tests-%
+ $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)" \
+ SKIP_DOCKER_BUILD=1 TARGET_DIR="$*/" run-guest-tests, \
+ "RUN", "TCG tests for $*")
+
+clean-tcg-tests-%:
+ $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)" TARGET_DIR="$*/" clean-guest-tests,)
+
+.PHONY: build-tcg
+build-tcg: $(BUILD_TCG_TARGET_RULES)
+
+.PHONY: check-tcg
+check-tcg: $(RUN_TCG_TARGET_RULES)
+
+.PHONY: clean-tcg
+clean-tcg: $(CLEAN_TCG_TARGET_RULES)
+
+# Other tests
+
+QEMU_IOTESTS_HELPERS-$(call land,$(CONFIG_SOFTMMU),$(CONFIG_LINUX)) = tests/qemu-iotests/socket_scm_helper$(EXESUF)
+
+.PHONY: check-tests/qemu-iotests-quick.sh
+check-tests/qemu-iotests-quick.sh: tests/qemu-iotests-quick.sh qemu-img$(EXESUF) qemu-io$(EXESUF) $(QEMU_IOTESTS_HELPERS-y)
+ $<
+
+.PHONY: $(patsubst %, check-%, $(check-qapi-schema-y))
+$(patsubst %, check-%, $(check-qapi-schema-y)): check-%.json: $(SRC_PATH)/%.json
+ $(call quiet-command, PYTHONPATH=$(SRC_PATH)/scripts \
+ $(PYTHON) $(SRC_PATH)/tests/qapi-schema/test-qapi.py \
+ $^ >$*.test.out 2>$*.test.err; \
+ echo $$? >$*.test.exit, \
+ "TEST","$*.out")
+ @# Sanitize error messages (make them independent of build directory)
+ @perl -p -e 's|\Q$(SRC_PATH)\E/||g' $*.test.err | diff -u $(SRC_PATH)/$*.err -
+ @diff -u $(SRC_PATH)/$*.out $*.test.out
+ @diff -u $(SRC_PATH)/$*.exit $*.test.exit
+
+.PHONY: check-tests/qapi-schema/doc-good.texi
+check-tests/qapi-schema/doc-good.texi: tests/qapi-schema/doc-good.test.texi
+ @diff -u $(SRC_PATH)/tests/qapi-schema/doc-good.texi $<
+
+.PHONY: check-decodetree
+check-decodetree:
+ $(call quiet-command, \
+ cd $(SRC_PATH)/tests/decode && \
+ ./check.sh "$(PYTHON)" "$(SRC_PATH)/scripts/decodetree.py", \
+ TEST, decodetree.py)
+
+# Python venv for running tests
+
+.PHONY: check-venv check-acceptance
+
+TESTS_VENV_DIR=$(BUILD_DIR)/tests/venv
+TESTS_VENV_REQ=$(SRC_PATH)/tests/requirements.txt
+TESTS_RESULTS_DIR=$(BUILD_DIR)/tests/results
+# Controls the output generated by Avocado when running tests.
+# Any number of command separated loggers are accepted. For more
+# information please refer to "avocado --help".
+AVOCADO_SHOW=none
+
+PYTHON3 = $(shell $(PYTHON) -c 'import sys; print(1 if sys.version_info >= (3, 0) else 0)')
+ifeq ($(PYTHON3), 1)
+$(TESTS_VENV_DIR): $(TESTS_VENV_REQ)
+ $(call quiet-command, \
+ $(PYTHON) -m venv --system-site-packages $@, \
+ VENV, $@)
+ $(call quiet-command, \
+ $(TESTS_VENV_DIR)/bin/python -m pip -q install -r $(TESTS_VENV_REQ), \
+ PIP, $(TESTS_VENV_REQ))
+ $(call quiet-command, touch $@)
+else
+$(TESTS_VENV_DIR):
+ $(error "venv directory for tests requires Python 3")
+endif
+
+$(TESTS_RESULTS_DIR):
+ $(call quiet-command, mkdir -p $@, \
+ MKDIR, $@)
+
+check-venv: $(TESTS_VENV_DIR)
+
+check-acceptance: check-venv $(TESTS_RESULTS_DIR)
+ $(call quiet-command, \
+ $(TESTS_VENV_DIR)/bin/python -m avocado \
+ --show=$(AVOCADO_SHOW) run --job-results-dir=$(TESTS_RESULTS_DIR) \
+ --failfast=on $(SRC_PATH)/tests/acceptance, \
+ "AVOCADO", "tests/acceptance")
+
+# Consolidated targets
+
+.PHONY: check-qapi-schema check-qtest check-unit check check-clean
+check-qapi-schema: $(patsubst %,check-%, $(check-qapi-schema-y)) check-tests/qapi-schema/doc-good.texi
+check-qtest: $(patsubst %,check-qtest-%, $(QTEST_TARGETS))
+check-block: $(patsubst %,check-%, $(check-block-y))
+check: check-qapi-schema check-unit check-qtest check-decodetree
+check-clean:
+ rm -rf $(check-unit-y) tests/*.o $(QEMU_IOTESTS_HELPERS-y)
+ rm -rf $(sort $(foreach target,$(SYSEMU_TARGET_LIST), $(check-qtest-$(target)-y)) $(check-qtest-generic-y))
+ rm -f tests/test-qapi-gen-timestamp
+ rm -rf $(TESTS_VENV_DIR) $(TESTS_RESULTS_DIR)
+
+clean: check-clean
+
+# Build the help program automatically
+
+all: $(QEMU_IOTESTS_HELPERS-y)
+
+-include $(wildcard tests/*.d)
+-include $(wildcard tests/libqos/*.d)
+
+endif
new file mode 100644
@@ -0,0 +1,569 @@
+export SRC_PATH
+
+qapi-py = $(SRC_PATH)/scripts/qapi.py $(SRC_PATH)/scripts/ordereddict.py
+
+# Get the list of all supported sysemu targets
+SYSEMU_TARGET_LIST := $(subst -softmmu.mak,,$(notdir \
+ $(wildcard $(SRC_PATH)/default-configs/*-softmmu.mak)))
+
+check-unit-y = tests/check-qdict$(EXESUF)
+gcov-files-check-qdict-y = qobject/qdict.c
+check-unit-y += tests/check-qfloat$(EXESUF)
+gcov-files-check-qfloat-y = qobject/qfloat.c
+check-unit-y += tests/check-qint$(EXESUF)
+gcov-files-check-qint-y = qobject/qint.c
+check-unit-y += tests/check-qstring$(EXESUF)
+gcov-files-check-qstring-y = qobject/qstring.c
+check-unit-y += tests/check-qlist$(EXESUF)
+gcov-files-check-qlist-y = qobject/qlist.c
+check-unit-y += tests/check-qjson$(EXESUF)
+gcov-files-check-qjson-y = qobject/qjson.c
+check-unit-y += tests/test-qmp-output-visitor$(EXESUF)
+gcov-files-test-qmp-output-visitor-y = qapi/qmp-output-visitor.c
+check-unit-y += tests/test-qmp-input-visitor$(EXESUF)
+gcov-files-test-qmp-input-visitor-y = qapi/qmp-input-visitor.c
+check-unit-y += tests/test-qmp-input-strict$(EXESUF)
+check-unit-y += tests/test-qmp-commands$(EXESUF)
+gcov-files-test-qmp-commands-y = qapi/qmp-dispatch.c
+check-unit-y += tests/test-string-input-visitor$(EXESUF)
+gcov-files-test-string-input-visitor-y = qapi/string-input-visitor.c
+check-unit-y += tests/test-string-output-visitor$(EXESUF)
+gcov-files-test-string-output-visitor-y = qapi/string-output-visitor.c
+check-unit-y += tests/test-qmp-event$(EXESUF)
+gcov-files-test-qmp-event-y += qapi/qmp-event.c
+check-unit-y += tests/test-opts-visitor$(EXESUF)
+gcov-files-test-opts-visitor-y = qapi/opts-visitor.c
+check-unit-y += tests/test-coroutine$(EXESUF)
+gcov-files-test-coroutine-y = coroutine-$(CONFIG_COROUTINE_BACKEND).c
+check-unit-y += tests/test-visitor-serialization$(EXESUF)
+check-unit-y += tests/test-iov$(EXESUF)
+gcov-files-test-iov-y = util/iov.c
+check-unit-y += tests/test-aio$(EXESUF)
+check-unit-$(CONFIG_POSIX) += tests/test-rfifolock$(EXESUF)
+check-unit-y += tests/test-throttle$(EXESUF)
+gcov-files-test-aio-$(CONFIG_WIN32) = aio-win32.c
+gcov-files-test-aio-$(CONFIG_POSIX) = aio-posix.c
+check-unit-y += tests/test-thread-pool$(EXESUF)
+gcov-files-test-thread-pool-y = thread-pool.c
+gcov-files-test-hbitmap-y = util/hbitmap.c
+check-unit-y += tests/test-hbitmap$(EXESUF)
+check-unit-y += tests/test-x86-cpuid$(EXESUF)
+# all code tested by test-x86-cpuid is inside topology.h
+gcov-files-test-x86-cpuid-y =
+ifeq ($(CONFIG_SOFTMMU),y)
+check-unit-y += tests/test-xbzrle$(EXESUF)
+gcov-files-test-xbzrle-y = migration/xbzrle.c
+check-unit-$(CONFIG_POSIX) += tests/test-vmstate$(EXESUF)
+endif
+check-unit-y += tests/test-cutils$(EXESUF)
+gcov-files-test-cutils-y += util/cutils.c
+check-unit-y += tests/test-mul64$(EXESUF)
+gcov-files-test-mul64-y = util/host-utils.c
+check-unit-y += tests/test-int128$(EXESUF)
+# all code tested by test-int128 is inside int128.h
+gcov-files-test-int128-y =
+check-unit-y += tests/rcutorture$(EXESUF)
+gcov-files-rcutorture-y = util/rcu.c
+check-unit-y += tests/test-rcu-list$(EXESUF)
+gcov-files-test-rcu-list-y = util/rcu.c
+check-unit-y += tests/test-bitops$(EXESUF)
+check-unit-$(CONFIG_HAS_GLIB_SUBPROCESS_TESTS) += tests/test-qdev-global-props$(EXESUF)
+check-unit-y += tests/check-qom-interface$(EXESUF)
+gcov-files-check-qom-interface-y = qom/object.c
+check-unit-y += tests/check-qom-proplist$(EXESUF)
+gcov-files-check-qom-proplist-y = qom/object.c
+check-unit-y += tests/test-qemu-opts$(EXESUF)
+gcov-files-test-qemu-opts-y = qom/test-qemu-opts.c
+check-unit-y += tests/test-write-threshold$(EXESUF)
+gcov-files-test-write-threshold-y = block/write-threshold.c
+check-unit-$(CONFIG_GNUTLS_HASH) += tests/test-crypto-hash$(EXESUF)
+check-unit-y += tests/test-crypto-cipher$(EXESUF)
+check-unit-$(CONFIG_GNUTLS) += tests/test-crypto-tlscredsx509$(EXESUF)
+check-unit-$(CONFIG_GNUTLS) += tests/test-crypto-tlssession$(EXESUF)
+
+check-block-$(CONFIG_POSIX) += tests/qemu-iotests-quick.sh
+
+# All QTests for now are POSIX-only, but the dependencies are
+# really in libqtest, not in the testcases themselves.
+
+gcov-files-ipack-y += hw/ipack/ipack.c
+check-qtest-ipack-y += tests/ipoctal232-test$(EXESUF)
+gcov-files-ipack-y += hw/char/ipoctal232.c
+
+check-qtest-virtioserial-y += tests/virtio-console-test$(EXESUF)
+gcov-files-virtioserial-y += hw/char/virtio-console.c
+
+gcov-files-virtio-y += i386-softmmu/hw/virtio/virtio.c
+check-qtest-virtio-y += tests/virtio-net-test$(EXESUF)
+gcov-files-virtio-y += i386-softmmu/hw/net/virtio-net.c
+check-qtest-virtio-y += tests/virtio-balloon-test$(EXESUF)
+gcov-files-virtio-y += i386-softmmu/hw/virtio/virtio-balloon.c
+check-qtest-virtio-y += tests/virtio-blk-test$(EXESUF)
+gcov-files-virtio-y += i386-softmmu/hw/block/virtio-blk.c
+check-qtest-virtio-y += tests/virtio-rng-test$(EXESUF)
+gcov-files-virtio-y += hw/virtio/virtio-rng.c
+check-qtest-virtio-y += tests/virtio-scsi-test$(EXESUF)
+gcov-files-virtio-y += i386-softmmu/hw/scsi/virtio-scsi.c
+ifeq ($(CONFIG_VIRTIO)$(CONFIG_VIRTFS)$(CONFIG_PCI),yyy)
+check-qtest-virtio-y += tests/virtio-9p-test$(EXESUF)
+gcov-files-virtio-y += hw/9pfs/virtio-9p.c
+gcov-files-virtio-y += i386-softmmu/hw/9pfs/virtio-9p-device.c
+endif
+check-qtest-virtio-y += tests/virtio-serial-test$(EXESUF)
+gcov-files-virtio-y += i386-softmmu/hw/char/virtio-serial-bus.c
+check-qtest-virtio-y += $(check-qtest-virtioserial-y)
+gcov-files-virtio-y += $(gcov-files-virtioserial-y)
+
+check-qtest-pci-y += tests/e1000-test$(EXESUF)
+gcov-files-pci-y += hw/net/e1000.c
+check-qtest-pci-y += tests/rtl8139-test$(EXESUF)
+gcov-files-pci-y += hw/net/rtl8139.c
+check-qtest-pci-y += tests/pcnet-test$(EXESUF)
+gcov-files-pci-y += hw/net/pcnet.c
+gcov-files-pci-y += hw/net/pcnet-pci.c
+check-qtest-pci-y += tests/eepro100-test$(EXESUF)
+gcov-files-pci-y += hw/net/eepro100.c
+check-qtest-pci-y += tests/ne2000-test$(EXESUF)
+gcov-files-pci-y += hw/net/ne2000.c
+check-qtest-pci-y += tests/nvme-test$(EXESUF)
+gcov-files-pci-y += hw/block/nvme.c
+check-qtest-pci-y += tests/ac97-test$(EXESUF)
+gcov-files-pci-y += hw/audio/ac97.c
+check-qtest-pci-y += tests/es1370-test$(EXESUF)
+gcov-files-pci-y += hw/audio/es1370.c
+check-qtest-pci-y += $(check-qtest-virtio-y)
+gcov-files-pci-y += $(gcov-files-virtio-y) hw/virtio/virtio-pci.c
+check-qtest-pci-y += tests/tpci200-test$(EXESUF)
+gcov-files-pci-y += hw/ipack/tpci200.c
+check-qtest-pci-y += $(check-qtest-ipack-y)
+gcov-files-pci-y += $(gcov-files-ipack-y)
+check-qtest-pci-y += tests/display-vga-test$(EXESUF)
+gcov-files-pci-y += hw/display/vga.c
+gcov-files-pci-y += hw/display/cirrus_vga.c
+gcov-files-pci-y += hw/display/vga-pci.c
+gcov-files-pci-y += hw/display/virtio-gpu.c
+gcov-files-pci-y += hw/display/virtio-gpu-pci.c
+gcov-files-pci-$(CONFIG_VIRTIO_VGA) += hw/display/virtio-vga.c
+check-qtest-pci-y += tests/intel-hda-test$(EXESUF)
+gcov-files-pci-y += hw/audio/intel-hda.c hw/audio/hda-codec.c
+
+check-qtest-i386-y = tests/endianness-test$(EXESUF)
+check-qtest-i386-y += tests/fdc-test$(EXESUF)
+gcov-files-i386-y = hw/block/fdc.c
+check-qtest-i386-y += tests/ide-test$(EXESUF)
+check-qtest-i386-y += tests/ahci-test$(EXESUF)
+check-qtest-i386-y += tests/hd-geo-test$(EXESUF)
+gcov-files-i386-y += hw/block/hd-geometry.c
+check-qtest-i386-y += tests/boot-order-test$(EXESUF)
+check-qtest-i386-y += tests/bios-tables-test$(EXESUF)
+check-qtest-i386-y += tests/rtc-test$(EXESUF)
+check-qtest-i386-y += tests/i440fx-test$(EXESUF)
+check-qtest-i386-y += tests/fw_cfg-test$(EXESUF)
+check-qtest-i386-y += tests/drive_del-test$(EXESUF)
+check-qtest-i386-y += tests/wdt_ib700-test$(EXESUF)
+check-qtest-i386-y += tests/tco-test$(EXESUF)
+gcov-files-i386-y += hw/watchdog/watchdog.c hw/watchdog/wdt_ib700.c
+check-qtest-i386-y += $(check-qtest-pci-y)
+gcov-files-i386-y += $(gcov-files-pci-y)
+check-qtest-i386-y += tests/vmxnet3-test$(EXESUF)
+gcov-files-i386-y += hw/net/vmxnet3.c
+gcov-files-i386-y += hw/net/vmxnet_rx_pkt.c
+gcov-files-i386-y += hw/net/vmxnet_tx_pkt.c
+check-qtest-i386-y += tests/pvpanic-test$(EXESUF)
+gcov-files-i386-y += i386-softmmu/hw/misc/pvpanic.c
+check-qtest-i386-y += tests/i82801b11-test$(EXESUF)
+gcov-files-i386-y += hw/pci-bridge/i82801b11.c
+check-qtest-i386-y += tests/ioh3420-test$(EXESUF)
+gcov-files-i386-y += hw/pci-bridge/ioh3420.c
+check-qtest-i386-y += tests/usb-hcd-ohci-test$(EXESUF)
+gcov-files-i386-y += hw/usb/hcd-ohci.c
+check-qtest-i386-y += tests/usb-hcd-uhci-test$(EXESUF)
+gcov-files-i386-y += hw/usb/hcd-uhci.c
+check-qtest-i386-y += tests/usb-hcd-ehci-test$(EXESUF)
+gcov-files-i386-y += hw/usb/hcd-ehci.c
+gcov-files-i386-y += hw/usb/dev-hid.c
+gcov-files-i386-y += hw/usb/dev-storage.c
+check-qtest-i386-y += tests/usb-hcd-xhci-test$(EXESUF)
+gcov-files-i386-y += hw/usb/hcd-xhci.c
+check-qtest-i386-y += tests/pc-cpu-test$(EXESUF)
+check-qtest-i386-y += tests/q35-test$(EXESUF)
+gcov-files-i386-y += hw/pci-host/q35.c
+ifeq ($(CONFIG_VHOST_NET),y)
+check-qtest-i386-$(CONFIG_LINUX) += tests/vhost-user-test$(EXESUF)
+endif
+check-qtest-x86_64-y = $(check-qtest-i386-y)
+gcov-files-i386-y += i386-softmmu/hw/timer/mc146818rtc.c
+gcov-files-x86_64-y = $(subst i386-softmmu/,x86_64-softmmu/,$(gcov-files-i386-y))
+check-qtest-mips-y = tests/endianness-test$(EXESUF)
+check-qtest-mips64-y = tests/endianness-test$(EXESUF)
+check-qtest-mips64el-y = tests/endianness-test$(EXESUF)
+check-qtest-ppc-y = tests/endianness-test$(EXESUF)
+check-qtest-ppc64-y = tests/endianness-test$(EXESUF)
+check-qtest-sh4-y = tests/endianness-test$(EXESUF)
+check-qtest-sh4eb-y = tests/endianness-test$(EXESUF)
+check-qtest-sparc64-y = tests/endianness-test$(EXESUF)
+#check-qtest-sparc-y = tests/m48t59-test$(EXESUF)
+#check-qtest-sparc64-y += tests/m48t59-test$(EXESUF)
+gcov-files-sparc-y += hw/timer/m48t59.c
+gcov-files-sparc64-y += hw/timer/m48t59.c
+check-qtest-arm-y = tests/tmp105-test$(EXESUF)
+check-qtest-arm-y = tests/ds1338-test$(EXESUF)
+gcov-files-arm-y += hw/misc/tmp105.c
+check-qtest-arm-y += tests/virtio-blk-test$(EXESUF)
+gcov-files-arm-y += arm-softmmu/hw/block/virtio-blk.c
+check-qtest-ppc-y += tests/boot-order-test$(EXESUF)
+check-qtest-ppc64-y += tests/boot-order-test$(EXESUF)
+check-qtest-ppc64-y += tests/spapr-phb-test$(EXESUF)
+gcov-files-ppc64-y += ppc64-softmmu/hw/ppc/spapr_pci.c
+check-qtest-microblazeel-y = $(check-qtest-microblaze-y)
+check-qtest-xtensaeb-y = $(check-qtest-xtensa-y)
+
+# qom-test works for all sysemu architectures:
+$(foreach target,$(SYSEMU_TARGET_LIST), \
+ $(if $(findstring tests/qom-test$(EXESUF), $(check-qtest-$(target)-y)),, \
+ $(eval check-qtest-$(target)-y += tests/qom-test$(EXESUF))))
+
+check-qapi-schema-y := $(addprefix tests/qapi-schema/, \
+ comments.json empty.json enum-empty.json enum-missing-data.json \
+ enum-wrong-data.json enum-int-member.json enum-dict-member.json \
+ enum-clash-member.json enum-max-member.json enum-union-clash.json \
+ enum-bad-name.json enum-bad-prefix.json \
+ funny-char.json indented-expr.json \
+ missing-type.json bad-ident.json ident-with-escape.json \
+ escape-outside-string.json unknown-escape.json \
+ escape-too-short.json escape-too-big.json unicode-str.json \
+ double-type.json bad-base.json bad-type-bool.json bad-type-int.json \
+ bad-type-dict.json double-data.json unknown-expr-key.json \
+ redefined-type.json redefined-command.json redefined-builtin.json \
+ redefined-event.json command-int.json bad-data.json event-max.json \
+ type-bypass-bad-gen.json \
+ args-invalid.json \
+ args-array-empty.json args-array-unknown.json args-int.json \
+ args-unknown.json args-member-unknown.json args-member-array.json \
+ args-member-array-bad.json args-alternate.json args-union.json \
+ args-any.json \
+ returns-array-bad.json returns-int.json returns-dict.json \
+ returns-unknown.json returns-alternate.json returns-whitelist.json \
+ missing-colon.json missing-comma-list.json missing-comma-object.json \
+ struct-data-invalid.json struct-member-invalid.json \
+ nested-struct-data.json non-objects.json \
+ qapi-schema-test.json quoted-structural-chars.json \
+ leading-comma-list.json leading-comma-object.json \
+ trailing-comma-list.json trailing-comma-object.json \
+ unclosed-list.json unclosed-object.json unclosed-string.json \
+ duplicate-key.json union-invalid-base.json union-bad-branch.json \
+ union-optional-branch.json union-unknown.json union-max.json \
+ flat-union-optional-discriminator.json flat-union-no-base.json \
+ flat-union-invalid-discriminator.json flat-union-inline.json \
+ flat-union-invalid-branch-key.json flat-union-reverse-define.json \
+ flat-union-string-discriminator.json union-base-no-discriminator.json \
+ flat-union-bad-discriminator.json flat-union-bad-base.json \
+ flat-union-base-any.json \
+ flat-union-array-branch.json flat-union-int-branch.json \
+ flat-union-base-union.json flat-union-branch-clash.json \
+ alternate-nested.json alternate-unknown.json alternate-clash.json \
+ alternate-good.json alternate-base.json alternate-array.json \
+ alternate-conflict-string.json alternate-conflict-dict.json \
+ include-simple.json include-relpath.json include-format-err.json \
+ include-non-file.json include-no-file.json include-before-err.json \
+ include-nested-err.json include-self-cycle.json include-cycle.json \
+ include-repetition.json event-nest-struct.json event-case.json \
+ struct-base-clash.json struct-base-clash-deep.json )
+
+GENERATED_HEADERS += tests/test-qapi-types.h tests/test-qapi-visit.h \
+ tests/test-qmp-commands.h tests/test-qapi-event.h \
+ tests/test-qmp-introspect.h
+
+test-obj-y = tests/check-qint.o tests/check-qstring.o tests/check-qdict.o \
+ tests/check-qlist.o tests/check-qfloat.o tests/check-qjson.o \
+ tests/test-coroutine.o tests/test-string-output-visitor.o \
+ tests/test-string-input-visitor.o tests/test-qmp-output-visitor.o \
+ tests/test-qmp-input-visitor.o tests/test-qmp-input-strict.o \
+ tests/test-qmp-commands.o tests/test-visitor-serialization.o \
+ tests/test-x86-cpuid.o tests/test-mul64.o tests/test-int128.o \
+ tests/test-opts-visitor.o tests/test-qmp-event.o \
+ tests/rcutorture.o tests/test-rcu-list.o
+
+$(test-obj-y): QEMU_INCLUDES += -Itests
+QEMU_CFLAGS += -I$(SRC_PATH)/tests
+
+
+# Deps that are common to various different sets of tests below
+test-util-obj-y = libqemuutil.a libqemustub.a
+test-qom-obj-y = $(qom-obj-y) $(test-util-obj-y)
+test-qapi-obj-y = tests/test-qapi-visit.o tests/test-qapi-types.o \
+ tests/test-qapi-event.o tests/test-qmp-introspect.o \
+ $(test-qom-obj-y)
+test-crypto-obj-y = $(crypto-obj-y) $(test-qom-obj-y)
+test-block-obj-y = $(block-obj-y) $(test-crypto-obj-y)
+
+tests/check-qint$(EXESUF): tests/check-qint.o $(test-util-obj-y)
+tests/check-qstring$(EXESUF): tests/check-qstring.o $(test-util-obj-y)
+tests/check-qdict$(EXESUF): tests/check-qdict.o $(test-util-obj-y)
+tests/check-qlist$(EXESUF): tests/check-qlist.o $(test-util-obj-y)
+tests/check-qfloat$(EXESUF): tests/check-qfloat.o $(test-util-obj-y)
+tests/check-qjson$(EXESUF): tests/check-qjson.o $(test-util-obj-y)
+tests/check-qom-interface$(EXESUF): tests/check-qom-interface.o $(test-qom-obj-y)
+tests/check-qom-proplist$(EXESUF): tests/check-qom-proplist.o $(test-qom-obj-y)
+tests/test-coroutine$(EXESUF): tests/test-coroutine.o $(test-block-obj-y)
+tests/test-aio$(EXESUF): tests/test-aio.o $(test-block-obj-y)
+tests/test-rfifolock$(EXESUF): tests/test-rfifolock.o $(test-util-obj-y)
+tests/test-throttle$(EXESUF): tests/test-throttle.o $(test-block-obj-y)
+tests/test-thread-pool$(EXESUF): tests/test-thread-pool.o $(test-block-obj-y)
+tests/test-iov$(EXESUF): tests/test-iov.o $(test-util-obj-y)
+tests/test-hbitmap$(EXESUF): tests/test-hbitmap.o $(test-util-obj-y)
+tests/test-x86-cpuid$(EXESUF): tests/test-x86-cpuid.o
+tests/test-xbzrle$(EXESUF): tests/test-xbzrle.o migration/xbzrle.o page_cache.o $(test-util-obj-y)
+tests/test-cutils$(EXESUF): tests/test-cutils.o util/cutils.o
+tests/test-int128$(EXESUF): tests/test-int128.o
+tests/rcutorture$(EXESUF): tests/rcutorture.o $(test-util-obj-y)
+tests/test-rcu-list$(EXESUF): tests/test-rcu-list.o $(test-util-obj-y)
+
+tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \
+ hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\
+ hw/core/irq.o \
+ hw/core/fw-path-provider.o \
+ $(test-qapi-obj-y)
+tests/test-vmstate$(EXESUF): tests/test-vmstate.o \
+ migration/vmstate.o migration/qemu-file.o migration/qemu-file-buf.o \
+ migration/qemu-file-unix.o qjson.o \
+ $(test-qom-obj-y)
+
+tests/test-qapi-types.c tests/test-qapi-types.h :\
+$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-types.py $(qapi-py)
+ $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-types.py \
+ $(gen-out-type) -o tests -p "test-" $<, \
+ " GEN $@")
+tests/test-qapi-visit.c tests/test-qapi-visit.h :\
+$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-visit.py $(qapi-py)
+ $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-visit.py \
+ $(gen-out-type) -o tests -p "test-" $<, \
+ " GEN $@")
+tests/test-qmp-commands.h tests/test-qmp-marshal.c :\
+$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-commands.py $(qapi-py)
+ $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-commands.py \
+ $(gen-out-type) -o tests -p "test-" $<, \
+ " GEN $@")
+tests/test-qapi-event.c tests/test-qapi-event.h :\
+$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-event.py $(qapi-py)
+ $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-event.py \
+ $(gen-out-type) -o tests -p "test-" $<, \
+ " GEN $@")
+tests/test-qmp-introspect.c tests/test-qmp-introspect.h :\
+$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-introspect.py $(qapi-py)
+ $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-introspect.py \
+ $(gen-out-type) -o tests -p "test-" $<, \
+ " GEN $@")
+
+tests/test-string-output-visitor$(EXESUF): tests/test-string-output-visitor.o $(test-qapi-obj-y)
+tests/test-string-input-visitor$(EXESUF): tests/test-string-input-visitor.o $(test-qapi-obj-y)
+tests/test-qmp-event$(EXESUF): tests/test-qmp-event.o $(test-qapi-obj-y)
+tests/test-qmp-output-visitor$(EXESUF): tests/test-qmp-output-visitor.o $(test-qapi-obj-y)
+tests/test-qmp-input-visitor$(EXESUF): tests/test-qmp-input-visitor.o $(test-qapi-obj-y)
+tests/test-qmp-input-strict$(EXESUF): tests/test-qmp-input-strict.o $(test-qapi-obj-y)
+tests/test-qmp-commands$(EXESUF): tests/test-qmp-commands.o tests/test-qmp-marshal.o $(test-qapi-obj-y)
+tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o $(test-qapi-obj-y)
+tests/test-opts-visitor$(EXESUF): tests/test-opts-visitor.o $(test-qapi-obj-y)
+
+tests/test-mul64$(EXESUF): tests/test-mul64.o $(test-util-obj-y)
+tests/test-bitops$(EXESUF): tests/test-bitops.o $(test-util-obj-y)
+tests/test-crypto-hash$(EXESUF): tests/test-crypto-hash.o $(test-crypto-obj-y)
+tests/test-crypto-cipher$(EXESUF): tests/test-crypto-cipher.o $(test-crypto-obj-y)
+tests/test-crypto-tlscredsx509$(EXESUF): tests/test-crypto-tlscredsx509.o \
+ tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o $(test-crypto-obj-y)
+tests/test-crypto-tlssession$(EXESUF): tests/test-crypto-tlssession.o \
+ tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o $(test-crypto-obj-y)
+
+libqos-obj-y = tests/libqos/pci.o tests/libqos/fw_cfg.o tests/libqos/malloc.o
+libqos-obj-y += tests/libqos/i2c.o tests/libqos/libqos.o
+libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o
+libqos-pc-obj-y += tests/libqos/malloc-pc.o tests/libqos/libqos-pc.o
+libqos-pc-obj-y += tests/libqos/ahci.o
+libqos-omap-obj-y = $(libqos-obj-y) tests/libqos/i2c-omap.o
+libqos-imx-obj-y = $(libqos-obj-y) tests/libqos/i2c-imx.o
+libqos-usb-obj-y = $(libqos-pc-obj-y) tests/libqos/usb.o
+libqos-virtio-obj-y = $(libqos-pc-obj-y) tests/libqos/virtio.o tests/libqos/virtio-pci.o tests/libqos/virtio-mmio.o tests/libqos/malloc-generic.o
+
+tests/rtc-test$(EXESUF): tests/rtc-test.o
+tests/m48t59-test$(EXESUF): tests/m48t59-test.o
+tests/endianness-test$(EXESUF): tests/endianness-test.o
+tests/spapr-phb-test$(EXESUF): tests/spapr-phb-test.o $(libqos-obj-y)
+tests/fdc-test$(EXESUF): tests/fdc-test.o
+tests/ide-test$(EXESUF): tests/ide-test.o $(libqos-pc-obj-y)
+tests/ahci-test$(EXESUF): tests/ahci-test.o $(libqos-pc-obj-y)
+tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
+tests/boot-order-test$(EXESUF): tests/boot-order-test.o $(libqos-obj-y)
+tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o $(libqos-obj-y)
+tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y)
+tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y)
+tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y)
+tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y)
+tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y)
+tests/e1000-test$(EXESUF): tests/e1000-test.o
+tests/rtl8139-test$(EXESUF): tests/rtl8139-test.o $(libqos-pc-obj-y)
+tests/pcnet-test$(EXESUF): tests/pcnet-test.o
+tests/eepro100-test$(EXESUF): tests/eepro100-test.o
+tests/vmxnet3-test$(EXESUF): tests/vmxnet3-test.o
+tests/ne2000-test$(EXESUF): tests/ne2000-test.o
+tests/wdt_ib700-test$(EXESUF): tests/wdt_ib700-test.o
+tests/tco-test$(EXESUF): tests/tco-test.o $(libqos-pc-obj-y)
+tests/virtio-balloon-test$(EXESUF): tests/virtio-balloon-test.o
+tests/virtio-blk-test$(EXESUF): tests/virtio-blk-test.o $(libqos-virtio-obj-y)
+tests/virtio-net-test$(EXESUF): tests/virtio-net-test.o $(libqos-pc-obj-y) $(libqos-virtio-obj-y)
+tests/virtio-rng-test$(EXESUF): tests/virtio-rng-test.o $(libqos-pc-obj-y)
+tests/virtio-scsi-test$(EXESUF): tests/virtio-scsi-test.o $(libqos-virtio-obj-y)
+tests/virtio-9p-test$(EXESUF): tests/virtio-9p-test.o
+tests/virtio-serial-test$(EXESUF): tests/virtio-serial-test.o
+tests/virtio-console-test$(EXESUF): tests/virtio-console-test.o
+tests/tpci200-test$(EXESUF): tests/tpci200-test.o
+tests/display-vga-test$(EXESUF): tests/display-vga-test.o
+tests/ipoctal232-test$(EXESUF): tests/ipoctal232-test.o
+tests/qom-test$(EXESUF): tests/qom-test.o
+tests/drive_del-test$(EXESUF): tests/drive_del-test.o $(libqos-pc-obj-y)
+tests/qdev-monitor-test$(EXESUF): tests/qdev-monitor-test.o $(libqos-pc-obj-y)
+tests/nvme-test$(EXESUF): tests/nvme-test.o
+tests/pvpanic-test$(EXESUF): tests/pvpanic-test.o
+tests/i82801b11-test$(EXESUF): tests/i82801b11-test.o
+tests/ac97-test$(EXESUF): tests/ac97-test.o
+tests/es1370-test$(EXESUF): tests/es1370-test.o
+tests/intel-hda-test$(EXESUF): tests/intel-hda-test.o
+tests/ioh3420-test$(EXESUF): tests/ioh3420-test.o
+tests/usb-hcd-ohci-test$(EXESUF): tests/usb-hcd-ohci-test.o $(libqos-usb-obj-y)
+tests/usb-hcd-uhci-test$(EXESUF): tests/usb-hcd-uhci-test.o $(libqos-usb-obj-y)
+tests/usb-hcd-ehci-test$(EXESUF): tests/usb-hcd-ehci-test.o $(libqos-usb-obj-y)
+tests/usb-hcd-xhci-test$(EXESUF): tests/usb-hcd-xhci-test.o $(libqos-usb-obj-y)
+tests/pc-cpu-test$(EXESUF): tests/pc-cpu-test.o
+tests/vhost-user-test$(EXESUF): tests/vhost-user-test.o qemu-char.o qemu-timer.o $(qtest-obj-y)
+tests/qemu-iotests/socket_scm_helper$(EXESUF): tests/qemu-iotests/socket_scm_helper.o
+tests/test-qemu-opts$(EXESUF): tests/test-qemu-opts.o $(test-util-obj-y)
+tests/test-write-threshold$(EXESUF): tests/test-write-threshold.o $(test-block-obj-y)
+
+ifeq ($(CONFIG_POSIX),y)
+LIBS += -lutil
+endif
+LIBS += $(TEST_LIBS)
+CFLAGS += $(TEST_CFLAGS)
+
+# QTest rules
+
+TARGETS=$(patsubst %-softmmu,%, $(filter %-softmmu,$(TARGET_DIRS)))
+ifeq ($(CONFIG_POSIX),y)
+QTEST_TARGETS=$(foreach TARGET,$(TARGETS), $(if $(check-qtest-$(TARGET)-y), $(TARGET),))
+check-qtest-y=$(foreach TARGET,$(TARGETS), $(check-qtest-$(TARGET)-y))
+endif
+
+qtest-obj-y = tests/libqtest.o $(test-util-obj-y)
+$(check-qtest-y): $(qtest-obj-y)
+
+.PHONY: check-help
+check-help:
+ @echo "Regression testing targets:"
+ @echo
+ @echo " make check Run all tests"
+ @echo " make check-qtest-TARGET Run qtest tests for given target"
+ @echo " make check-qtest Run qtest tests"
+ @echo " make check-unit Run qobject tests"
+ @echo " make check-qapi-schema Run QAPI schema tests"
+ @echo " make check-block Run block tests"
+ @echo " make check-report.html Generates an HTML test report"
+ @echo " make check-clean Clean the tests"
+ @echo
+ @echo "Please note that HTML reports do not regenerate if the unit tests"
+ @echo "has not changed."
+ @echo
+ @echo "The variable SPEED can be set to control the gtester speed setting."
+ @echo "Default options are -k and (for make V=1) --verbose; they can be"
+ @echo "changed with variable GTESTER_OPTIONS."
+
+SPEED = quick
+GTESTER_OPTIONS = -k $(if $(V),--verbose,-q)
+GCOV_OPTIONS = -n $(if $(V),-f,)
+
+# gtester tests, possibly with verbose output
+
+.PHONY: $(patsubst %, check-qtest-%, $(QTEST_TARGETS))
+$(patsubst %, check-qtest-%, $(QTEST_TARGETS)): check-qtest-%: $(check-qtest-y)
+ $(if $(CONFIG_GCOV),@rm -f *.gcda */*.gcda */*/*.gcda */*/*/*.gcda,)
+ $(call quiet-command,QTEST_QEMU_BINARY=$*-softmmu/qemu-system-$* \
+ QTEST_QEMU_IMG=qemu-img$(EXESUF) \
+ MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$((RANDOM % 255 + 1))} \
+ gtester $(GTESTER_OPTIONS) -m=$(SPEED) $(check-qtest-$*-y),"GTESTER $@")
+ $(if $(CONFIG_GCOV),@for f in $(gcov-files-$*-y); do \
+ echo Gcov report for $$f:;\
+ $(GCOV) $(GCOV_OPTIONS) $$f -o `dirname $$f`; \
+ done,)
+
+.PHONY: $(patsubst %, check-%, $(check-unit-y))
+$(patsubst %, check-%, $(check-unit-y)): check-%: %
+ $(if $(CONFIG_GCOV),@rm -f *.gcda */*.gcda */*/*.gcda */*/*/*.gcda,)
+ $(call quiet-command, \
+ MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$((RANDOM % 255 + 1))} \
+ gtester $(GTESTER_OPTIONS) -m=$(SPEED) $*,"GTESTER $*")
+ $(if $(CONFIG_GCOV),@for f in $(gcov-files-$(subst tests/,,$*)-y); do \
+ echo Gcov report for $$f:;\
+ $(GCOV) $(GCOV_OPTIONS) $$f -o `dirname $$f`; \
+ done,)
+
+# gtester tests with XML output
+
+$(patsubst %, check-report-qtest-%.xml, $(QTEST_TARGETS)): check-report-qtest-%.xml: $(check-qtest-y)
+ $(call quiet-command,QTEST_QEMU_BINARY=$*-softmmu/qemu-system-$* \
+ QTEST_QEMU_IMG=qemu-img$(EXESUF) \
+ gtester -q $(GTESTER_OPTIONS) -o $@ -m=$(SPEED) $(check-qtest-$*-y),"GTESTER $@")
+
+check-report-unit.xml: $(check-unit-y)
+ $(call quiet-command,gtester -q $(GTESTER_OPTIONS) -o $@ -m=$(SPEED) $^, "GTESTER $@")
+
+# Reports and overall runs
+
+check-report.xml: $(patsubst %,check-report-qtest-%.xml, $(QTEST_TARGETS)) check-report-unit.xml
+ $(call quiet-command,$(SRC_PATH)/scripts/gtester-cat $^ > $@, " GEN $@")
+
+check-report.html: check-report.xml
+ $(call quiet-command,gtester-report $< > $@, " GEN $@")
+
+
+# Other tests
+
+QEMU_IOTESTS_HELPERS-$(CONFIG_LINUX) = tests/qemu-iotests/socket_scm_helper$(EXESUF)
+
+.PHONY: check-tests/qemu-iotests-quick.sh
+check-tests/qemu-iotests-quick.sh: tests/qemu-iotests-quick.sh qemu-img$(EXESUF) qemu-io$(EXESUF) $(QEMU_IOTESTS_HELPERS-y)
+ $<
+
+.PHONY: check-tests/test-qapi.py
+check-tests/test-qapi.py: tests/test-qapi.py
+
+.PHONY: $(patsubst %, check-%, $(check-qapi-schema-y))
+$(patsubst %, check-%, $(check-qapi-schema-y)): check-%.json: $(SRC_PATH)/%.json
+ $(call quiet-command, PYTHONPATH=$(SRC_PATH)/scripts \
+ $(PYTHON) $(SRC_PATH)/tests/qapi-schema/test-qapi.py \
+ $^ >$*.test.out 2>$*.test.err; \
+ echo $$? >$*.test.exit, \
+ " TEST $*.out")
+ @diff -q $(SRC_PATH)/$*.out $*.test.out
+ @# Sanitize error messages (make them independent of build directory)
+ @perl -p -e 's|\Q$(SRC_PATH)\E/||g' $*.test.err | diff -q $(SRC_PATH)/$*.err -
+ @diff -q $(SRC_PATH)/$*.exit $*.test.exit
+
+# Consolidated targets
+
+.PHONY: check-qapi-schema check-qtest check-unit check check-clean
+check-qapi-schema: $(patsubst %,check-%, $(check-qapi-schema-y))
+check-qtest: $(patsubst %,check-qtest-%, $(QTEST_TARGETS))
+check-unit: $(patsubst %,check-%, $(check-unit-y))
+check-block: $(patsubst %,check-%, $(check-block-y))
+check: check-qapi-schema check-unit check-qtest
+check-clean:
+ $(MAKE) -C tests/tcg clean
+ rm -rf $(check-unit-y) tests/*.o $(QEMU_IOTESTS_HELPERS-y)
+ rm -rf $(sort $(foreach target,$(SYSEMU_TARGET_LIST), $(check-qtest-$(target)-y)))
+
+clean: check-clean
+
+# Build the help program automatically
+
+all: $(QEMU_IOTESTS_HELPERS-y)
+
+-include $(wildcard tests/*.d)
+-include $(wildcard tests/libqos/*.d)
new file mode 100644
@@ -0,0 +1,925 @@
+/*
+ * Boot order test cases.
+ *
+ * Copyright (c) 2013 Red Hat Inc.
+ *
+ * Authors:
+ * Michael S. Tsirkin <mst@redhat.com>,
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include <glib/gstdio.h>
+#include "qemu-common.h"
+#include "hw/firmware/smbios.h"
+#include "qemu/bitmap.h"
+#include "acpi-utils.h"
+#include "boot-sector.h"
+
+#define MACHINE_PC "pc"
+#define MACHINE_Q35 "q35"
+
+#define ACPI_REBUILD_EXPECTED_AML "TEST_ACPI_REBUILD_AML"
+
+typedef struct {
+ const char *machine;
+ const char *variant;
+ uint32_t rsdp_addr;
+ uint8_t rsdp_table[36 /* ACPI 2.0+ RSDP size */];
+ AcpiRsdtDescriptorRev1 rsdt_table;
+ uint32_t dsdt_addr;
+ uint32_t facs_addr;
+ AcpiFacsDescriptorRev1 facs_table;
+ uint32_t *rsdt_tables_addr;
+ int rsdt_tables_nr;
+ GArray *tables;
+ uint32_t smbios_ep_addr;
+ struct smbios_21_entry_point smbios_ep_table;
+ uint8_t *required_struct_types;
+ int required_struct_types_len;
+ QTestState *qts;
+} test_data;
+
+static char disk[] = "tests/acpi-test-disk-XXXXXX";
+static const char *data_dir = "tests/data/acpi";
+#ifdef CONFIG_IASL
+static const char *iasl = stringify(CONFIG_IASL);
+#else
+static const char *iasl;
+#endif
+
+static void free_test_data(test_data *data)
+{
+ AcpiSdtTable *temp;
+ int i;
+
+ g_free(data->rsdt_tables_addr);
+
+ for (i = 0; i < data->tables->len; ++i) {
+ temp = &g_array_index(data->tables, AcpiSdtTable, i);
+ g_free(temp->aml);
+ if (temp->aml_file &&
+ !temp->tmp_files_retain &&
+ g_strstr_len(temp->aml_file, -1, "aml-")) {
+ unlink(temp->aml_file);
+ }
+ g_free(temp->aml_file);
+ g_free(temp->asl);
+ if (temp->asl_file &&
+ !temp->tmp_files_retain) {
+ unlink(temp->asl_file);
+ }
+ g_free(temp->asl_file);
+ }
+
+ g_array_free(data->tables, true);
+}
+
+static void test_acpi_rsdp_address(test_data *data)
+{
+ uint32_t off = acpi_find_rsdp_address(data->qts);
+ g_assert_cmphex(off, <, 0x100000);
+ data->rsdp_addr = off;
+}
+
+static void test_acpi_rsdp_table(test_data *data)
+{
+ uint8_t *rsdp_table = data->rsdp_table, revision;
+ uint32_t addr = data->rsdp_addr;
+
+ acpi_parse_rsdp_table(data->qts, addr, rsdp_table);
+ revision = rsdp_table[15 /* Revision offset */];
+
+ switch (revision) {
+ case 0: /* ACPI 1.0 RSDP */
+ /* With rev 1, checksum is only for the first 20 bytes */
+ g_assert(!acpi_calc_checksum(rsdp_table, 20));
+ break;
+ case 2: /* ACPI 2.0+ RSDP */
+ /* With revision 2, we have 2 checksums */
+ g_assert(!acpi_calc_checksum(rsdp_table, 20));
+ g_assert(!acpi_calc_checksum(rsdp_table, 36));
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void test_acpi_rsdt_table(test_data *data)
+{
+ AcpiRsdtDescriptorRev1 *rsdt_table = &data->rsdt_table;
+ uint32_t addr = acpi_get_rsdt_address(data->rsdp_table);
+ uint32_t *tables;
+ int tables_nr;
+ uint8_t checksum;
+ uint32_t rsdt_table_length;
+
+ /* read the header */
+ ACPI_READ_TABLE_HEADER(data->qts, rsdt_table, addr);
+ ACPI_ASSERT_CMP(rsdt_table->signature, "RSDT");
+
+ rsdt_table_length = le32_to_cpu(rsdt_table->length);
+
+ /* compute the table entries in rsdt */
+ tables_nr = (rsdt_table_length - sizeof(AcpiRsdtDescriptorRev1)) /
+ sizeof(uint32_t);
+ g_assert(tables_nr > 0);
+
+ /* get the addresses of the tables pointed by rsdt */
+ tables = g_new0(uint32_t, tables_nr);
+ ACPI_READ_ARRAY_PTR(data->qts, tables, tables_nr, addr);
+
+ checksum = acpi_calc_checksum((uint8_t *)rsdt_table, rsdt_table_length) +
+ acpi_calc_checksum((uint8_t *)tables,
+ tables_nr * sizeof(uint32_t));
+ g_assert(!checksum);
+
+ /* SSDT tables after FADT */
+ data->rsdt_tables_addr = tables;
+ data->rsdt_tables_nr = tables_nr;
+}
+
+static void fadt_fetch_facs_and_dsdt_ptrs(test_data *data)
+{
+ uint32_t addr;
+ AcpiTableHeader hdr;
+
+ /* FADT table comes first */
+ addr = le32_to_cpu(data->rsdt_tables_addr[0]);
+ ACPI_READ_TABLE_HEADER(data->qts, &hdr, addr);
+ ACPI_ASSERT_CMP(hdr.signature, "FACP");
+
+ ACPI_READ_FIELD(data->qts, data->facs_addr, addr);
+ ACPI_READ_FIELD(data->qts, data->dsdt_addr, addr);
+}
+
+static void sanitize_fadt_ptrs(test_data *data)
+{
+ /* fixup pointers in FADT */
+ int i;
+
+ for (i = 0; i < data->tables->len; i++) {
+ AcpiSdtTable *sdt = &g_array_index(data->tables, AcpiSdtTable, i);
+
+ if (memcmp(&sdt->header.signature, "FACP", 4)) {
+ continue;
+ }
+
+ /* check original FADT checksum before sanitizing table */
+ g_assert(!(uint8_t)(
+ acpi_calc_checksum((uint8_t *)sdt, sizeof(AcpiTableHeader)) +
+ acpi_calc_checksum((uint8_t *)sdt->aml, sdt->aml_len)
+ ));
+
+ /* sdt->aml field offset := spec offset - header size */
+ memset(sdt->aml + 0, 0, 4); /* sanitize FIRMWARE_CTRL(36) ptr */
+ memset(sdt->aml + 4, 0, 4); /* sanitize DSDT(40) ptr */
+ if (sdt->header.revision >= 3) {
+ memset(sdt->aml + 96, 0, 8); /* sanitize X_FIRMWARE_CTRL(132) ptr */
+ memset(sdt->aml + 104, 0, 8); /* sanitize X_DSDT(140) ptr */
+ }
+
+ /* update checksum */
+ sdt->header.checksum = 0;
+ sdt->header.checksum -=
+ acpi_calc_checksum((uint8_t *)sdt, sizeof(AcpiTableHeader)) +
+ acpi_calc_checksum((uint8_t *)sdt->aml, sdt->aml_len);
+ break;
+ }
+}
+
+static void test_acpi_facs_table(test_data *data)
+{
+ AcpiFacsDescriptorRev1 *facs_table = &data->facs_table;
+ uint32_t addr = le32_to_cpu(data->facs_addr);
+
+ ACPI_READ_FIELD(data->qts, facs_table->signature, addr);
+ ACPI_READ_FIELD(data->qts, facs_table->length, addr);
+ ACPI_READ_FIELD(data->qts, facs_table->hardware_signature, addr);
+ ACPI_READ_FIELD(data->qts, facs_table->firmware_waking_vector, addr);
+ ACPI_READ_FIELD(data->qts, facs_table->global_lock, addr);
+ ACPI_READ_FIELD(data->qts, facs_table->flags, addr);
+ ACPI_READ_ARRAY(data->qts, facs_table->resverved3, addr);
+
+ ACPI_ASSERT_CMP(facs_table->signature, "FACS");
+}
+
+/** fetch_table
+ * load ACPI table at @addr into table descriptor @sdt_table
+ * and check that header checksum matches actual one.
+ */
+static void fetch_table(QTestState *qts, AcpiSdtTable *sdt_table, uint32_t addr)
+{
+ uint8_t checksum;
+
+ memset(sdt_table, 0, sizeof(*sdt_table));
+ ACPI_READ_TABLE_HEADER(qts, &sdt_table->header, addr);
+
+ sdt_table->aml_len = le32_to_cpu(sdt_table->header.length)
+ - sizeof(AcpiTableHeader);
+ sdt_table->aml = g_malloc0(sdt_table->aml_len);
+ ACPI_READ_ARRAY_PTR(qts, sdt_table->aml, sdt_table->aml_len, addr);
+
+ checksum = acpi_calc_checksum((uint8_t *)sdt_table,
+ sizeof(AcpiTableHeader)) +
+ acpi_calc_checksum((uint8_t *)sdt_table->aml,
+ sdt_table->aml_len);
+ g_assert(!checksum);
+}
+
+static void test_acpi_dsdt_table(test_data *data)
+{
+ AcpiSdtTable dsdt_table;
+ uint32_t addr = le32_to_cpu(data->dsdt_addr);
+
+ fetch_table(data->qts, &dsdt_table, addr);
+ ACPI_ASSERT_CMP(dsdt_table.header.signature, "DSDT");
+
+ /* Since DSDT isn't in RSDT, add DSDT to ASL test tables list manually */
+ g_array_append_val(data->tables, dsdt_table);
+}
+
+/* Load all tables and add to test list directly RSDT referenced tables */
+static void fetch_rsdt_referenced_tables(test_data *data)
+{
+ int tables_nr = data->rsdt_tables_nr;
+ int i;
+
+ for (i = 0; i < tables_nr; i++) {
+ AcpiSdtTable ssdt_table;
+ uint32_t addr;
+
+ addr = le32_to_cpu(data->rsdt_tables_addr[i]);
+ fetch_table(data->qts, &ssdt_table, addr);
+
+ /* Add table to ASL test tables list */
+ g_array_append_val(data->tables, ssdt_table);
+ }
+}
+
+static void dump_aml_files(test_data *data, bool rebuild)
+{
+ AcpiSdtTable *sdt;
+ GError *error = NULL;
+ gchar *aml_file = NULL;
+ gint fd;
+ ssize_t ret;
+ int i;
+
+ for (i = 0; i < data->tables->len; ++i) {
+ const char *ext = data->variant ? data->variant : "";
+ sdt = &g_array_index(data->tables, AcpiSdtTable, i);
+ g_assert(sdt->aml);
+
+ if (rebuild) {
+ aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine,
+ (gchar *)&sdt->header.signature, ext);
+ fd = g_open(aml_file, O_WRONLY|O_TRUNC|O_CREAT,
+ S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH);
+ } else {
+ fd = g_file_open_tmp("aml-XXXXXX", &sdt->aml_file, &error);
+ g_assert_no_error(error);
+ }
+ g_assert(fd >= 0);
+
+ ret = qemu_write_full(fd, sdt, sizeof(AcpiTableHeader));
+ g_assert(ret == sizeof(AcpiTableHeader));
+ ret = qemu_write_full(fd, sdt->aml, sdt->aml_len);
+ g_assert(ret == sdt->aml_len);
+
+ close(fd);
+
+ g_free(aml_file);
+ }
+}
+
+static bool compare_signature(AcpiSdtTable *sdt, const char *signature)
+{
+ return !memcmp(&sdt->header.signature, signature, 4);
+}
+
+static bool load_asl(GArray *sdts, AcpiSdtTable *sdt)
+{
+ AcpiSdtTable *temp;
+ GError *error = NULL;
+ GString *command_line = g_string_new(iasl);
+ gint fd;
+ gchar *out, *out_err;
+ gboolean ret;
+ int i;
+
+ fd = g_file_open_tmp("asl-XXXXXX.dsl", &sdt->asl_file, &error);
+ g_assert_no_error(error);
+ close(fd);
+
+ /* build command line */
+ g_string_append_printf(command_line, " -p %s ", sdt->asl_file);
+ if (compare_signature(sdt, "DSDT") ||
+ compare_signature(sdt, "SSDT")) {
+ for (i = 0; i < sdts->len; ++i) {
+ temp = &g_array_index(sdts, AcpiSdtTable, i);
+ if (compare_signature(temp, "DSDT") ||
+ compare_signature(temp, "SSDT")) {
+ g_string_append_printf(command_line, "-e %s ", temp->aml_file);
+ }
+ }
+ }
+ g_string_append_printf(command_line, "-d %s", sdt->aml_file);
+
+ /* pass 'out' and 'out_err' in order to be redirected */
+ ret = g_spawn_command_line_sync(command_line->str, &out, &out_err, NULL, &error);
+ g_assert_no_error(error);
+ if (ret) {
+ ret = g_file_get_contents(sdt->asl_file, &sdt->asl,
+ &sdt->asl_len, &error);
+ g_assert(ret);
+ g_assert_no_error(error);
+ ret = (sdt->asl_len > 0);
+ }
+
+ g_free(out);
+ g_free(out_err);
+ g_string_free(command_line, true);
+
+ return !ret;
+}
+
+#define COMMENT_END "*/"
+#define DEF_BLOCK "DefinitionBlock ("
+#define BLOCK_NAME_END ","
+
+static GString *normalize_asl(gchar *asl_code)
+{
+ GString *asl = g_string_new(asl_code);
+ gchar *comment, *block_name;
+
+ /* strip comments (different generation days) */
+ comment = g_strstr_len(asl->str, asl->len, COMMENT_END);
+ if (comment) {
+ comment += strlen(COMMENT_END);
+ while (*comment == '\n') {
+ comment++;
+ }
+ asl = g_string_erase(asl, 0, comment - asl->str);
+ }
+
+ /* strip def block name (it has file path in it) */
+ if (g_str_has_prefix(asl->str, DEF_BLOCK)) {
+ block_name = g_strstr_len(asl->str, asl->len, BLOCK_NAME_END);
+ g_assert(block_name);
+ asl = g_string_erase(asl, 0,
+ block_name + sizeof(BLOCK_NAME_END) - asl->str);
+ }
+
+ return asl;
+}
+
+static GArray *load_expected_aml(test_data *data)
+{
+ int i;
+ AcpiSdtTable *sdt;
+ GError *error = NULL;
+ gboolean ret;
+
+ GArray *exp_tables = g_array_new(false, true, sizeof(AcpiSdtTable));
+ if (getenv("V")) {
+ fputc('\n', stderr);
+ }
+ for (i = 0; i < data->tables->len; ++i) {
+ AcpiSdtTable exp_sdt;
+ gchar *aml_file = NULL;
+ const char *ext = data->variant ? data->variant : "";
+
+ sdt = &g_array_index(data->tables, AcpiSdtTable, i);
+
+ memset(&exp_sdt, 0, sizeof(exp_sdt));
+ exp_sdt.header.signature = sdt->header.signature;
+
+try_again:
+ aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine,
+ (gchar *)&sdt->header.signature, ext);
+ if (getenv("V")) {
+ fprintf(stderr, "Looking for expected file '%s'\n", aml_file);
+ }
+ if (g_file_test(aml_file, G_FILE_TEST_EXISTS)) {
+ exp_sdt.aml_file = aml_file;
+ } else if (*ext != '\0') {
+ /* try fallback to generic (extension less) expected file */
+ ext = "";
+ g_free(aml_file);
+ goto try_again;
+ }
+ g_assert(exp_sdt.aml_file);
+ if (getenv("V")) {
+ fprintf(stderr, "Using expected file '%s'\n", aml_file);
+ }
+ ret = g_file_get_contents(aml_file, &exp_sdt.aml,
+ &exp_sdt.aml_len, &error);
+ g_assert(ret);
+ g_assert_no_error(error);
+ g_assert(exp_sdt.aml);
+ g_assert(exp_sdt.aml_len);
+
+ g_array_append_val(exp_tables, exp_sdt);
+ }
+
+ return exp_tables;
+}
+
+/* test the list of tables in @data->tables against reference tables */
+static void test_acpi_asl(test_data *data)
+{
+ int i;
+ AcpiSdtTable *sdt, *exp_sdt;
+ test_data exp_data;
+ gboolean exp_err, err;
+
+ memset(&exp_data, 0, sizeof(exp_data));
+ exp_data.tables = load_expected_aml(data);
+ dump_aml_files(data, false);
+ for (i = 0; i < data->tables->len; ++i) {
+ GString *asl, *exp_asl;
+
+ sdt = &g_array_index(data->tables, AcpiSdtTable, i);
+ exp_sdt = &g_array_index(exp_data.tables, AcpiSdtTable, i);
+
+ err = load_asl(data->tables, sdt);
+ asl = normalize_asl(sdt->asl);
+
+ exp_err = load_asl(exp_data.tables, exp_sdt);
+ exp_asl = normalize_asl(exp_sdt->asl);
+
+ /* TODO: check for warnings */
+ g_assert(!err || exp_err);
+
+ if (g_strcmp0(asl->str, exp_asl->str)) {
+ if (exp_err) {
+ fprintf(stderr,
+ "Warning! iasl couldn't parse the expected aml\n");
+ } else {
+ uint32_t signature = cpu_to_le32(exp_sdt->header.signature);
+ sdt->tmp_files_retain = true;
+ exp_sdt->tmp_files_retain = true;
+ fprintf(stderr,
+ "acpi-test: Warning! %.4s mismatch. "
+ "Actual [asl:%s, aml:%s], Expected [asl:%s, aml:%s].\n",
+ (gchar *)&signature,
+ sdt->asl_file, sdt->aml_file,
+ exp_sdt->asl_file, exp_sdt->aml_file);
+ if (getenv("V")) {
+ const char *diff_cmd = getenv("DIFF");
+ if (diff_cmd) {
+ int ret G_GNUC_UNUSED;
+ char *diff = g_strdup_printf("%s %s %s", diff_cmd,
+ exp_sdt->asl_file, sdt->asl_file);
+ ret = system(diff) ;
+ g_free(diff);
+ } else {
+ fprintf(stderr, "acpi-test: Warning. not showing "
+ "difference since no diff utility is specified. "
+ "Set 'DIFF' environment variable to a preferred "
+ "diff utility and run 'make V=1 check' again to "
+ "see ASL difference.");
+ }
+ }
+ }
+ }
+ g_string_free(asl, true);
+ g_string_free(exp_asl, true);
+ }
+
+ free_test_data(&exp_data);
+}
+
+static bool smbios_ep_table_ok(test_data *data)
+{
+ struct smbios_21_entry_point *ep_table = &data->smbios_ep_table;
+ uint32_t addr = data->smbios_ep_addr;
+
+ ACPI_READ_ARRAY(data->qts, ep_table->anchor_string, addr);
+ if (memcmp(ep_table->anchor_string, "_SM_", 4)) {
+ return false;
+ }
+ ACPI_READ_FIELD(data->qts, ep_table->checksum, addr);
+ ACPI_READ_FIELD(data->qts, ep_table->length, addr);
+ ACPI_READ_FIELD(data->qts, ep_table->smbios_major_version, addr);
+ ACPI_READ_FIELD(data->qts, ep_table->smbios_minor_version, addr);
+ ACPI_READ_FIELD(data->qts, ep_table->max_structure_size, addr);
+ ACPI_READ_FIELD(data->qts, ep_table->entry_point_revision, addr);
+ ACPI_READ_ARRAY(data->qts, ep_table->formatted_area, addr);
+ ACPI_READ_ARRAY(data->qts, ep_table->intermediate_anchor_string, addr);
+ if (memcmp(ep_table->intermediate_anchor_string, "_DMI_", 5)) {
+ return false;
+ }
+ ACPI_READ_FIELD(data->qts, ep_table->intermediate_checksum, addr);
+ ACPI_READ_FIELD(data->qts, ep_table->structure_table_length, addr);
+ if (ep_table->structure_table_length == 0) {
+ return false;
+ }
+ ACPI_READ_FIELD(data->qts, ep_table->structure_table_address, addr);
+ ACPI_READ_FIELD(data->qts, ep_table->number_of_structures, addr);
+ if (ep_table->number_of_structures == 0) {
+ return false;
+ }
+ ACPI_READ_FIELD(data->qts, ep_table->smbios_bcd_revision, addr);
+ if (acpi_calc_checksum((uint8_t *)ep_table, sizeof *ep_table) ||
+ acpi_calc_checksum((uint8_t *)ep_table + 0x10,
+ sizeof *ep_table - 0x10)) {
+ return false;
+ }
+ return true;
+}
+
+static void test_smbios_entry_point(test_data *data)
+{
+ uint32_t off;
+
+ /* find smbios entry point structure */
+ for (off = 0xf0000; off < 0x100000; off += 0x10) {
+ uint8_t sig[] = "_SM_";
+ int i;
+
+ for (i = 0; i < sizeof sig - 1; ++i) {
+ sig[i] = qtest_readb(data->qts, off + i);
+ }
+
+ if (!memcmp(sig, "_SM_", sizeof sig)) {
+ /* signature match, but is this a valid entry point? */
+ data->smbios_ep_addr = off;
+ if (smbios_ep_table_ok(data)) {
+ break;
+ }
+ }
+ }
+
+ g_assert_cmphex(off, <, 0x100000);
+}
+
+static inline bool smbios_single_instance(uint8_t type)
+{
+ switch (type) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 16:
+ case 32:
+ case 127:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static void test_smbios_structs(test_data *data)
+{
+ DECLARE_BITMAP(struct_bitmap, SMBIOS_MAX_TYPE+1) = { 0 };
+ struct smbios_21_entry_point *ep_table = &data->smbios_ep_table;
+ uint32_t addr = le32_to_cpu(ep_table->structure_table_address);
+ int i, len, max_len = 0;
+ uint8_t type, prv, crt;
+
+ /* walk the smbios tables */
+ for (i = 0; i < le16_to_cpu(ep_table->number_of_structures); i++) {
+
+ /* grab type and formatted area length from struct header */
+ type = qtest_readb(data->qts, addr);
+ g_assert_cmpuint(type, <=, SMBIOS_MAX_TYPE);
+ len = qtest_readb(data->qts, addr + 1);
+
+ /* single-instance structs must not have been encountered before */
+ if (smbios_single_instance(type)) {
+ g_assert(!test_bit(type, struct_bitmap));
+ }
+ set_bit(type, struct_bitmap);
+
+ /* seek to end of unformatted string area of this struct ("\0\0") */
+ prv = crt = 1;
+ while (prv || crt) {
+ prv = crt;
+ crt = qtest_readb(data->qts, addr + len);
+ len++;
+ }
+
+ /* keep track of max. struct size */
+ if (max_len < len) {
+ max_len = len;
+ g_assert_cmpuint(max_len, <=, ep_table->max_structure_size);
+ }
+
+ /* start of next structure */
+ addr += len;
+ }
+
+ /* total table length and max struct size must match entry point values */
+ g_assert_cmpuint(le16_to_cpu(ep_table->structure_table_length), ==,
+ addr - le32_to_cpu(ep_table->structure_table_address));
+ g_assert_cmpuint(le16_to_cpu(ep_table->max_structure_size), ==, max_len);
+
+ /* required struct types must all be present */
+ for (i = 0; i < data->required_struct_types_len; i++) {
+ g_assert(test_bit(data->required_struct_types[i], struct_bitmap));
+ }
+}
+
+static void test_acpi_one(const char *params, test_data *data)
+{
+ char *args;
+
+ /* Disable kernel irqchip to be able to override apic irq0. */
+ args = g_strdup_printf("-machine %s,accel=%s,kernel-irqchip=off "
+ "-net none -display none %s "
+ "-drive id=hd0,if=none,file=%s,format=raw "
+ "-device ide-hd,drive=hd0 ",
+ data->machine, "kvm:tcg",
+ params ? params : "", disk);
+
+ data->qts = qtest_init(args);
+
+ boot_sector_test(data->qts);
+
+ data->tables = g_array_new(false, true, sizeof(AcpiSdtTable));
+ test_acpi_rsdp_address(data);
+ test_acpi_rsdp_table(data);
+ test_acpi_rsdt_table(data);
+ fadt_fetch_facs_and_dsdt_ptrs(data);
+ test_acpi_facs_table(data);
+ test_acpi_dsdt_table(data);
+ fetch_rsdt_referenced_tables(data);
+
+ sanitize_fadt_ptrs(data);
+
+ if (iasl) {
+ if (getenv(ACPI_REBUILD_EXPECTED_AML)) {
+ dump_aml_files(data, true);
+ } else {
+ test_acpi_asl(data);
+ }
+ }
+
+ test_smbios_entry_point(data);
+ test_smbios_structs(data);
+
+ assert(!global_qtest);
+ qtest_quit(data->qts);
+ g_free(args);
+}
+
+static uint8_t base_required_struct_types[] = {
+ 0, 1, 3, 4, 16, 17, 19, 32, 127
+};
+
+static void test_acpi_piix4_tcg(void)
+{
+ test_data data;
+
+ /* Supplying -machine accel argument overrides the default (qtest).
+ * This is to make guest actually run.
+ */
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
+ test_acpi_one(NULL, &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_piix4_tcg_bridge(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+ data.variant = ".bridge";
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
+ test_acpi_one("-device pci-bridge,chassis_nr=1", &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
+ test_acpi_one(NULL, &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_bridge(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.variant = ".bridge";
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
+ test_acpi_one("-device pci-bridge,chassis_nr=1",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_mmio64(void)
+{
+ test_data data = {
+ .machine = MACHINE_Q35,
+ .variant = ".mmio64",
+ .required_struct_types = base_required_struct_types,
+ .required_struct_types_len = ARRAY_SIZE(base_required_struct_types)
+ };
+
+ test_acpi_one("-m 128M,slots=1,maxmem=2G "
+ "-device pci-testdev,membar=2G",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_piix4_tcg_cphp(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+ data.variant = ".cphp";
+ test_acpi_one("-smp 2,cores=3,sockets=2,maxcpus=6"
+ " -numa node -numa node"
+ " -numa dist,src=0,dst=1,val=21",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_cphp(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.variant = ".cphp";
+ test_acpi_one(" -smp 2,cores=3,sockets=2,maxcpus=6"
+ " -numa node -numa node"
+ " -numa dist,src=0,dst=1,val=21",
+ &data);
+ free_test_data(&data);
+}
+
+static uint8_t ipmi_required_struct_types[] = {
+ 0, 1, 3, 4, 16, 17, 19, 32, 38, 127
+};
+
+static void test_acpi_q35_tcg_ipmi(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.variant = ".ipmibt";
+ data.required_struct_types = ipmi_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types);
+ test_acpi_one("-device ipmi-bmc-sim,id=bmc0"
+ " -device isa-ipmi-bt,bmc=bmc0",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_piix4_tcg_ipmi(void)
+{
+ test_data data;
+
+ /* Supplying -machine accel argument overrides the default (qtest).
+ * This is to make guest actually run.
+ */
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+ data.variant = ".ipmikcs";
+ data.required_struct_types = ipmi_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types);
+ test_acpi_one("-device ipmi-bmc-sim,id=bmc0"
+ " -device isa-ipmi-kcs,irq=0,bmc=bmc0",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_memhp(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.variant = ".memhp";
+ test_acpi_one(" -m 128,slots=3,maxmem=1G"
+ " -numa node -numa node"
+ " -numa dist,src=0,dst=1,val=21",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_piix4_tcg_memhp(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+ data.variant = ".memhp";
+ test_acpi_one(" -m 128,slots=3,maxmem=1G"
+ " -numa node -numa node"
+ " -numa dist,src=0,dst=1,val=21",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_numamem(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.variant = ".numamem";
+ test_acpi_one(" -numa node -numa node,mem=128", &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_piix4_tcg_numamem(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+ data.variant = ".numamem";
+ test_acpi_one(" -numa node -numa node,mem=128", &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_tcg_dimm_pxm(const char *machine)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = machine;
+ data.variant = ".dimmpxm";
+ test_acpi_one(" -machine nvdimm=on,nvdimm-persistence=cpu"
+ " -smp 4,sockets=4"
+ " -m 128M,slots=3,maxmem=1G"
+ " -numa node,mem=32M,nodeid=0"
+ " -numa node,mem=32M,nodeid=1"
+ " -numa node,mem=32M,nodeid=2"
+ " -numa node,mem=32M,nodeid=3"
+ " -numa cpu,node-id=0,socket-id=0"
+ " -numa cpu,node-id=1,socket-id=1"
+ " -numa cpu,node-id=2,socket-id=2"
+ " -numa cpu,node-id=3,socket-id=3"
+ " -object memory-backend-ram,id=ram0,size=128M"
+ " -object memory-backend-ram,id=nvm0,size=128M"
+ " -device pc-dimm,id=dimm0,memdev=ram0,node=1"
+ " -device nvdimm,id=dimm1,memdev=nvm0,node=2",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_dimm_pxm(void)
+{
+ test_acpi_tcg_dimm_pxm(MACHINE_Q35);
+}
+
+static void test_acpi_piix4_tcg_dimm_pxm(void)
+{
+ test_acpi_tcg_dimm_pxm(MACHINE_PC);
+}
+
+int main(int argc, char *argv[])
+{
+ const char *arch = qtest_get_arch();
+ int ret;
+
+ ret = boot_sector_init(disk);
+ if(ret)
+ return ret;
+
+ g_test_init(&argc, &argv, NULL);
+
+ if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
+ qtest_add_func("acpi/piix4", test_acpi_piix4_tcg);
+ qtest_add_func("acpi/piix4/bridge", test_acpi_piix4_tcg_bridge);
+ qtest_add_func("acpi/q35", test_acpi_q35_tcg);
+ qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge);
+ qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64);
+ qtest_add_func("acpi/piix4/ipmi", test_acpi_piix4_tcg_ipmi);
+ qtest_add_func("acpi/q35/ipmi", test_acpi_q35_tcg_ipmi);
+ qtest_add_func("acpi/piix4/cpuhp", test_acpi_piix4_tcg_cphp);
+ qtest_add_func("acpi/q35/cpuhp", test_acpi_q35_tcg_cphp);
+ qtest_add_func("acpi/piix4/memhp", test_acpi_piix4_tcg_memhp);
+ qtest_add_func("acpi/q35/memhp", test_acpi_q35_tcg_memhp);
+ qtest_add_func("acpi/piix4/numamem", test_acpi_piix4_tcg_numamem);
+ qtest_add_func("acpi/q35/numamem", test_acpi_q35_tcg_numamem);
+ qtest_add_func("acpi/piix4/dimmpxm", test_acpi_piix4_tcg_dimm_pxm);
+ qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm);
+ }
+ ret = g_test_run();
+ boot_sector_cleanup(disk);
+ return ret;
+}
new file mode 100644
new file mode 100644
@@ -0,0 +1,21 @@
+#!/usr/bin/python
+
+import os, re
+root = "tests/data/acpi"
+for machine in os.listdir(root):
+ machine_root = os.path.join(root, machine)
+ if not os.path.isdir(machine_root):
+ continue
+ files = os.listdir(machine_root):
+ for file in files:
+ if file.endswith(".dsl"):
+ continue
+ extension_prefix = "^[^.]*\."
+ if re.match(extension_prefix, file):
+ variant = re.sub(extension_prefix, "", file)
+
+
+for dirpath, dirnames, filenames in os.walk("tests/data/acpi"):
+ for file in files:
+ if file.endswith(".txt"):
+ print(os.path.join(root, file))
new file mode 100644
@@ -0,0 +1,56 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/microvm/APIC, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000046
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : D7
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 01 [I/O APIC]
+[035h 0053 1] Length : 0C
+[036h 0054 1] I/O Apic ID : 00
+[037h 0055 1] Reserved : 00
+[038h 0056 4] Address : FEC00000
+[03Ch 0060 4] Interrupt : 00000000
+
+[040h 0064 1] Subtable Type : 04 [Local APIC NMI]
+[041h 0065 1] Length : 06
+[042h 0066 1] Processor ID : FF
+[043h 0067 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[045h 0069 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 70 (0x46)
+
+ 0000: 41 50 49 43 46 00 00 00 01 D7 42 4F 43 48 53 20 // APICF.....BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................
+ 0040: 04 06 FF 00 00 01 // ......
new file mode 100644
@@ -0,0 +1,121 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/microvm/DSDT, Mon Sep 28 17:24:38 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000016D (365)
+ * Revision 0x02
+ * Checksum 0x62
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (_SB)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (GED)
+ {
+ Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
+ Name (_UID, "GED") // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000009,
+ }
+ })
+ OperationRegion (EREG, SystemMemory, 0xFEA00000, 0x04)
+ Field (EREG, DWordAcc, NoLock, WriteAsZeros)
+ {
+ ESEL, 32
+ }
+
+ Method (_EVT, 1, Serialized) // _EVT: Event
+ {
+ Local0 = ESEL /* \_SB_.GED_.ESEL */
+ If (((Local0 & 0x02) == 0x02))
+ {
+ Notify (PWRB, 0x80) // Status Change
+ }
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+
+ Device (VR07)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xFEB00E00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ 0x05,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+}
+
new file mode 100644
@@ -0,0 +1,196 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/microvm/FACP, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 0000010C
+[008h 0008 1] Revision : 05
+[009h 0009 1] Checksum : 7E
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 00
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0000
+[030h 0048 4] SMI Command Port : 00000000
+[034h 0052 1] ACPI Enable Value : 00
+[035h 0053 1] ACPI Disable Value : 00
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000000
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000000
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000000
+[050h 0080 4] GPE0 Block Address : 00000000
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 00
+[059h 0089 1] PM1 Control Block Length : 00
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 00
+[05Ch 0092 1] GPE0 Block Length : 00
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0000
+[062h 0098 2] C3 Latency : 0000
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 00
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 00100400
+ WBINVD instruction is operational (V1) : 0
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 0
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 0
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 0
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 0
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 1
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 00 [SystemMemory]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 00000000FEA00202
+
+[080h 0128 1] Value to cause reset : 42
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 00 [SystemMemory]
+[095h 0149 1] Bit Width : 00
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000000
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 00 [SystemMemory]
+[0ADh 0173 1] Bit Width : 00
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000000
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 00 [SystemMemory]
+[0D1h 0209 1] Bit Width : 00
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000000
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 00 [SystemMemory]
+[0DDh 0221 1] Bit Width : 00
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000000
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+[0F4h 0244 12] Sleep Control Register : [Generic Address Structure]
+[0F4h 0244 1] Space ID : 00 [SystemMemory]
+[0F5h 0245 1] Bit Width : 08
+[0F6h 0246 1] Bit Offset : 00
+[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0F8h 0248 8] Address : 00000000FEA00200
+
+[100h 0256 12] Sleep Status Register : [Generic Address Structure]
+[100h 0256 1] Space ID : 00 [SystemMemory]
+[101h 0257 1] Bit Width : 08
+[102h 0258 1] Bit Offset : 00
+[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
+[104h 0260 8] Address : 00000000FEA00201
+
+/**** ACPI table terminates in the middle of a data structure! (dump table) */
+
+Raw Table Data: Length 268 (0x10C)
+
+ 0000: 46 41 43 50 0C 01 00 00 05 7E 42 4F 43 48 53 20 // FACP.....~BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0070: 00 04 10 00 00 08 00 00 02 02 A0 FE 00 00 00 00 // ................
+ 0080: 42 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // B...............
+ 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00F0: 00 00 00 00 00 08 00 00 00 02 A0 FE 00 00 00 00 // ................
+ 0100: 00 08 00 00 01 02 A0 FE 00 00 00 00 // ............
new file mode 100644
@@ -0,0 +1,112 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/APIC.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000080
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : DA
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[03Ch 0060 1] Subtable Type : 01 [I/O APIC]
+[03Dh 0061 1] Length : 0C
+[03Eh 0062 1] I/O Apic ID : 00
+[03Fh 0063 1] Reserved : 00
+[040h 0064 4] Address : FEC00000
+[044h 0068 4] Interrupt : 00000000
+
+[048h 0072 1] Subtable Type : 02 [Interrupt Source Override]
+[049h 0073 1] Length : 0A
+[04Ah 0074 1] Bus : 00
+[04Bh 0075 1] Source : 00
+[04Ch 0076 4] Interrupt : 00000002
+[050h 0080 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[052h 0082 1] Subtable Type : 02 [Interrupt Source Override]
+[053h 0083 1] Length : 0A
+[054h 0084 1] Bus : 00
+[055h 0085 1] Source : 05
+[056h 0086 4] Interrupt : 00000005
+[05Ah 0090 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[05Ch 0092 1] Subtable Type : 02 [Interrupt Source Override]
+[05Dh 0093 1] Length : 0A
+[05Eh 0094 1] Bus : 00
+[05Fh 0095 1] Source : 09
+[060h 0096 4] Interrupt : 00000009
+[064h 0100 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[066h 0102 1] Subtable Type : 02 [Interrupt Source Override]
+[067h 0103 1] Length : 0A
+[068h 0104 1] Bus : 00
+[069h 0105 1] Source : 0A
+[06Ah 0106 4] Interrupt : 0000000A
+[06Eh 0110 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[070h 0112 1] Subtable Type : 02 [Interrupt Source Override]
+[071h 0113 1] Length : 0A
+[072h 0114 1] Bus : 00
+[073h 0115 1] Source : 0B
+[074h 0116 4] Interrupt : 0000000B
+[078h 0120 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[07Ah 0122 1] Subtable Type : 04 [Local APIC NMI]
+[07Bh 0123 1] Length : 06
+[07Ch 0124 1] Processor ID : FF
+[07Dh 0125 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[07Fh 0127 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 128 (0x80)
+
+ 0000: 41 50 49 43 80 00 00 00 01 DA 42 4F 43 48 53 20 // APIC......BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 00 08 01 01 01 00 00 00 01 0C 00 00 // ................
+ 0040: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................
+ 0050: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................
+ 0060: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................
+ 0070: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................
new file mode 100644
GIT binary patch
literal 120
zcmZ<^@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2jnsGfW!{`1CdNz
hKn!AlSgfo-nis_4<b<)ffC?aD+}vOm3)_F75db|X4FLcE
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,104 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/APIC.bridge, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000078
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : ED
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 01 [I/O APIC]
+[035h 0053 1] Length : 0C
+[036h 0054 1] I/O Apic ID : 00
+[037h 0055 1] Reserved : 00
+[038h 0056 4] Address : FEC00000
+[03Ch 0060 4] Interrupt : 00000000
+
+[040h 0064 1] Subtable Type : 02 [Interrupt Source Override]
+[041h 0065 1] Length : 0A
+[042h 0066 1] Bus : 00
+[043h 0067 1] Source : 00
+[044h 0068 4] Interrupt : 00000002
+[048h 0072 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override]
+[04Bh 0075 1] Length : 0A
+[04Ch 0076 1] Bus : 00
+[04Dh 0077 1] Source : 05
+[04Eh 0078 4] Interrupt : 00000005
+[052h 0082 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[054h 0084 1] Subtable Type : 02 [Interrupt Source Override]
+[055h 0085 1] Length : 0A
+[056h 0086 1] Bus : 00
+[057h 0087 1] Source : 09
+[058h 0088 4] Interrupt : 00000009
+[05Ch 0092 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override]
+[05Fh 0095 1] Length : 0A
+[060h 0096 1] Bus : 00
+[061h 0097 1] Source : 0A
+[062h 0098 4] Interrupt : 0000000A
+[066h 0102 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
+[069h 0105 1] Length : 0A
+[06Ah 0106 1] Bus : 00
+[06Bh 0107 1] Source : 0B
+[06Ch 0108 4] Interrupt : 0000000B
+[070h 0112 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[072h 0114 1] Subtable Type : 04 [Local APIC NMI]
+[073h 0115 1] Length : 06
+[074h 0116 1] Processor ID : FF
+[075h 0117 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[077h 0119 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 120 (0x78)
+
+ 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................
+ 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................
+ 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................
+ 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................
+ 0070: 0D 00 04 06 FF 00 00 01 // ........
new file mode 100644
@@ -0,0 +1,146 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/APIC.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 000000A0
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 7B
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[03Ch 0060 1] Subtable Type : 00 [Processor Local APIC]
+[03Dh 0061 1] Length : 08
+[03Eh 0062 1] Processor ID : 02
+[03Fh 0063 1] Local Apic ID : 02
+[040h 0064 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[044h 0068 1] Subtable Type : 00 [Processor Local APIC]
+[045h 0069 1] Length : 08
+[046h 0070 1] Processor ID : 03
+[047h 0071 1] Local Apic ID : 04
+[048h 0072 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[04Ch 0076 1] Subtable Type : 00 [Processor Local APIC]
+[04Dh 0077 1] Length : 08
+[04Eh 0078 1] Processor ID : 04
+[04Fh 0079 1] Local Apic ID : 05
+[050h 0080 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[054h 0084 1] Subtable Type : 00 [Processor Local APIC]
+[055h 0085 1] Length : 08
+[056h 0086 1] Processor ID : 05
+[057h 0087 1] Local Apic ID : 06
+[058h 0088 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[05Ch 0092 1] Subtable Type : 01 [I/O APIC]
+[05Dh 0093 1] Length : 0C
+[05Eh 0094 1] I/O Apic ID : 00
+[05Fh 0095 1] Reserved : 00
+[060h 0096 4] Address : FEC00000
+[064h 0100 4] Interrupt : 00000000
+
+[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
+[069h 0105 1] Length : 0A
+[06Ah 0106 1] Bus : 00
+[06Bh 0107 1] Source : 00
+[06Ch 0108 4] Interrupt : 00000002
+[070h 0112 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[072h 0114 1] Subtable Type : 02 [Interrupt Source Override]
+[073h 0115 1] Length : 0A
+[074h 0116 1] Bus : 00
+[075h 0117 1] Source : 05
+[076h 0118 4] Interrupt : 00000005
+[07Ah 0122 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[07Ch 0124 1] Subtable Type : 02 [Interrupt Source Override]
+[07Dh 0125 1] Length : 0A
+[07Eh 0126 1] Bus : 00
+[07Fh 0127 1] Source : 09
+[080h 0128 4] Interrupt : 00000009
+[084h 0132 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[086h 0134 1] Subtable Type : 02 [Interrupt Source Override]
+[087h 0135 1] Length : 0A
+[088h 0136 1] Bus : 00
+[089h 0137 1] Source : 0A
+[08Ah 0138 4] Interrupt : 0000000A
+[08Eh 0142 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[090h 0144 1] Subtable Type : 02 [Interrupt Source Override]
+[091h 0145 1] Length : 0A
+[092h 0146 1] Bus : 00
+[093h 0147 1] Source : 0B
+[094h 0148 4] Interrupt : 0000000B
+[098h 0152 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[09Ah 0154 1] Subtable Type : 04 [Local APIC NMI]
+[09Bh 0155 1] Length : 06
+[09Ch 0156 1] Processor ID : FF
+[09Dh 0157 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[09Fh 0159 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 160 (0xA0)
+
+ 0000: 41 50 49 43 A0 00 00 00 01 7B 42 4F 43 48 53 20 // APIC.....{BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 00 08 01 01 01 00 00 00 00 08 02 02 // ................
+ 0040: 00 00 00 00 00 08 03 04 00 00 00 00 00 08 04 05 // ................
+ 0050: 00 00 00 00 00 08 05 06 00 00 00 00 01 0C 00 00 // ................
+ 0060: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................
+ 0070: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................
+ 0080: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................
+ 0090: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................
new file mode 100644
@@ -0,0 +1,129 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/APIC.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000090
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : AE
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[03Ch 0060 1] Subtable Type : 00 [Processor Local APIC]
+[03Dh 0061 1] Length : 08
+[03Eh 0062 1] Processor ID : 02
+[03Fh 0063 1] Local Apic ID : 02
+[040h 0064 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[044h 0068 1] Subtable Type : 00 [Processor Local APIC]
+[045h 0069 1] Length : 08
+[046h 0070 1] Processor ID : 03
+[047h 0071 1] Local Apic ID : 03
+[048h 0072 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[04Ch 0076 1] Subtable Type : 01 [I/O APIC]
+[04Dh 0077 1] Length : 0C
+[04Eh 0078 1] I/O Apic ID : 00
+[04Fh 0079 1] Reserved : 00
+[050h 0080 4] Address : FEC00000
+[054h 0084 4] Interrupt : 00000000
+
+[058h 0088 1] Subtable Type : 02 [Interrupt Source Override]
+[059h 0089 1] Length : 0A
+[05Ah 0090 1] Bus : 00
+[05Bh 0091 1] Source : 00
+[05Ch 0092 4] Interrupt : 00000002
+[060h 0096 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[062h 0098 1] Subtable Type : 02 [Interrupt Source Override]
+[063h 0099 1] Length : 0A
+[064h 0100 1] Bus : 00
+[065h 0101 1] Source : 05
+[066h 0102 4] Interrupt : 00000005
+[06Ah 0106 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[06Ch 0108 1] Subtable Type : 02 [Interrupt Source Override]
+[06Dh 0109 1] Length : 0A
+[06Eh 0110 1] Bus : 00
+[06Fh 0111 1] Source : 09
+[070h 0112 4] Interrupt : 00000009
+[074h 0116 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[076h 0118 1] Subtable Type : 02 [Interrupt Source Override]
+[077h 0119 1] Length : 0A
+[078h 0120 1] Bus : 00
+[079h 0121 1] Source : 0A
+[07Ah 0122 4] Interrupt : 0000000A
+[07Eh 0126 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[080h 0128 1] Subtable Type : 02 [Interrupt Source Override]
+[081h 0129 1] Length : 0A
+[082h 0130 1] Bus : 00
+[083h 0131 1] Source : 0B
+[084h 0132 4] Interrupt : 0000000B
+[088h 0136 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[08Ah 0138 1] Subtable Type : 04 [Local APIC NMI]
+[08Bh 0139 1] Length : 06
+[08Ch 0140 1] Processor ID : FF
+[08Dh 0141 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[08Fh 0143 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 144 (0x90)
+
+ 0000: 41 50 49 43 90 00 00 00 01 AE 42 4F 43 48 53 20 // APIC......BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 00 08 01 01 01 00 00 00 00 08 02 02 // ................
+ 0040: 01 00 00 00 00 08 03 03 01 00 00 00 01 0C 00 00 // ................
+ 0050: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................
+ 0060: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................
+ 0070: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................
+ 0080: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................
new file mode 100644
@@ -0,0 +1,104 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/APIC.roothp, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000078
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : ED
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 01 [I/O APIC]
+[035h 0053 1] Length : 0C
+[036h 0054 1] I/O Apic ID : 00
+[037h 0055 1] Reserved : 00
+[038h 0056 4] Address : FEC00000
+[03Ch 0060 4] Interrupt : 00000000
+
+[040h 0064 1] Subtable Type : 02 [Interrupt Source Override]
+[041h 0065 1] Length : 0A
+[042h 0066 1] Bus : 00
+[043h 0067 1] Source : 00
+[044h 0068 4] Interrupt : 00000002
+[048h 0072 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override]
+[04Bh 0075 1] Length : 0A
+[04Ch 0076 1] Bus : 00
+[04Dh 0077 1] Source : 05
+[04Eh 0078 4] Interrupt : 00000005
+[052h 0082 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[054h 0084 1] Subtable Type : 02 [Interrupt Source Override]
+[055h 0085 1] Length : 0A
+[056h 0086 1] Bus : 00
+[057h 0087 1] Source : 09
+[058h 0088 4] Interrupt : 00000009
+[05Ch 0092 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override]
+[05Fh 0095 1] Length : 0A
+[060h 0096 1] Bus : 00
+[061h 0097 1] Source : 0A
+[062h 0098 4] Interrupt : 0000000A
+[066h 0102 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
+[069h 0105 1] Length : 0A
+[06Ah 0106 1] Bus : 00
+[06Bh 0107 1] Source : 0B
+[06Ch 0108 4] Interrupt : 0000000B
+[070h 0112 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[072h 0114 1] Subtable Type : 04 [Local APIC NMI]
+[073h 0115 1] Length : 06
+[074h 0116 1] Processor ID : FF
+[075h 0117 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[077h 0119 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 120 (0x78)
+
+ 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................
+ 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................
+ 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................
+ 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................
+ 0070: 0D 00 04 06 FF 00 00 01 // ........
new file mode 100644
GIT binary patch
literal 120
zcmZ<^@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2jnsGfW!{`1CdNz
hKn!AlSgfo-nis_4<b<)ffC?aD+}vOm3)_F75db|X4FLcE
literal 0
HcmV?d00001
new file mode 100644
GIT binary patch
literal 120
zcmZ<^@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2jnsGfW!{`1CdNz
hKn!AlSgfo-nis_4<b<)ffC?aD+}vOm3)_F75db|X4FLcE
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,104 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/APIC.ipmikcs, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000078
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : ED
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 01 [I/O APIC]
+[035h 0053 1] Length : 0C
+[036h 0054 1] I/O Apic ID : 00
+[037h 0055 1] Reserved : 00
+[038h 0056 4] Address : FEC00000
+[03Ch 0060 4] Interrupt : 00000000
+
+[040h 0064 1] Subtable Type : 02 [Interrupt Source Override]
+[041h 0065 1] Length : 0A
+[042h 0066 1] Bus : 00
+[043h 0067 1] Source : 00
+[044h 0068 4] Interrupt : 00000002
+[048h 0072 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override]
+[04Bh 0075 1] Length : 0A
+[04Ch 0076 1] Bus : 00
+[04Dh 0077 1] Source : 05
+[04Eh 0078 4] Interrupt : 00000005
+[052h 0082 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[054h 0084 1] Subtable Type : 02 [Interrupt Source Override]
+[055h 0085 1] Length : 0A
+[056h 0086 1] Bus : 00
+[057h 0087 1] Source : 09
+[058h 0088 4] Interrupt : 00000009
+[05Ch 0092 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override]
+[05Fh 0095 1] Length : 0A
+[060h 0096 1] Bus : 00
+[061h 0097 1] Source : 0A
+[062h 0098 4] Interrupt : 0000000A
+[066h 0102 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
+[069h 0105 1] Length : 0A
+[06Ah 0106 1] Bus : 00
+[06Bh 0107 1] Source : 0B
+[06Ch 0108 4] Interrupt : 0000000B
+[070h 0112 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[072h 0114 1] Subtable Type : 04 [Local APIC NMI]
+[073h 0115 1] Length : 06
+[074h 0116 1] Processor ID : FF
+[075h 0117 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[077h 0119 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 120 (0x78)
+
+ 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................
+ 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................
+ 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................
+ 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................
+ 0070: 0D 00 04 06 FF 00 00 01 // ........
new file mode 100644
GIT binary patch
literal 120
zcmZ<^@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2jnsGfW!{`1CdNz
hKn!AlSgfo-nis_4<b<)ffC?aD+}vOm3)_F75db|X4FLcE
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,104 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/APIC.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000078
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : ED
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 01 [I/O APIC]
+[035h 0053 1] Length : 0C
+[036h 0054 1] I/O Apic ID : 00
+[037h 0055 1] Reserved : 00
+[038h 0056 4] Address : FEC00000
+[03Ch 0060 4] Interrupt : 00000000
+
+[040h 0064 1] Subtable Type : 02 [Interrupt Source Override]
+[041h 0065 1] Length : 0A
+[042h 0066 1] Bus : 00
+[043h 0067 1] Source : 00
+[044h 0068 4] Interrupt : 00000002
+[048h 0072 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override]
+[04Bh 0075 1] Length : 0A
+[04Ch 0076 1] Bus : 00
+[04Dh 0077 1] Source : 05
+[04Eh 0078 4] Interrupt : 00000005
+[052h 0082 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[054h 0084 1] Subtable Type : 02 [Interrupt Source Override]
+[055h 0085 1] Length : 0A
+[056h 0086 1] Bus : 00
+[057h 0087 1] Source : 09
+[058h 0088 4] Interrupt : 00000009
+[05Ch 0092 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override]
+[05Fh 0095 1] Length : 0A
+[060h 0096 1] Bus : 00
+[061h 0097 1] Source : 0A
+[062h 0098 4] Interrupt : 0000000A
+[066h 0102 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
+[069h 0105 1] Length : 0A
+[06Ah 0106 1] Bus : 00
+[06Bh 0107 1] Source : 0B
+[06Ch 0108 4] Interrupt : 0000000B
+[070h 0112 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[072h 0114 1] Subtable Type : 04 [Local APIC NMI]
+[073h 0115 1] Length : 06
+[074h 0116 1] Processor ID : FF
+[075h 0117 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[077h 0119 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 120 (0x78)
+
+ 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................
+ 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................
+ 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................
+ 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................
+ 0070: 0D 00 04 06 FF 00 00 01 // ........
new file mode 100644
GIT binary patch
literal 120
zcmZ<^@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2jnsGfW!{`1CdNz
hKn!AlSgfo-nis_4<b<)ffC?aD+}vOm3)_F75db|X4FLcE
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,104 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/APIC.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000078
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : ED
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 01 [I/O APIC]
+[035h 0053 1] Length : 0C
+[036h 0054 1] I/O Apic ID : 00
+[037h 0055 1] Reserved : 00
+[038h 0056 4] Address : FEC00000
+[03Ch 0060 4] Interrupt : 00000000
+
+[040h 0064 1] Subtable Type : 02 [Interrupt Source Override]
+[041h 0065 1] Length : 0A
+[042h 0066 1] Bus : 00
+[043h 0067 1] Source : 00
+[044h 0068 4] Interrupt : 00000002
+[048h 0072 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override]
+[04Bh 0075 1] Length : 0A
+[04Ch 0076 1] Bus : 00
+[04Dh 0077 1] Source : 05
+[04Eh 0078 4] Interrupt : 00000005
+[052h 0082 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[054h 0084 1] Subtable Type : 02 [Interrupt Source Override]
+[055h 0085 1] Length : 0A
+[056h 0086 1] Bus : 00
+[057h 0087 1] Source : 09
+[058h 0088 4] Interrupt : 00000009
+[05Ch 0092 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override]
+[05Fh 0095 1] Length : 0A
+[060h 0096 1] Bus : 00
+[061h 0097 1] Source : 0A
+[062h 0098 4] Interrupt : 0000000A
+[066h 0102 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
+[069h 0105 1] Length : 0A
+[06Ah 0106 1] Bus : 00
+[06Bh 0107 1] Source : 0B
+[06Ch 0108 4] Interrupt : 0000000B
+[070h 0112 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[072h 0114 1] Subtable Type : 04 [Local APIC NMI]
+[073h 0115 1] Length : 06
+[074h 0116 1] Processor ID : FF
+[075h 0117 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[077h 0119 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 120 (0x78)
+
+ 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................
+ 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................
+ 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................
+ 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................
+ 0070: 0D 00 04 06 FF 00 00 01 // ........
new file mode 100644
GIT binary patch
literal 120
zcmZ<^@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2jnsGfW!{`1CdNz
hKn!AlSgfo-nis_4<b<)ffC?aD+}vOm3)_F75db|X4FLcE
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,1619 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/pc/DSDT.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00001872 (6258)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x8E
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ OperationRegion (P40C, PCI_Config, 0x60, 0x04)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F2, // Range Minimum
+ 0x03F2, // Range Maximum
+ 0x00, // Alignment
+ 0x04, // Length
+ )
+ IO (Decode16,
+ 0x03F7, // Range Minimum
+ 0x03F7, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {6}
+ DMA (Compatibility, NotBusMaster, Transfer8, )
+ {2}
+ })
+ Device (FLPA)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information
+ {
+ Zero,
+ 0x05,
+ 0x4F,
+ 0x30,
+ One,
+ 0xAF,
+ 0x02,
+ 0x25,
+ 0x02,
+ 0x12,
+ 0x1B,
+ 0xFF,
+ 0x6C,
+ 0xF6,
+ 0x0F,
+ 0x08
+ })
+ }
+
+ Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate
+ {
+ /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0010 */ 0x02, 0x00, 0x00, 0x00 // ....
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ OperationRegion (PCST, SystemIO, 0xAE00, 0x08)
+ Field (PCST, DWordAcc, NoLock, WriteAsZeros)
+ {
+ PCIU, 32,
+ PCID, 32
+ }
+
+ OperationRegion (SEJ, SystemIO, 0xAE08, 0x04)
+ Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
+ {
+ B0EJ, 32
+ }
+
+ OperationRegion (BNMR, SystemIO, 0xAE10, 0x04)
+ Field (BNMR, DWordAcc, NoLock, WriteAsZeros)
+ {
+ BNUM, 32
+ }
+
+ Mutex (BLCK, 0x00)
+ Method (PCEJ, 2, NotSerialized)
+ {
+ Acquire (BLCK, 0xFFFF)
+ BNUM = Arg0
+ B0EJ = (One << Arg1)
+ Release (BLCK)
+ Return (Zero)
+ }
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Local0 = Package (0x80){}
+ Local1 = Zero
+ While ((Local1 < 0x80))
+ {
+ Local2 = (Local1 >> 0x02)
+ Local3 = ((Local1 + Local2) & 0x03)
+ If ((Local3 == Zero))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKD,
+ Zero
+ }
+ }
+
+ If ((Local3 == One))
+ {
+ If ((Local1 == 0x04))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKS,
+ Zero
+ }
+ }
+ Else
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKA,
+ Zero
+ }
+ }
+ }
+
+ If ((Local3 == 0x02))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKB,
+ Zero
+ }
+ }
+
+ If ((Local3 == 0x03))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKC,
+ Zero
+ }
+ }
+
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
+ Local4 [One] = (Local1 & 0x03)
+ Local0 [Local1] = Local4
+ Local1++
+ }
+
+ Return (Local0)
+ }
+ }
+
+ Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
+ {
+ PRQ0, 8,
+ PRQ1, 8,
+ PRQ2, 8,
+ PRQ3, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ If ((Arg0 < 0x80))
+ {
+ PRRI = Arg0
+ }
+
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ0))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ0 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ0))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ1))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ1 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ1))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ2))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ2 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ2))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ3))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ3 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ3))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKS)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000009,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0B)
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (_PRS) /* \_SB_.LNKS._PRS */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAF00, // Range Minimum
+ 0xAF00, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0xAF00, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (C001, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Device (\_SB.PCI0.MHPD)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "Memory hotplug resources") // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0A00, // Range Minimum
+ 0x0A00, // Range Maximum
+ 0x00, // Alignment
+ 0x18, // Length
+ )
+ })
+ OperationRegion (HPMR, SystemIO, 0x0A00, 0x18)
+ }
+
+ Device (\_SB.MHPC)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "DIMM devices") // _UID: Unique ID
+ Name (MDNR, 0x02)
+ Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MRBL, 32,
+ MRBH, 32,
+ MRLL, 32,
+ MRLH, 32,
+ MPX, 32
+ }
+
+ Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x14),
+ MES, 1,
+ MINS, 1,
+ MRMV, 1,
+ MEJ, 1
+ }
+
+ Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MSEL, 32,
+ MOEV, 32,
+ MOSC, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0B)
+ }
+
+ Mutex (MLCK, 0x00)
+ Method (MSCN, 0, NotSerialized)
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ While ((Local0 < MDNR))
+ {
+ MSEL = Local0
+ If ((MINS == One))
+ {
+ MTFY (Local0, One)
+ MINS = One
+ }
+ ElseIf ((MRMV == One))
+ {
+ MTFY (Local0, 0x03)
+ MRMV = One
+ }
+
+ Local0 += One
+ }
+
+ Release (MLCK)
+ Return (One)
+ }
+
+ Method (MRST, 1, NotSerialized)
+ {
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ If ((MES == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MCRS, 1, Serialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Name (MR64, ResourceTemplate ()
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Range Minimum
+ 0xFFFFFFFFFFFFFFFE, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0xFFFFFFFFFFFFFFFF, // Length
+ ,, _Y01, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address
+ CreateDWordField (MR64, 0x12, MINH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length
+ CreateDWordField (MR64, 0x2A, LENH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address
+ CreateDWordField (MR64, 0x1A, MAXH)
+ MINH = MRBH /* \_SB_.MHPC.MRBH */
+ MINL = MRBL /* \_SB_.MHPC.MRBL */
+ LENH = MRLH /* \_SB_.MHPC.MRLH */
+ LENL = MRLL /* \_SB_.MHPC.MRLL */
+ MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */
+ MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */
+ If ((MAXL < MINL))
+ {
+ MAXH += One
+ }
+
+ If ((MAXL < One))
+ {
+ MAXH -= One
+ }
+
+ MAXL -= One
+ If ((MAXH == Zero))
+ {
+ Name (MR32, ResourceTemplate ()
+ {
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0xFFFFFFFE, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xFFFFFFFF, // Length
+ ,, _Y02, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length
+ MIN = MINL /* \_SB_.MHPC.MCRS.MINL */
+ MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */
+ LEN = LENL /* \_SB_.MHPC.MCRS.LENL */
+ Release (MLCK)
+ Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */
+ }
+
+ Release (MLCK)
+ Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */
+ }
+
+ Method (MPXM, 1, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Local0 = MPX /* \_SB_.MHPC.MPX_ */
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MOST, 4, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MOEV = Arg1
+ MOSC = Arg2
+ Release (MLCK)
+ }
+
+ Method (MEJ0, 2, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MEJ = One
+ Release (MLCK)
+ }
+
+ Device (MP00)
+ {
+ Name (_UID, "0x00") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Device (MP01)
+ {
+ Name (_UID, "0x01") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Method (MTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (MP00, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (MP01, Arg1)
+ }
+ }
+ }
+
+ Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.MHPC.MSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ Acquire (\_SB.PCI0.BLCK, 0xFFFF)
+ \_SB.PCI0.PCNT ()
+ Release (\_SB.PCI0.BLCK)
+ }
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xF6C00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x00000001C0000000, // Range Minimum
+ 0x000000023FFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000080000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAFE0, // Range Minimum
+ 0xAFE0, // Range Maximum
+ 0x01, // Alignment
+ 0x04, // Length
+ )
+ })
+ }
+
+ Device (PHPR)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "PCI Hotplug resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAE00, // Range Minimum
+ 0xAE00, // Range Maximum
+ 0x01, // Alignment
+ 0x14, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (BSEL, Zero)
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S10)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Device (S18)
+ {
+ Name (_SUN, 0x03) // _SUN: Slot User Number
+ Name (_ADR, 0x00030000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S20)
+ {
+ Name (_SUN, 0x04) // _SUN: Slot User Number
+ Name (_ADR, 0x00040000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S28)
+ {
+ Name (_SUN, 0x05) // _SUN: Slot User Number
+ Name (_ADR, 0x00050000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S30)
+ {
+ Name (_SUN, 0x06) // _SUN: Slot User Number
+ Name (_ADR, 0x00060000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S38)
+ {
+ Name (_SUN, 0x07) // _SUN: Slot User Number
+ Name (_ADR, 0x00070000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S40)
+ {
+ Name (_SUN, 0x08) // _SUN: Slot User Number
+ Name (_ADR, 0x00080000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S48)
+ {
+ Name (_SUN, 0x09) // _SUN: Slot User Number
+ Name (_ADR, 0x00090000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S50)
+ {
+ Name (_SUN, 0x0A) // _SUN: Slot User Number
+ Name (_ADR, 0x000A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S58)
+ {
+ Name (_SUN, 0x0B) // _SUN: Slot User Number
+ Name (_ADR, 0x000B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S60)
+ {
+ Name (_SUN, 0x0C) // _SUN: Slot User Number
+ Name (_ADR, 0x000C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S68)
+ {
+ Name (_SUN, 0x0D) // _SUN: Slot User Number
+ Name (_ADR, 0x000D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S70)
+ {
+ Name (_SUN, 0x0E) // _SUN: Slot User Number
+ Name (_ADR, 0x000E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S78)
+ {
+ Name (_SUN, 0x0F) // _SUN: Slot User Number
+ Name (_ADR, 0x000F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S80)
+ {
+ Name (_SUN, 0x10) // _SUN: Slot User Number
+ Name (_ADR, 0x00100000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S88)
+ {
+ Name (_SUN, 0x11) // _SUN: Slot User Number
+ Name (_ADR, 0x00110000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S90)
+ {
+ Name (_SUN, 0x12) // _SUN: Slot User Number
+ Name (_ADR, 0x00120000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S98)
+ {
+ Name (_SUN, 0x13) // _SUN: Slot User Number
+ Name (_ADR, 0x00130000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA0)
+ {
+ Name (_SUN, 0x14) // _SUN: Slot User Number
+ Name (_ADR, 0x00140000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA8)
+ {
+ Name (_SUN, 0x15) // _SUN: Slot User Number
+ Name (_ADR, 0x00150000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB0)
+ {
+ Name (_SUN, 0x16) // _SUN: Slot User Number
+ Name (_ADR, 0x00160000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB8)
+ {
+ Name (_SUN, 0x17) // _SUN: Slot User Number
+ Name (_ADR, 0x00170000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC0)
+ {
+ Name (_SUN, 0x18) // _SUN: Slot User Number
+ Name (_ADR, 0x00180000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC8)
+ {
+ Name (_SUN, 0x19) // _SUN: Slot User Number
+ Name (_ADR, 0x00190000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD0)
+ {
+ Name (_SUN, 0x1A) // _SUN: Slot User Number
+ Name (_ADR, 0x001A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD8)
+ {
+ Name (_SUN, 0x1B) // _SUN: Slot User Number
+ Name (_ADR, 0x001B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE0)
+ {
+ Name (_SUN, 0x1C) // _SUN: Slot User Number
+ Name (_ADR, 0x001C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE8)
+ {
+ Name (_SUN, 0x1D) // _SUN: Slot User Number
+ Name (_ADR, 0x001D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF0)
+ {
+ Name (_SUN, 0x1E) // _SUN: Slot User Number
+ Name (_ADR, 0x001E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF8)
+ {
+ Name (_SUN, 0x1F) // _SUN: Slot User Number
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Method (DVNT, 2, NotSerialized)
+ {
+ If ((Arg0 & 0x08))
+ {
+ Notify (S18, Arg1)
+ }
+
+ If ((Arg0 & 0x10))
+ {
+ Notify (S20, Arg1)
+ }
+
+ If ((Arg0 & 0x20))
+ {
+ Notify (S28, Arg1)
+ }
+
+ If ((Arg0 & 0x40))
+ {
+ Notify (S30, Arg1)
+ }
+
+ If ((Arg0 & 0x80))
+ {
+ Notify (S38, Arg1)
+ }
+
+ If ((Arg0 & 0x0100))
+ {
+ Notify (S40, Arg1)
+ }
+
+ If ((Arg0 & 0x0200))
+ {
+ Notify (S48, Arg1)
+ }
+
+ If ((Arg0 & 0x0400))
+ {
+ Notify (S50, Arg1)
+ }
+
+ If ((Arg0 & 0x0800))
+ {
+ Notify (S58, Arg1)
+ }
+
+ If ((Arg0 & 0x1000))
+ {
+ Notify (S60, Arg1)
+ }
+
+ If ((Arg0 & 0x2000))
+ {
+ Notify (S68, Arg1)
+ }
+
+ If ((Arg0 & 0x4000))
+ {
+ Notify (S70, Arg1)
+ }
+
+ If ((Arg0 & 0x8000))
+ {
+ Notify (S78, Arg1)
+ }
+
+ If ((Arg0 & 0x00010000))
+ {
+ Notify (S80, Arg1)
+ }
+
+ If ((Arg0 & 0x00020000))
+ {
+ Notify (S88, Arg1)
+ }
+
+ If ((Arg0 & 0x00040000))
+ {
+ Notify (S90, Arg1)
+ }
+
+ If ((Arg0 & 0x00080000))
+ {
+ Notify (S98, Arg1)
+ }
+
+ If ((Arg0 & 0x00100000))
+ {
+ Notify (SA0, Arg1)
+ }
+
+ If ((Arg0 & 0x00200000))
+ {
+ Notify (SA8, Arg1)
+ }
+
+ If ((Arg0 & 0x00400000))
+ {
+ Notify (SB0, Arg1)
+ }
+
+ If ((Arg0 & 0x00800000))
+ {
+ Notify (SB8, Arg1)
+ }
+
+ If ((Arg0 & 0x01000000))
+ {
+ Notify (SC0, Arg1)
+ }
+
+ If ((Arg0 & 0x02000000))
+ {
+ Notify (SC8, Arg1)
+ }
+
+ If ((Arg0 & 0x04000000))
+ {
+ Notify (SD0, Arg1)
+ }
+
+ If ((Arg0 & 0x08000000))
+ {
+ Notify (SD8, Arg1)
+ }
+
+ If ((Arg0 & 0x10000000))
+ {
+ Notify (SE0, Arg1)
+ }
+
+ If ((Arg0 & 0x20000000))
+ {
+ Notify (SE8, Arg1)
+ }
+
+ If ((Arg0 & 0x40000000))
+ {
+ Notify (SF0, Arg1)
+ }
+
+ If ((Arg0 & 0x80000000))
+ {
+ Notify (SF8, Arg1)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ BNUM = Zero
+ DVNT (PCIU, One)
+ DVNT (PCID, 0x03)
+ }
+ }
+ }
+}
+
new file mode 100644
@@ -0,0 +1,1800 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/pc/DSDT.bridge, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00001A89 (6793)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x09
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ OperationRegion (P40C, PCI_Config, 0x60, 0x04)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F2, // Range Minimum
+ 0x03F2, // Range Maximum
+ 0x00, // Alignment
+ 0x04, // Length
+ )
+ IO (Decode16,
+ 0x03F7, // Range Minimum
+ 0x03F7, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {6}
+ DMA (Compatibility, NotBusMaster, Transfer8, )
+ {2}
+ })
+ Device (FLPA)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information
+ {
+ Zero,
+ 0x05,
+ 0x4F,
+ 0x30,
+ One,
+ 0xAF,
+ 0x02,
+ 0x25,
+ 0x02,
+ 0x12,
+ 0x1B,
+ 0xFF,
+ 0x6C,
+ 0xF6,
+ 0x0F,
+ 0x08
+ })
+ }
+
+ Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate
+ {
+ /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0010 */ 0x02, 0x00, 0x00, 0x00 // ....
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ OperationRegion (PCST, SystemIO, 0xAE00, 0x08)
+ Field (PCST, DWordAcc, NoLock, WriteAsZeros)
+ {
+ PCIU, 32,
+ PCID, 32
+ }
+
+ OperationRegion (SEJ, SystemIO, 0xAE08, 0x04)
+ Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
+ {
+ B0EJ, 32
+ }
+
+ OperationRegion (BNMR, SystemIO, 0xAE10, 0x04)
+ Field (BNMR, DWordAcc, NoLock, WriteAsZeros)
+ {
+ BNUM, 32
+ }
+
+ Mutex (BLCK, 0x00)
+ Method (PCEJ, 2, NotSerialized)
+ {
+ Acquire (BLCK, 0xFFFF)
+ BNUM = Arg0
+ B0EJ = (One << Arg1)
+ Release (BLCK)
+ Return (Zero)
+ }
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Local0 = Package (0x80){}
+ Local1 = Zero
+ While ((Local1 < 0x80))
+ {
+ Local2 = (Local1 >> 0x02)
+ Local3 = ((Local1 + Local2) & 0x03)
+ If ((Local3 == Zero))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKD,
+ Zero
+ }
+ }
+
+ If ((Local3 == One))
+ {
+ If ((Local1 == 0x04))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKS,
+ Zero
+ }
+ }
+ Else
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKA,
+ Zero
+ }
+ }
+ }
+
+ If ((Local3 == 0x02))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKB,
+ Zero
+ }
+ }
+
+ If ((Local3 == 0x03))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKC,
+ Zero
+ }
+ }
+
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
+ Local4 [One] = (Local1 & 0x03)
+ Local0 [Local1] = Local4
+ Local1++
+ }
+
+ Return (Local0)
+ }
+ }
+
+ Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
+ {
+ PRQ0, 8,
+ PRQ1, 8,
+ PRQ2, 8,
+ PRQ3, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ If ((Arg0 < 0x80))
+ {
+ PRRI = Arg0
+ }
+
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ0))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ0 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ0))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ1))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ1 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ1))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ2))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ2 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ2))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ3))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ3 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ3))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKS)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000009,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0B)
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (_PRS) /* \_SB_.LNKS._PRS */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAF00, // Range Minimum
+ 0xAF00, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0xAF00, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ Acquire (\_SB.PCI0.BLCK, 0xFFFF)
+ \_SB.PCI0.PCNT ()
+ Release (\_SB.PCI0.BLCK)
+ }
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xF6C00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000100000000, // Range Minimum
+ 0x000000017FFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000080000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAFE0, // Range Minimum
+ 0xAFE0, // Range Maximum
+ 0x01, // Alignment
+ 0x04, // Length
+ )
+ })
+ }
+
+ Device (PHPR)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "PCI Hotplug resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAE00, // Range Minimum
+ 0xAE00, // Range Maximum
+ 0x01, // Alignment
+ 0x14, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (BSEL, Zero)
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S10)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Device (S18)
+ {
+ Name (_ADR, 0x00030000) // _ADR: Address
+ Name (BSEL, One)
+ Device (S00)
+ {
+ Name (_SUN, Zero) // _SUN: Slot User Number
+ Name (_ADR, Zero) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S08)
+ {
+ Name (_SUN, One) // _SUN: Slot User Number
+ Name (_ADR, 0x00010000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S10)
+ {
+ Name (_SUN, 0x02) // _SUN: Slot User Number
+ Name (_ADR, 0x00020000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S18)
+ {
+ Name (_SUN, 0x03) // _SUN: Slot User Number
+ Name (_ADR, 0x00030000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S20)
+ {
+ Name (_SUN, 0x04) // _SUN: Slot User Number
+ Name (_ADR, 0x00040000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S28)
+ {
+ Name (_SUN, 0x05) // _SUN: Slot User Number
+ Name (_ADR, 0x00050000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S30)
+ {
+ Name (_SUN, 0x06) // _SUN: Slot User Number
+ Name (_ADR, 0x00060000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S38)
+ {
+ Name (_SUN, 0x07) // _SUN: Slot User Number
+ Name (_ADR, 0x00070000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S40)
+ {
+ Name (_SUN, 0x08) // _SUN: Slot User Number
+ Name (_ADR, 0x00080000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S48)
+ {
+ Name (_SUN, 0x09) // _SUN: Slot User Number
+ Name (_ADR, 0x00090000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S50)
+ {
+ Name (_SUN, 0x0A) // _SUN: Slot User Number
+ Name (_ADR, 0x000A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S58)
+ {
+ Name (_SUN, 0x0B) // _SUN: Slot User Number
+ Name (_ADR, 0x000B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S60)
+ {
+ Name (_SUN, 0x0C) // _SUN: Slot User Number
+ Name (_ADR, 0x000C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S68)
+ {
+ Name (_SUN, 0x0D) // _SUN: Slot User Number
+ Name (_ADR, 0x000D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S70)
+ {
+ Name (_SUN, 0x0E) // _SUN: Slot User Number
+ Name (_ADR, 0x000E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S78)
+ {
+ Name (_SUN, 0x0F) // _SUN: Slot User Number
+ Name (_ADR, 0x000F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S80)
+ {
+ Name (_SUN, 0x10) // _SUN: Slot User Number
+ Name (_ADR, 0x00100000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S88)
+ {
+ Name (_SUN, 0x11) // _SUN: Slot User Number
+ Name (_ADR, 0x00110000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S90)
+ {
+ Name (_SUN, 0x12) // _SUN: Slot User Number
+ Name (_ADR, 0x00120000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S98)
+ {
+ Name (_SUN, 0x13) // _SUN: Slot User Number
+ Name (_ADR, 0x00130000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA0)
+ {
+ Name (_SUN, 0x14) // _SUN: Slot User Number
+ Name (_ADR, 0x00140000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA8)
+ {
+ Name (_SUN, 0x15) // _SUN: Slot User Number
+ Name (_ADR, 0x00150000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB0)
+ {
+ Name (_SUN, 0x16) // _SUN: Slot User Number
+ Name (_ADR, 0x00160000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB8)
+ {
+ Name (_SUN, 0x17) // _SUN: Slot User Number
+ Name (_ADR, 0x00170000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC0)
+ {
+ Name (_SUN, 0x18) // _SUN: Slot User Number
+ Name (_ADR, 0x00180000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC8)
+ {
+ Name (_SUN, 0x19) // _SUN: Slot User Number
+ Name (_ADR, 0x00190000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD0)
+ {
+ Name (_SUN, 0x1A) // _SUN: Slot User Number
+ Name (_ADR, 0x001A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD8)
+ {
+ Name (_SUN, 0x1B) // _SUN: Slot User Number
+ Name (_ADR, 0x001B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE0)
+ {
+ Name (_SUN, 0x1C) // _SUN: Slot User Number
+ Name (_ADR, 0x001C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE8)
+ {
+ Name (_SUN, 0x1D) // _SUN: Slot User Number
+ Name (_ADR, 0x001D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF0)
+ {
+ Name (_SUN, 0x1E) // _SUN: Slot User Number
+ Name (_ADR, 0x001E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF8)
+ {
+ Name (_SUN, 0x1F) // _SUN: Slot User Number
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Method (DVNT, 2, NotSerialized)
+ {
+ If ((Arg0 & One))
+ {
+ Notify (S00, Arg1)
+ }
+
+ If ((Arg0 & 0x02))
+ {
+ Notify (S08, Arg1)
+ }
+
+ If ((Arg0 & 0x04))
+ {
+ Notify (S10, Arg1)
+ }
+
+ If ((Arg0 & 0x08))
+ {
+ Notify (S18, Arg1)
+ }
+
+ If ((Arg0 & 0x10))
+ {
+ Notify (S20, Arg1)
+ }
+
+ If ((Arg0 & 0x20))
+ {
+ Notify (S28, Arg1)
+ }
+
+ If ((Arg0 & 0x40))
+ {
+ Notify (S30, Arg1)
+ }
+
+ If ((Arg0 & 0x80))
+ {
+ Notify (S38, Arg1)
+ }
+
+ If ((Arg0 & 0x0100))
+ {
+ Notify (S40, Arg1)
+ }
+
+ If ((Arg0 & 0x0200))
+ {
+ Notify (S48, Arg1)
+ }
+
+ If ((Arg0 & 0x0400))
+ {
+ Notify (S50, Arg1)
+ }
+
+ If ((Arg0 & 0x0800))
+ {
+ Notify (S58, Arg1)
+ }
+
+ If ((Arg0 & 0x1000))
+ {
+ Notify (S60, Arg1)
+ }
+
+ If ((Arg0 & 0x2000))
+ {
+ Notify (S68, Arg1)
+ }
+
+ If ((Arg0 & 0x4000))
+ {
+ Notify (S70, Arg1)
+ }
+
+ If ((Arg0 & 0x8000))
+ {
+ Notify (S78, Arg1)
+ }
+
+ If ((Arg0 & 0x00010000))
+ {
+ Notify (S80, Arg1)
+ }
+
+ If ((Arg0 & 0x00020000))
+ {
+ Notify (S88, Arg1)
+ }
+
+ If ((Arg0 & 0x00040000))
+ {
+ Notify (S90, Arg1)
+ }
+
+ If ((Arg0 & 0x00080000))
+ {
+ Notify (S98, Arg1)
+ }
+
+ If ((Arg0 & 0x00100000))
+ {
+ Notify (SA0, Arg1)
+ }
+
+ If ((Arg0 & 0x00200000))
+ {
+ Notify (SA8, Arg1)
+ }
+
+ If ((Arg0 & 0x00400000))
+ {
+ Notify (SB0, Arg1)
+ }
+
+ If ((Arg0 & 0x00800000))
+ {
+ Notify (SB8, Arg1)
+ }
+
+ If ((Arg0 & 0x01000000))
+ {
+ Notify (SC0, Arg1)
+ }
+
+ If ((Arg0 & 0x02000000))
+ {
+ Notify (SC8, Arg1)
+ }
+
+ If ((Arg0 & 0x04000000))
+ {
+ Notify (SD0, Arg1)
+ }
+
+ If ((Arg0 & 0x08000000))
+ {
+ Notify (SD8, Arg1)
+ }
+
+ If ((Arg0 & 0x10000000))
+ {
+ Notify (SE0, Arg1)
+ }
+
+ If ((Arg0 & 0x20000000))
+ {
+ Notify (SE8, Arg1)
+ }
+
+ If ((Arg0 & 0x40000000))
+ {
+ Notify (SF0, Arg1)
+ }
+
+ If ((Arg0 & 0x80000000))
+ {
+ Notify (SF8, Arg1)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ BNUM = One
+ DVNT (PCIU, One)
+ DVNT (PCID, 0x03)
+ }
+ }
+
+ Device (S20)
+ {
+ Name (_SUN, 0x04) // _SUN: Slot User Number
+ Name (_ADR, 0x00040000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S28)
+ {
+ Name (_SUN, 0x05) // _SUN: Slot User Number
+ Name (_ADR, 0x00050000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S30)
+ {
+ Name (_SUN, 0x06) // _SUN: Slot User Number
+ Name (_ADR, 0x00060000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S38)
+ {
+ Name (_SUN, 0x07) // _SUN: Slot User Number
+ Name (_ADR, 0x00070000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S40)
+ {
+ Name (_SUN, 0x08) // _SUN: Slot User Number
+ Name (_ADR, 0x00080000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S48)
+ {
+ Name (_SUN, 0x09) // _SUN: Slot User Number
+ Name (_ADR, 0x00090000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S50)
+ {
+ Name (_SUN, 0x0A) // _SUN: Slot User Number
+ Name (_ADR, 0x000A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S58)
+ {
+ Name (_SUN, 0x0B) // _SUN: Slot User Number
+ Name (_ADR, 0x000B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S60)
+ {
+ Name (_SUN, 0x0C) // _SUN: Slot User Number
+ Name (_ADR, 0x000C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S68)
+ {
+ Name (_SUN, 0x0D) // _SUN: Slot User Number
+ Name (_ADR, 0x000D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S70)
+ {
+ Name (_SUN, 0x0E) // _SUN: Slot User Number
+ Name (_ADR, 0x000E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S78)
+ {
+ Name (_SUN, 0x0F) // _SUN: Slot User Number
+ Name (_ADR, 0x000F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S80)
+ {
+ Name (_SUN, 0x10) // _SUN: Slot User Number
+ Name (_ADR, 0x00100000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S88)
+ {
+ Name (_SUN, 0x11) // _SUN: Slot User Number
+ Name (_ADR, 0x00110000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S90)
+ {
+ Name (_SUN, 0x12) // _SUN: Slot User Number
+ Name (_ADR, 0x00120000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S98)
+ {
+ Name (_SUN, 0x13) // _SUN: Slot User Number
+ Name (_ADR, 0x00130000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA0)
+ {
+ Name (_SUN, 0x14) // _SUN: Slot User Number
+ Name (_ADR, 0x00140000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA8)
+ {
+ Name (_SUN, 0x15) // _SUN: Slot User Number
+ Name (_ADR, 0x00150000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB0)
+ {
+ Name (_SUN, 0x16) // _SUN: Slot User Number
+ Name (_ADR, 0x00160000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB8)
+ {
+ Name (_SUN, 0x17) // _SUN: Slot User Number
+ Name (_ADR, 0x00170000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC0)
+ {
+ Name (_SUN, 0x18) // _SUN: Slot User Number
+ Name (_ADR, 0x00180000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC8)
+ {
+ Name (_SUN, 0x19) // _SUN: Slot User Number
+ Name (_ADR, 0x00190000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD0)
+ {
+ Name (_SUN, 0x1A) // _SUN: Slot User Number
+ Name (_ADR, 0x001A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD8)
+ {
+ Name (_SUN, 0x1B) // _SUN: Slot User Number
+ Name (_ADR, 0x001B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE0)
+ {
+ Name (_SUN, 0x1C) // _SUN: Slot User Number
+ Name (_ADR, 0x001C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE8)
+ {
+ Name (_SUN, 0x1D) // _SUN: Slot User Number
+ Name (_ADR, 0x001D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF0)
+ {
+ Name (_SUN, 0x1E) // _SUN: Slot User Number
+ Name (_ADR, 0x001E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF8)
+ {
+ Name (_SUN, 0x1F) // _SUN: Slot User Number
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Method (DVNT, 2, NotSerialized)
+ {
+ If ((Arg0 & 0x10))
+ {
+ Notify (S20, Arg1)
+ }
+
+ If ((Arg0 & 0x20))
+ {
+ Notify (S28, Arg1)
+ }
+
+ If ((Arg0 & 0x40))
+ {
+ Notify (S30, Arg1)
+ }
+
+ If ((Arg0 & 0x80))
+ {
+ Notify (S38, Arg1)
+ }
+
+ If ((Arg0 & 0x0100))
+ {
+ Notify (S40, Arg1)
+ }
+
+ If ((Arg0 & 0x0200))
+ {
+ Notify (S48, Arg1)
+ }
+
+ If ((Arg0 & 0x0400))
+ {
+ Notify (S50, Arg1)
+ }
+
+ If ((Arg0 & 0x0800))
+ {
+ Notify (S58, Arg1)
+ }
+
+ If ((Arg0 & 0x1000))
+ {
+ Notify (S60, Arg1)
+ }
+
+ If ((Arg0 & 0x2000))
+ {
+ Notify (S68, Arg1)
+ }
+
+ If ((Arg0 & 0x4000))
+ {
+ Notify (S70, Arg1)
+ }
+
+ If ((Arg0 & 0x8000))
+ {
+ Notify (S78, Arg1)
+ }
+
+ If ((Arg0 & 0x00010000))
+ {
+ Notify (S80, Arg1)
+ }
+
+ If ((Arg0 & 0x00020000))
+ {
+ Notify (S88, Arg1)
+ }
+
+ If ((Arg0 & 0x00040000))
+ {
+ Notify (S90, Arg1)
+ }
+
+ If ((Arg0 & 0x00080000))
+ {
+ Notify (S98, Arg1)
+ }
+
+ If ((Arg0 & 0x00100000))
+ {
+ Notify (SA0, Arg1)
+ }
+
+ If ((Arg0 & 0x00200000))
+ {
+ Notify (SA8, Arg1)
+ }
+
+ If ((Arg0 & 0x00400000))
+ {
+ Notify (SB0, Arg1)
+ }
+
+ If ((Arg0 & 0x00800000))
+ {
+ Notify (SB8, Arg1)
+ }
+
+ If ((Arg0 & 0x01000000))
+ {
+ Notify (SC0, Arg1)
+ }
+
+ If ((Arg0 & 0x02000000))
+ {
+ Notify (SC8, Arg1)
+ }
+
+ If ((Arg0 & 0x04000000))
+ {
+ Notify (SD0, Arg1)
+ }
+
+ If ((Arg0 & 0x08000000))
+ {
+ Notify (SD8, Arg1)
+ }
+
+ If ((Arg0 & 0x10000000))
+ {
+ Notify (SE0, Arg1)
+ }
+
+ If ((Arg0 & 0x20000000))
+ {
+ Notify (SE8, Arg1)
+ }
+
+ If ((Arg0 & 0x40000000))
+ {
+ Notify (SF0, Arg1)
+ }
+
+ If ((Arg0 & 0x80000000))
+ {
+ Notify (SF8, Arg1)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ BNUM = Zero
+ DVNT (PCIU, One)
+ DVNT (PCID, 0x03)
+ ^S18.PCNT ()
+ }
+ }
+ }
+}
+
new file mode 100644
@@ -0,0 +1,1466 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/pc/DSDT.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00001515 (5397)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x39
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ OperationRegion (P40C, PCI_Config, 0x60, 0x04)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F2, // Range Minimum
+ 0x03F2, // Range Maximum
+ 0x00, // Alignment
+ 0x04, // Length
+ )
+ IO (Decode16,
+ 0x03F7, // Range Minimum
+ 0x03F7, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {6}
+ DMA (Compatibility, NotBusMaster, Transfer8, )
+ {2}
+ })
+ Device (FLPA)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information
+ {
+ Zero,
+ 0x05,
+ 0x4F,
+ 0x30,
+ One,
+ 0xAF,
+ 0x02,
+ 0x25,
+ 0x02,
+ 0x12,
+ 0x1B,
+ 0xFF,
+ 0x6C,
+ 0xF6,
+ 0x0F,
+ 0x08
+ })
+ }
+
+ Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate
+ {
+ /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0010 */ 0x02, 0x00, 0x00, 0x00 // ....
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ OperationRegion (PCST, SystemIO, 0xAE00, 0x08)
+ Field (PCST, DWordAcc, NoLock, WriteAsZeros)
+ {
+ PCIU, 32,
+ PCID, 32
+ }
+
+ OperationRegion (SEJ, SystemIO, 0xAE08, 0x04)
+ Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
+ {
+ B0EJ, 32
+ }
+
+ OperationRegion (BNMR, SystemIO, 0xAE10, 0x04)
+ Field (BNMR, DWordAcc, NoLock, WriteAsZeros)
+ {
+ BNUM, 32
+ }
+
+ Mutex (BLCK, 0x00)
+ Method (PCEJ, 2, NotSerialized)
+ {
+ Acquire (BLCK, 0xFFFF)
+ BNUM = Arg0
+ B0EJ = (One << Arg1)
+ Release (BLCK)
+ Return (Zero)
+ }
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Local0 = Package (0x80){}
+ Local1 = Zero
+ While ((Local1 < 0x80))
+ {
+ Local2 = (Local1 >> 0x02)
+ Local3 = ((Local1 + Local2) & 0x03)
+ If ((Local3 == Zero))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKD,
+ Zero
+ }
+ }
+
+ If ((Local3 == One))
+ {
+ If ((Local1 == 0x04))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKS,
+ Zero
+ }
+ }
+ Else
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKA,
+ Zero
+ }
+ }
+ }
+
+ If ((Local3 == 0x02))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKB,
+ Zero
+ }
+ }
+
+ If ((Local3 == 0x03))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKC,
+ Zero
+ }
+ }
+
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
+ Local4 [One] = (Local1 & 0x03)
+ Local0 [Local1] = Local4
+ Local1++
+ }
+
+ Return (Local0)
+ }
+ }
+
+ Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
+ {
+ PRQ0, 8,
+ PRQ1, 8,
+ PRQ2, 8,
+ PRQ3, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ If ((Arg0 < 0x80))
+ {
+ PRRI = Arg0
+ }
+
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ0))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ0 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ0))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ1))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ1 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ1))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ2))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ2 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ2))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ3))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ3 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ3))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKS)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000009,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0B)
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (_PRS) /* \_SB_.LNKS._PRS */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAF00, // Range Minimum
+ 0xAF00, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0xAF00, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (C001, Arg1)
+ }
+
+ If ((Arg0 == 0x02))
+ {
+ Notify (C002, Arg1)
+ }
+
+ If ((Arg0 == 0x03))
+ {
+ Notify (C003, Arg1)
+ }
+
+ If ((Arg0 == 0x04))
+ {
+ Notify (C004, Arg1)
+ }
+
+ If ((Arg0 == 0x05))
+ {
+ Notify (C005, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+
+ Processor (C002, 0x02, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x02))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x02)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x02, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+
+ Processor (C003, 0x03, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x03))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x03, 0x04, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x03)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x03, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, One) // _PXM: Device Proximity
+ }
+
+ Processor (C004, 0x04, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x04))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x04, 0x05, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x04)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x04, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, One) // _PXM: Device Proximity
+ }
+
+ Processor (C005, 0x05, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x05))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x05, 0x06, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x05)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x05, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, One) // _PXM: Device Proximity
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ Acquire (\_SB.PCI0.BLCK, 0xFFFF)
+ \_SB.PCI0.PCNT ()
+ Release (\_SB.PCI0.BLCK)
+ }
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xF6C00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000100000000, // Range Minimum
+ 0x000000017FFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000080000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAFE0, // Range Minimum
+ 0xAFE0, // Range Maximum
+ 0x01, // Alignment
+ 0x04, // Length
+ )
+ })
+ }
+
+ Device (PHPR)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "PCI Hotplug resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAE00, // Range Minimum
+ 0xAE00, // Range Maximum
+ 0x01, // Alignment
+ 0x14, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (BSEL, Zero)
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S10)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Device (S18)
+ {
+ Name (_SUN, 0x03) // _SUN: Slot User Number
+ Name (_ADR, 0x00030000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S20)
+ {
+ Name (_SUN, 0x04) // _SUN: Slot User Number
+ Name (_ADR, 0x00040000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S28)
+ {
+ Name (_SUN, 0x05) // _SUN: Slot User Number
+ Name (_ADR, 0x00050000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S30)
+ {
+ Name (_SUN, 0x06) // _SUN: Slot User Number
+ Name (_ADR, 0x00060000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S38)
+ {
+ Name (_SUN, 0x07) // _SUN: Slot User Number
+ Name (_ADR, 0x00070000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S40)
+ {
+ Name (_SUN, 0x08) // _SUN: Slot User Number
+ Name (_ADR, 0x00080000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S48)
+ {
+ Name (_SUN, 0x09) // _SUN: Slot User Number
+ Name (_ADR, 0x00090000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S50)
+ {
+ Name (_SUN, 0x0A) // _SUN: Slot User Number
+ Name (_ADR, 0x000A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S58)
+ {
+ Name (_SUN, 0x0B) // _SUN: Slot User Number
+ Name (_ADR, 0x000B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S60)
+ {
+ Name (_SUN, 0x0C) // _SUN: Slot User Number
+ Name (_ADR, 0x000C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S68)
+ {
+ Name (_SUN, 0x0D) // _SUN: Slot User Number
+ Name (_ADR, 0x000D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S70)
+ {
+ Name (_SUN, 0x0E) // _SUN: Slot User Number
+ Name (_ADR, 0x000E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S78)
+ {
+ Name (_SUN, 0x0F) // _SUN: Slot User Number
+ Name (_ADR, 0x000F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S80)
+ {
+ Name (_SUN, 0x10) // _SUN: Slot User Number
+ Name (_ADR, 0x00100000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S88)
+ {
+ Name (_SUN, 0x11) // _SUN: Slot User Number
+ Name (_ADR, 0x00110000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S90)
+ {
+ Name (_SUN, 0x12) // _SUN: Slot User Number
+ Name (_ADR, 0x00120000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S98)
+ {
+ Name (_SUN, 0x13) // _SUN: Slot User Number
+ Name (_ADR, 0x00130000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA0)
+ {
+ Name (_SUN, 0x14) // _SUN: Slot User Number
+ Name (_ADR, 0x00140000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA8)
+ {
+ Name (_SUN, 0x15) // _SUN: Slot User Number
+ Name (_ADR, 0x00150000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB0)
+ {
+ Name (_SUN, 0x16) // _SUN: Slot User Number
+ Name (_ADR, 0x00160000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB8)
+ {
+ Name (_SUN, 0x17) // _SUN: Slot User Number
+ Name (_ADR, 0x00170000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC0)
+ {
+ Name (_SUN, 0x18) // _SUN: Slot User Number
+ Name (_ADR, 0x00180000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC8)
+ {
+ Name (_SUN, 0x19) // _SUN: Slot User Number
+ Name (_ADR, 0x00190000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD0)
+ {
+ Name (_SUN, 0x1A) // _SUN: Slot User Number
+ Name (_ADR, 0x001A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD8)
+ {
+ Name (_SUN, 0x1B) // _SUN: Slot User Number
+ Name (_ADR, 0x001B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE0)
+ {
+ Name (_SUN, 0x1C) // _SUN: Slot User Number
+ Name (_ADR, 0x001C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE8)
+ {
+ Name (_SUN, 0x1D) // _SUN: Slot User Number
+ Name (_ADR, 0x001D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF0)
+ {
+ Name (_SUN, 0x1E) // _SUN: Slot User Number
+ Name (_ADR, 0x001E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF8)
+ {
+ Name (_SUN, 0x1F) // _SUN: Slot User Number
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Method (DVNT, 2, NotSerialized)
+ {
+ If ((Arg0 & 0x08))
+ {
+ Notify (S18, Arg1)
+ }
+
+ If ((Arg0 & 0x10))
+ {
+ Notify (S20, Arg1)
+ }
+
+ If ((Arg0 & 0x20))
+ {
+ Notify (S28, Arg1)
+ }
+
+ If ((Arg0 & 0x40))
+ {
+ Notify (S30, Arg1)
+ }
+
+ If ((Arg0 & 0x80))
+ {
+ Notify (S38, Arg1)
+ }
+
+ If ((Arg0 & 0x0100))
+ {
+ Notify (S40, Arg1)
+ }
+
+ If ((Arg0 & 0x0200))
+ {
+ Notify (S48, Arg1)
+ }
+
+ If ((Arg0 & 0x0400))
+ {
+ Notify (S50, Arg1)
+ }
+
+ If ((Arg0 & 0x0800))
+ {
+ Notify (S58, Arg1)
+ }
+
+ If ((Arg0 & 0x1000))
+ {
+ Notify (S60, Arg1)
+ }
+
+ If ((Arg0 & 0x2000))
+ {
+ Notify (S68, Arg1)
+ }
+
+ If ((Arg0 & 0x4000))
+ {
+ Notify (S70, Arg1)
+ }
+
+ If ((Arg0 & 0x8000))
+ {
+ Notify (S78, Arg1)
+ }
+
+ If ((Arg0 & 0x00010000))
+ {
+ Notify (S80, Arg1)
+ }
+
+ If ((Arg0 & 0x00020000))
+ {
+ Notify (S88, Arg1)
+ }
+
+ If ((Arg0 & 0x00040000))
+ {
+ Notify (S90, Arg1)
+ }
+
+ If ((Arg0 & 0x00080000))
+ {
+ Notify (S98, Arg1)
+ }
+
+ If ((Arg0 & 0x00100000))
+ {
+ Notify (SA0, Arg1)
+ }
+
+ If ((Arg0 & 0x00200000))
+ {
+ Notify (SA8, Arg1)
+ }
+
+ If ((Arg0 & 0x00400000))
+ {
+ Notify (SB0, Arg1)
+ }
+
+ If ((Arg0 & 0x00800000))
+ {
+ Notify (SB8, Arg1)
+ }
+
+ If ((Arg0 & 0x01000000))
+ {
+ Notify (SC0, Arg1)
+ }
+
+ If ((Arg0 & 0x02000000))
+ {
+ Notify (SC8, Arg1)
+ }
+
+ If ((Arg0 & 0x04000000))
+ {
+ Notify (SD0, Arg1)
+ }
+
+ If ((Arg0 & 0x08000000))
+ {
+ Notify (SD8, Arg1)
+ }
+
+ If ((Arg0 & 0x10000000))
+ {
+ Notify (SE0, Arg1)
+ }
+
+ If ((Arg0 & 0x20000000))
+ {
+ Notify (SE8, Arg1)
+ }
+
+ If ((Arg0 & 0x40000000))
+ {
+ Notify (SF0, Arg1)
+ }
+
+ If ((Arg0 & 0x80000000))
+ {
+ Notify (SF8, Arg1)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ BNUM = Zero
+ DVNT (PCIU, One)
+ DVNT (PCID, 0x03)
+ }
+ }
+ }
+}
+
new file mode 100644
@@ -0,0 +1,1719 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/pc/DSDT.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x000019BB (6587)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x21
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ External (_SB_.NVDR, UnknownObj)
+
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ OperationRegion (P40C, PCI_Config, 0x60, 0x04)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F2, // Range Minimum
+ 0x03F2, // Range Maximum
+ 0x00, // Alignment
+ 0x04, // Length
+ )
+ IO (Decode16,
+ 0x03F7, // Range Minimum
+ 0x03F7, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {6}
+ DMA (Compatibility, NotBusMaster, Transfer8, )
+ {2}
+ })
+ Device (FLPA)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information
+ {
+ Zero,
+ 0x05,
+ 0x4F,
+ 0x30,
+ One,
+ 0xAF,
+ 0x02,
+ 0x25,
+ 0x02,
+ 0x12,
+ 0x1B,
+ 0xFF,
+ 0x6C,
+ 0xF6,
+ 0x0F,
+ 0x08
+ })
+ }
+
+ Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate
+ {
+ /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0010 */ 0x02, 0x00, 0x00, 0x00 // ....
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ OperationRegion (PCST, SystemIO, 0xAE00, 0x08)
+ Field (PCST, DWordAcc, NoLock, WriteAsZeros)
+ {
+ PCIU, 32,
+ PCID, 32
+ }
+
+ OperationRegion (SEJ, SystemIO, 0xAE08, 0x04)
+ Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
+ {
+ B0EJ, 32
+ }
+
+ OperationRegion (BNMR, SystemIO, 0xAE10, 0x04)
+ Field (BNMR, DWordAcc, NoLock, WriteAsZeros)
+ {
+ BNUM, 32
+ }
+
+ Mutex (BLCK, 0x00)
+ Method (PCEJ, 2, NotSerialized)
+ {
+ Acquire (BLCK, 0xFFFF)
+ BNUM = Arg0
+ B0EJ = (One << Arg1)
+ Release (BLCK)
+ Return (Zero)
+ }
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Local0 = Package (0x80){}
+ Local1 = Zero
+ While ((Local1 < 0x80))
+ {
+ Local2 = (Local1 >> 0x02)
+ Local3 = ((Local1 + Local2) & 0x03)
+ If ((Local3 == Zero))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKD,
+ Zero
+ }
+ }
+
+ If ((Local3 == One))
+ {
+ If ((Local1 == 0x04))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKS,
+ Zero
+ }
+ }
+ Else
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKA,
+ Zero
+ }
+ }
+ }
+
+ If ((Local3 == 0x02))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKB,
+ Zero
+ }
+ }
+
+ If ((Local3 == 0x03))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKC,
+ Zero
+ }
+ }
+
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
+ Local4 [One] = (Local1 & 0x03)
+ Local0 [Local1] = Local4
+ Local1++
+ }
+
+ Return (Local0)
+ }
+ }
+
+ Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
+ {
+ PRQ0, 8,
+ PRQ1, 8,
+ PRQ2, 8,
+ PRQ3, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ If ((Arg0 < 0x80))
+ {
+ PRRI = Arg0
+ }
+
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ0))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ0 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ0))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ1))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ1 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ1))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ2))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ2 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ2))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ3))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ3 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ3))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKS)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000009,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0B)
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (_PRS) /* \_SB_.LNKS._PRS */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAF00, // Range Minimum
+ 0xAF00, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0xAF00, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (C001, Arg1)
+ }
+
+ If ((Arg0 == 0x02))
+ {
+ Notify (C002, Arg1)
+ }
+
+ If ((Arg0 == 0x03))
+ {
+ Notify (C003, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, One) // _PXM: Device Proximity
+ }
+
+ Processor (C002, 0x02, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x02))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x02)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x02, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, 0x02) // _PXM: Device Proximity
+ }
+
+ Processor (C003, 0x03, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x03))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x03)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x03, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, 0x03) // _PXM: Device Proximity
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Device (\_SB.PCI0.MHPD)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "Memory hotplug resources") // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0A00, // Range Minimum
+ 0x0A00, // Range Maximum
+ 0x00, // Alignment
+ 0x18, // Length
+ )
+ })
+ OperationRegion (HPMR, SystemIO, 0x0A00, 0x18)
+ }
+
+ Device (\_SB.MHPC)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "DIMM devices") // _UID: Unique ID
+ Name (MDNR, 0x03)
+ Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MRBL, 32,
+ MRBH, 32,
+ MRLL, 32,
+ MRLH, 32,
+ MPX, 32
+ }
+
+ Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x14),
+ MES, 1,
+ MINS, 1,
+ MRMV, 1,
+ MEJ, 1
+ }
+
+ Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MSEL, 32,
+ MOEV, 32,
+ MOSC, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0B)
+ }
+
+ Mutex (MLCK, 0x00)
+ Method (MSCN, 0, NotSerialized)
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ While ((Local0 < MDNR))
+ {
+ MSEL = Local0
+ If ((MINS == One))
+ {
+ MTFY (Local0, One)
+ MINS = One
+ }
+ ElseIf ((MRMV == One))
+ {
+ MTFY (Local0, 0x03)
+ MRMV = One
+ }
+
+ Local0 += One
+ }
+
+ Release (MLCK)
+ Return (One)
+ }
+
+ Method (MRST, 1, NotSerialized)
+ {
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ If ((MES == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MCRS, 1, Serialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Name (MR64, ResourceTemplate ()
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Range Minimum
+ 0xFFFFFFFFFFFFFFFE, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0xFFFFFFFFFFFFFFFF, // Length
+ ,, _Y01, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address
+ CreateDWordField (MR64, 0x12, MINH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length
+ CreateDWordField (MR64, 0x2A, LENH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address
+ CreateDWordField (MR64, 0x1A, MAXH)
+ MINH = MRBH /* \_SB_.MHPC.MRBH */
+ MINL = MRBL /* \_SB_.MHPC.MRBL */
+ LENH = MRLH /* \_SB_.MHPC.MRLH */
+ LENL = MRLL /* \_SB_.MHPC.MRLL */
+ MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */
+ MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */
+ If ((MAXL < MINL))
+ {
+ MAXH += One
+ }
+
+ If ((MAXL < One))
+ {
+ MAXH -= One
+ }
+
+ MAXL -= One
+ If ((MAXH == Zero))
+ {
+ Name (MR32, ResourceTemplate ()
+ {
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0xFFFFFFFE, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xFFFFFFFF, // Length
+ ,, _Y02, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length
+ MIN = MINL /* \_SB_.MHPC.MCRS.MINL */
+ MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */
+ LEN = LENL /* \_SB_.MHPC.MCRS.LENL */
+ Release (MLCK)
+ Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */
+ }
+
+ Release (MLCK)
+ Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */
+ }
+
+ Method (MPXM, 1, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Local0 = MPX /* \_SB_.MHPC.MPX_ */
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MOST, 4, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MOEV = Arg1
+ MOSC = Arg2
+ Release (MLCK)
+ }
+
+ Method (MEJ0, 2, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MEJ = One
+ Release (MLCK)
+ }
+
+ Device (MP00)
+ {
+ Name (_UID, "0x00") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Device (MP01)
+ {
+ Name (_UID, "0x01") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Device (MP02)
+ {
+ Name (_UID, "0x02") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Method (MTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (MP00, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (MP01, Arg1)
+ }
+
+ If ((Arg0 == 0x02))
+ {
+ Notify (MP02, Arg1)
+ }
+ }
+ }
+
+ Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.MHPC.MSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ Acquire (\_SB.PCI0.BLCK, 0xFFFF)
+ \_SB.PCI0.PCNT ()
+ Release (\_SB.PCI0.BLCK)
+ }
+
+ Method (_E04, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ Notify (\_SB.NVDR, 0x80) // Status Change
+ }
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xF6C00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000200000000, // Range Minimum
+ 0x000000027FFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000080000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAFE0, // Range Minimum
+ 0xAFE0, // Range Maximum
+ 0x01, // Alignment
+ 0x04, // Length
+ )
+ })
+ }
+
+ Device (PHPR)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "PCI Hotplug resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAE00, // Range Minimum
+ 0xAE00, // Range Maximum
+ 0x01, // Alignment
+ 0x14, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (BSEL, Zero)
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S10)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Device (S18)
+ {
+ Name (_SUN, 0x03) // _SUN: Slot User Number
+ Name (_ADR, 0x00030000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S20)
+ {
+ Name (_SUN, 0x04) // _SUN: Slot User Number
+ Name (_ADR, 0x00040000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S28)
+ {
+ Name (_SUN, 0x05) // _SUN: Slot User Number
+ Name (_ADR, 0x00050000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S30)
+ {
+ Name (_SUN, 0x06) // _SUN: Slot User Number
+ Name (_ADR, 0x00060000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S38)
+ {
+ Name (_SUN, 0x07) // _SUN: Slot User Number
+ Name (_ADR, 0x00070000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S40)
+ {
+ Name (_SUN, 0x08) // _SUN: Slot User Number
+ Name (_ADR, 0x00080000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S48)
+ {
+ Name (_SUN, 0x09) // _SUN: Slot User Number
+ Name (_ADR, 0x00090000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S50)
+ {
+ Name (_SUN, 0x0A) // _SUN: Slot User Number
+ Name (_ADR, 0x000A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S58)
+ {
+ Name (_SUN, 0x0B) // _SUN: Slot User Number
+ Name (_ADR, 0x000B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S60)
+ {
+ Name (_SUN, 0x0C) // _SUN: Slot User Number
+ Name (_ADR, 0x000C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S68)
+ {
+ Name (_SUN, 0x0D) // _SUN: Slot User Number
+ Name (_ADR, 0x000D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S70)
+ {
+ Name (_SUN, 0x0E) // _SUN: Slot User Number
+ Name (_ADR, 0x000E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S78)
+ {
+ Name (_SUN, 0x0F) // _SUN: Slot User Number
+ Name (_ADR, 0x000F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S80)
+ {
+ Name (_SUN, 0x10) // _SUN: Slot User Number
+ Name (_ADR, 0x00100000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S88)
+ {
+ Name (_SUN, 0x11) // _SUN: Slot User Number
+ Name (_ADR, 0x00110000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S90)
+ {
+ Name (_SUN, 0x12) // _SUN: Slot User Number
+ Name (_ADR, 0x00120000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S98)
+ {
+ Name (_SUN, 0x13) // _SUN: Slot User Number
+ Name (_ADR, 0x00130000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA0)
+ {
+ Name (_SUN, 0x14) // _SUN: Slot User Number
+ Name (_ADR, 0x00140000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA8)
+ {
+ Name (_SUN, 0x15) // _SUN: Slot User Number
+ Name (_ADR, 0x00150000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB0)
+ {
+ Name (_SUN, 0x16) // _SUN: Slot User Number
+ Name (_ADR, 0x00160000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB8)
+ {
+ Name (_SUN, 0x17) // _SUN: Slot User Number
+ Name (_ADR, 0x00170000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC0)
+ {
+ Name (_SUN, 0x18) // _SUN: Slot User Number
+ Name (_ADR, 0x00180000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC8)
+ {
+ Name (_SUN, 0x19) // _SUN: Slot User Number
+ Name (_ADR, 0x00190000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD0)
+ {
+ Name (_SUN, 0x1A) // _SUN: Slot User Number
+ Name (_ADR, 0x001A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD8)
+ {
+ Name (_SUN, 0x1B) // _SUN: Slot User Number
+ Name (_ADR, 0x001B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE0)
+ {
+ Name (_SUN, 0x1C) // _SUN: Slot User Number
+ Name (_ADR, 0x001C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE8)
+ {
+ Name (_SUN, 0x1D) // _SUN: Slot User Number
+ Name (_ADR, 0x001D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF0)
+ {
+ Name (_SUN, 0x1E) // _SUN: Slot User Number
+ Name (_ADR, 0x001E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF8)
+ {
+ Name (_SUN, 0x1F) // _SUN: Slot User Number
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Method (DVNT, 2, NotSerialized)
+ {
+ If ((Arg0 & 0x08))
+ {
+ Notify (S18, Arg1)
+ }
+
+ If ((Arg0 & 0x10))
+ {
+ Notify (S20, Arg1)
+ }
+
+ If ((Arg0 & 0x20))
+ {
+ Notify (S28, Arg1)
+ }
+
+ If ((Arg0 & 0x40))
+ {
+ Notify (S30, Arg1)
+ }
+
+ If ((Arg0 & 0x80))
+ {
+ Notify (S38, Arg1)
+ }
+
+ If ((Arg0 & 0x0100))
+ {
+ Notify (S40, Arg1)
+ }
+
+ If ((Arg0 & 0x0200))
+ {
+ Notify (S48, Arg1)
+ }
+
+ If ((Arg0 & 0x0400))
+ {
+ Notify (S50, Arg1)
+ }
+
+ If ((Arg0 & 0x0800))
+ {
+ Notify (S58, Arg1)
+ }
+
+ If ((Arg0 & 0x1000))
+ {
+ Notify (S60, Arg1)
+ }
+
+ If ((Arg0 & 0x2000))
+ {
+ Notify (S68, Arg1)
+ }
+
+ If ((Arg0 & 0x4000))
+ {
+ Notify (S70, Arg1)
+ }
+
+ If ((Arg0 & 0x8000))
+ {
+ Notify (S78, Arg1)
+ }
+
+ If ((Arg0 & 0x00010000))
+ {
+ Notify (S80, Arg1)
+ }
+
+ If ((Arg0 & 0x00020000))
+ {
+ Notify (S88, Arg1)
+ }
+
+ If ((Arg0 & 0x00040000))
+ {
+ Notify (S90, Arg1)
+ }
+
+ If ((Arg0 & 0x00080000))
+ {
+ Notify (S98, Arg1)
+ }
+
+ If ((Arg0 & 0x00100000))
+ {
+ Notify (SA0, Arg1)
+ }
+
+ If ((Arg0 & 0x00200000))
+ {
+ Notify (SA8, Arg1)
+ }
+
+ If ((Arg0 & 0x00400000))
+ {
+ Notify (SB0, Arg1)
+ }
+
+ If ((Arg0 & 0x00800000))
+ {
+ Notify (SB8, Arg1)
+ }
+
+ If ((Arg0 & 0x01000000))
+ {
+ Notify (SC0, Arg1)
+ }
+
+ If ((Arg0 & 0x02000000))
+ {
+ Notify (SC8, Arg1)
+ }
+
+ If ((Arg0 & 0x04000000))
+ {
+ Notify (SD0, Arg1)
+ }
+
+ If ((Arg0 & 0x08000000))
+ {
+ Notify (SD8, Arg1)
+ }
+
+ If ((Arg0 & 0x10000000))
+ {
+ Notify (SE0, Arg1)
+ }
+
+ If ((Arg0 & 0x20000000))
+ {
+ Notify (SE8, Arg1)
+ }
+
+ If ((Arg0 & 0x40000000))
+ {
+ Notify (SF0, Arg1)
+ }
+
+ If ((Arg0 & 0x80000000))
+ {
+ Notify (SF8, Arg1)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ BNUM = Zero
+ DVNT (PCIU, One)
+ DVNT (PCID, 0x03)
+ }
+ }
+ }
+}
+
new file mode 100644
@@ -0,0 +1,1407 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/pc/DSDT.roothp, Mon Sep 28 17:24:38 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00001488 (5256)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xF2
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ OperationRegion (P40C, PCI_Config, 0x60, 0x04)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F2, // Range Minimum
+ 0x03F2, // Range Maximum
+ 0x00, // Alignment
+ 0x04, // Length
+ )
+ IO (Decode16,
+ 0x03F7, // Range Minimum
+ 0x03F7, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {6}
+ DMA (Compatibility, NotBusMaster, Transfer8, )
+ {2}
+ })
+ Device (FLPA)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information
+ {
+ Zero,
+ 0x05,
+ 0x4F,
+ 0x30,
+ One,
+ 0xAF,
+ 0x02,
+ 0x25,
+ 0x02,
+ 0x12,
+ 0x1B,
+ 0xFF,
+ 0x6C,
+ 0xF6,
+ 0x0F,
+ 0x08
+ })
+ }
+
+ Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate
+ {
+ /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0010 */ 0x02, 0x00, 0x00, 0x00 // ....
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ OperationRegion (PCST, SystemIO, 0xAE00, 0x08)
+ Field (PCST, DWordAcc, NoLock, WriteAsZeros)
+ {
+ PCIU, 32,
+ PCID, 32
+ }
+
+ OperationRegion (SEJ, SystemIO, 0xAE08, 0x04)
+ Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
+ {
+ B0EJ, 32
+ }
+
+ OperationRegion (BNMR, SystemIO, 0xAE10, 0x04)
+ Field (BNMR, DWordAcc, NoLock, WriteAsZeros)
+ {
+ BNUM, 32
+ }
+
+ Mutex (BLCK, 0x00)
+ Method (PCEJ, 2, NotSerialized)
+ {
+ Acquire (BLCK, 0xFFFF)
+ BNUM = Arg0
+ B0EJ = (One << Arg1)
+ Release (BLCK)
+ Return (Zero)
+ }
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Local0 = Package (0x80){}
+ Local1 = Zero
+ While ((Local1 < 0x80))
+ {
+ Local2 = (Local1 >> 0x02)
+ Local3 = ((Local1 + Local2) & 0x03)
+ If ((Local3 == Zero))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKD,
+ Zero
+ }
+ }
+
+ If ((Local3 == One))
+ {
+ If ((Local1 == 0x04))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKS,
+ Zero
+ }
+ }
+ Else
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKA,
+ Zero
+ }
+ }
+ }
+
+ If ((Local3 == 0x02))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKB,
+ Zero
+ }
+ }
+
+ If ((Local3 == 0x03))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKC,
+ Zero
+ }
+ }
+
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
+ Local4 [One] = (Local1 & 0x03)
+ Local0 [Local1] = Local4
+ Local1++
+ }
+
+ Return (Local0)
+ }
+ }
+
+ Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
+ {
+ PRQ0, 8,
+ PRQ1, 8,
+ PRQ2, 8,
+ PRQ3, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ If ((Arg0 < 0x80))
+ {
+ PRRI = Arg0
+ }
+
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ0))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ0 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ0))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ1))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ1 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ1))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ2))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ2 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ2))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ3))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ3 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ3))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKS)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000009,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0B)
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (_PRS) /* \_SB_.LNKS._PRS */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAF00, // Range Minimum
+ 0xAF00, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0xAF00, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Name (CNEW, Package (0xFF){})
+ Local3 = Zero
+ Local4 = One
+ While ((Local4 == One))
+ {
+ Local4 = Zero
+ Local0 = One
+ Local1 = Zero
+ While (((Local0 == One) && (Local3 < One)))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CSEL = Local3
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CDAT < Local3))
+ {
+ Break
+ }
+
+ If ((Local1 == 0xFF))
+ {
+ Local4 = One
+ Break
+ }
+
+ Local3 = \_SB.PCI0.PRES.CDAT
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CNEW [Local1] = Local3
+ Local1++
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (Local3, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+
+ Local3++
+ }
+
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ Local3 = DerefOf (CNEW [Local2])
+ CTFY (Local3, One)
+ Debug = Local3
+ \_SB.PCI0.PRES.CSEL = Local3
+ \_SB.PCI0.PRES.CINS = One
+ Local2++
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ Acquire (\_SB.PCI0.BLCK, 0xFFFF)
+ \_SB.PCI0.PCNT ()
+ Release (\_SB.PCI0.BLCK)
+ }
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xF6C00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000100000000, // Range Minimum
+ 0x000000017FFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000080000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAFE0, // Range Minimum
+ 0xAFE0, // Range Maximum
+ 0x01, // Alignment
+ 0x04, // Length
+ )
+ })
+ }
+
+ Device (PHPR)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "PCI Hotplug resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAE00, // Range Minimum
+ 0xAE00, // Range Maximum
+ 0x01, // Alignment
+ 0x14, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S10)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Device (S18)
+ {
+ Name (_ADR, 0x00030000) // _ADR: Address
+ Name (BSEL, Zero)
+ Device (S00)
+ {
+ Name (_SUN, Zero) // _SUN: Slot User Number
+ Name (_ADR, Zero) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S08)
+ {
+ Name (_SUN, One) // _SUN: Slot User Number
+ Name (_ADR, 0x00010000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S10)
+ {
+ Name (_SUN, 0x02) // _SUN: Slot User Number
+ Name (_ADR, 0x00020000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S18)
+ {
+ Name (_SUN, 0x03) // _SUN: Slot User Number
+ Name (_ADR, 0x00030000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S20)
+ {
+ Name (_SUN, 0x04) // _SUN: Slot User Number
+ Name (_ADR, 0x00040000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S28)
+ {
+ Name (_SUN, 0x05) // _SUN: Slot User Number
+ Name (_ADR, 0x00050000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S30)
+ {
+ Name (_SUN, 0x06) // _SUN: Slot User Number
+ Name (_ADR, 0x00060000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S38)
+ {
+ Name (_SUN, 0x07) // _SUN: Slot User Number
+ Name (_ADR, 0x00070000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S40)
+ {
+ Name (_SUN, 0x08) // _SUN: Slot User Number
+ Name (_ADR, 0x00080000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S48)
+ {
+ Name (_SUN, 0x09) // _SUN: Slot User Number
+ Name (_ADR, 0x00090000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S50)
+ {
+ Name (_SUN, 0x0A) // _SUN: Slot User Number
+ Name (_ADR, 0x000A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S58)
+ {
+ Name (_SUN, 0x0B) // _SUN: Slot User Number
+ Name (_ADR, 0x000B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S60)
+ {
+ Name (_SUN, 0x0C) // _SUN: Slot User Number
+ Name (_ADR, 0x000C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S68)
+ {
+ Name (_SUN, 0x0D) // _SUN: Slot User Number
+ Name (_ADR, 0x000D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S70)
+ {
+ Name (_SUN, 0x0E) // _SUN: Slot User Number
+ Name (_ADR, 0x000E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S78)
+ {
+ Name (_SUN, 0x0F) // _SUN: Slot User Number
+ Name (_ADR, 0x000F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S80)
+ {
+ Name (_SUN, 0x10) // _SUN: Slot User Number
+ Name (_ADR, 0x00100000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S88)
+ {
+ Name (_SUN, 0x11) // _SUN: Slot User Number
+ Name (_ADR, 0x00110000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S90)
+ {
+ Name (_SUN, 0x12) // _SUN: Slot User Number
+ Name (_ADR, 0x00120000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S98)
+ {
+ Name (_SUN, 0x13) // _SUN: Slot User Number
+ Name (_ADR, 0x00130000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA0)
+ {
+ Name (_SUN, 0x14) // _SUN: Slot User Number
+ Name (_ADR, 0x00140000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA8)
+ {
+ Name (_SUN, 0x15) // _SUN: Slot User Number
+ Name (_ADR, 0x00150000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB0)
+ {
+ Name (_SUN, 0x16) // _SUN: Slot User Number
+ Name (_ADR, 0x00160000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB8)
+ {
+ Name (_SUN, 0x17) // _SUN: Slot User Number
+ Name (_ADR, 0x00170000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC0)
+ {
+ Name (_SUN, 0x18) // _SUN: Slot User Number
+ Name (_ADR, 0x00180000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC8)
+ {
+ Name (_SUN, 0x19) // _SUN: Slot User Number
+ Name (_ADR, 0x00190000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD0)
+ {
+ Name (_SUN, 0x1A) // _SUN: Slot User Number
+ Name (_ADR, 0x001A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD8)
+ {
+ Name (_SUN, 0x1B) // _SUN: Slot User Number
+ Name (_ADR, 0x001B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE0)
+ {
+ Name (_SUN, 0x1C) // _SUN: Slot User Number
+ Name (_ADR, 0x001C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE8)
+ {
+ Name (_SUN, 0x1D) // _SUN: Slot User Number
+ Name (_ADR, 0x001D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF0)
+ {
+ Name (_SUN, 0x1E) // _SUN: Slot User Number
+ Name (_ADR, 0x001E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF8)
+ {
+ Name (_SUN, 0x1F) // _SUN: Slot User Number
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Method (DVNT, 2, NotSerialized)
+ {
+ If ((Arg0 & One))
+ {
+ Notify (S00, Arg1)
+ }
+
+ If ((Arg0 & 0x02))
+ {
+ Notify (S08, Arg1)
+ }
+
+ If ((Arg0 & 0x04))
+ {
+ Notify (S10, Arg1)
+ }
+
+ If ((Arg0 & 0x08))
+ {
+ Notify (S18, Arg1)
+ }
+
+ If ((Arg0 & 0x10))
+ {
+ Notify (S20, Arg1)
+ }
+
+ If ((Arg0 & 0x20))
+ {
+ Notify (S28, Arg1)
+ }
+
+ If ((Arg0 & 0x40))
+ {
+ Notify (S30, Arg1)
+ }
+
+ If ((Arg0 & 0x80))
+ {
+ Notify (S38, Arg1)
+ }
+
+ If ((Arg0 & 0x0100))
+ {
+ Notify (S40, Arg1)
+ }
+
+ If ((Arg0 & 0x0200))
+ {
+ Notify (S48, Arg1)
+ }
+
+ If ((Arg0 & 0x0400))
+ {
+ Notify (S50, Arg1)
+ }
+
+ If ((Arg0 & 0x0800))
+ {
+ Notify (S58, Arg1)
+ }
+
+ If ((Arg0 & 0x1000))
+ {
+ Notify (S60, Arg1)
+ }
+
+ If ((Arg0 & 0x2000))
+ {
+ Notify (S68, Arg1)
+ }
+
+ If ((Arg0 & 0x4000))
+ {
+ Notify (S70, Arg1)
+ }
+
+ If ((Arg0 & 0x8000))
+ {
+ Notify (S78, Arg1)
+ }
+
+ If ((Arg0 & 0x00010000))
+ {
+ Notify (S80, Arg1)
+ }
+
+ If ((Arg0 & 0x00020000))
+ {
+ Notify (S88, Arg1)
+ }
+
+ If ((Arg0 & 0x00040000))
+ {
+ Notify (S90, Arg1)
+ }
+
+ If ((Arg0 & 0x00080000))
+ {
+ Notify (S98, Arg1)
+ }
+
+ If ((Arg0 & 0x00100000))
+ {
+ Notify (SA0, Arg1)
+ }
+
+ If ((Arg0 & 0x00200000))
+ {
+ Notify (SA8, Arg1)
+ }
+
+ If ((Arg0 & 0x00400000))
+ {
+ Notify (SB0, Arg1)
+ }
+
+ If ((Arg0 & 0x00800000))
+ {
+ Notify (SB8, Arg1)
+ }
+
+ If ((Arg0 & 0x01000000))
+ {
+ Notify (SC0, Arg1)
+ }
+
+ If ((Arg0 & 0x02000000))
+ {
+ Notify (SC8, Arg1)
+ }
+
+ If ((Arg0 & 0x04000000))
+ {
+ Notify (SD0, Arg1)
+ }
+
+ If ((Arg0 & 0x08000000))
+ {
+ Notify (SD8, Arg1)
+ }
+
+ If ((Arg0 & 0x10000000))
+ {
+ Notify (SE0, Arg1)
+ }
+
+ If ((Arg0 & 0x20000000))
+ {
+ Notify (SE8, Arg1)
+ }
+
+ If ((Arg0 & 0x40000000))
+ {
+ Notify (SF0, Arg1)
+ }
+
+ If ((Arg0 & 0x80000000))
+ {
+ Notify (SF8, Arg1)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ BNUM = Zero
+ DVNT (PCIU, One)
+ DVNT (PCID, 0x03)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ ^S18.PCNT ()
+ }
+ }
+ }
+}
+
GIT binary patch
delta 323
zcmbQQHdmd?CD<iot}p`wBkM-4Eo@9)c9RdVt!DByo}A16m&r|Rat?<~J%_WOYq${8
z{{n{O0>+d@E<%%27z-Fu3K$a#7!nux@JyJTz&JG-D3nl;9HY+?AM6w#;OuD-5ab%{
z9PH{-z<@63?CY{Xd@8!Ai(^Rg(gmE86S@8atyx+Cldp%F1yZm;Wim`0ChX}K%vg}z
z0diy_Lun$=Sqse<m|`dk@(p8j4snZ2=3*{jL^lH{3Dj4bT)>dD$dzSkQer_f*uW%)
eWM^)WCZG+`h6Tx!bvRU6ffkk~ZMNln#0dabbz!Rj
delta 193
zcmbQMK3|Q?CD<iIUYLP_@#jXaEo@9aW|I%Ft!DDqo}A16m&t=~at?<KUjbvnB1i7Y
z35*2{2?Y$34Y`E<7Pzxaj?rg{4|a+VaP~9^2yzW}_Vf#8bPjQgL>G5)3}Gx_L>C3B
l2AaFjn`MCq%VZl)NnLaWKy6&inEHZz!+`oW@8*2O2>_N2HcS8j
new file mode 100644
@@ -0,0 +1,1337 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/pc/DSDT.ipmikcs, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000138E (5006)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x54
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ OperationRegion (P40C, PCI_Config, 0x60, 0x04)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (MI1)
+ {
+ Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID
+ Name (_STR, "ipmi_kcs") // _STR: Description String
+ Name (_UID, One) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0CA2, // Range Minimum
+ 0x0CA3, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ })
+ Name (_IFT, One) // _IFT: IPMI Interface Type
+ Name (_SRV, 0x0200) // _SRV: IPMI Spec Revision
+ }
+
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F2, // Range Minimum
+ 0x03F2, // Range Maximum
+ 0x00, // Alignment
+ 0x04, // Length
+ )
+ IO (Decode16,
+ 0x03F7, // Range Minimum
+ 0x03F7, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {6}
+ DMA (Compatibility, NotBusMaster, Transfer8, )
+ {2}
+ })
+ Device (FLPA)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information
+ {
+ Zero,
+ 0x05,
+ 0x4F,
+ 0x30,
+ One,
+ 0xAF,
+ 0x02,
+ 0x25,
+ 0x02,
+ 0x12,
+ 0x1B,
+ 0xFF,
+ 0x6C,
+ 0xF6,
+ 0x0F,
+ 0x08
+ })
+ }
+
+ Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate
+ {
+ /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0010 */ 0x02, 0x00, 0x00, 0x00 // ....
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ OperationRegion (PCST, SystemIO, 0xAE00, 0x08)
+ Field (PCST, DWordAcc, NoLock, WriteAsZeros)
+ {
+ PCIU, 32,
+ PCID, 32
+ }
+
+ OperationRegion (SEJ, SystemIO, 0xAE08, 0x04)
+ Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
+ {
+ B0EJ, 32
+ }
+
+ OperationRegion (BNMR, SystemIO, 0xAE10, 0x04)
+ Field (BNMR, DWordAcc, NoLock, WriteAsZeros)
+ {
+ BNUM, 32
+ }
+
+ Mutex (BLCK, 0x00)
+ Method (PCEJ, 2, NotSerialized)
+ {
+ Acquire (BLCK, 0xFFFF)
+ BNUM = Arg0
+ B0EJ = (One << Arg1)
+ Release (BLCK)
+ Return (Zero)
+ }
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Local0 = Package (0x80){}
+ Local1 = Zero
+ While ((Local1 < 0x80))
+ {
+ Local2 = (Local1 >> 0x02)
+ Local3 = ((Local1 + Local2) & 0x03)
+ If ((Local3 == Zero))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKD,
+ Zero
+ }
+ }
+
+ If ((Local3 == One))
+ {
+ If ((Local1 == 0x04))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKS,
+ Zero
+ }
+ }
+ Else
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKA,
+ Zero
+ }
+ }
+ }
+
+ If ((Local3 == 0x02))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKB,
+ Zero
+ }
+ }
+
+ If ((Local3 == 0x03))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKC,
+ Zero
+ }
+ }
+
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
+ Local4 [One] = (Local1 & 0x03)
+ Local0 [Local1] = Local4
+ Local1++
+ }
+
+ Return (Local0)
+ }
+ }
+
+ Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
+ {
+ PRQ0, 8,
+ PRQ1, 8,
+ PRQ2, 8,
+ PRQ3, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ If ((Arg0 < 0x80))
+ {
+ PRRI = Arg0
+ }
+
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ0))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ0 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ0))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ1))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ1 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ1))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ2))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ2 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ2))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ3))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ3 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ3))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKS)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000009,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0B)
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (_PRS) /* \_SB_.LNKS._PRS */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAF00, // Range Minimum
+ 0xAF00, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0xAF00, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ Acquire (\_SB.PCI0.BLCK, 0xFFFF)
+ \_SB.PCI0.PCNT ()
+ Release (\_SB.PCI0.BLCK)
+ }
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xF6C00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000100000000, // Range Minimum
+ 0x000000017FFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000080000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAFE0, // Range Minimum
+ 0xAFE0, // Range Maximum
+ 0x01, // Alignment
+ 0x04, // Length
+ )
+ })
+ }
+
+ Device (PHPR)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "PCI Hotplug resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAE00, // Range Minimum
+ 0xAE00, // Range Maximum
+ 0x01, // Alignment
+ 0x14, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (BSEL, Zero)
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S10)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Device (S18)
+ {
+ Name (_SUN, 0x03) // _SUN: Slot User Number
+ Name (_ADR, 0x00030000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S20)
+ {
+ Name (_SUN, 0x04) // _SUN: Slot User Number
+ Name (_ADR, 0x00040000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S28)
+ {
+ Name (_SUN, 0x05) // _SUN: Slot User Number
+ Name (_ADR, 0x00050000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S30)
+ {
+ Name (_SUN, 0x06) // _SUN: Slot User Number
+ Name (_ADR, 0x00060000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S38)
+ {
+ Name (_SUN, 0x07) // _SUN: Slot User Number
+ Name (_ADR, 0x00070000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S40)
+ {
+ Name (_SUN, 0x08) // _SUN: Slot User Number
+ Name (_ADR, 0x00080000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S48)
+ {
+ Name (_SUN, 0x09) // _SUN: Slot User Number
+ Name (_ADR, 0x00090000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S50)
+ {
+ Name (_SUN, 0x0A) // _SUN: Slot User Number
+ Name (_ADR, 0x000A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S58)
+ {
+ Name (_SUN, 0x0B) // _SUN: Slot User Number
+ Name (_ADR, 0x000B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S60)
+ {
+ Name (_SUN, 0x0C) // _SUN: Slot User Number
+ Name (_ADR, 0x000C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S68)
+ {
+ Name (_SUN, 0x0D) // _SUN: Slot User Number
+ Name (_ADR, 0x000D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S70)
+ {
+ Name (_SUN, 0x0E) // _SUN: Slot User Number
+ Name (_ADR, 0x000E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S78)
+ {
+ Name (_SUN, 0x0F) // _SUN: Slot User Number
+ Name (_ADR, 0x000F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S80)
+ {
+ Name (_SUN, 0x10) // _SUN: Slot User Number
+ Name (_ADR, 0x00100000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S88)
+ {
+ Name (_SUN, 0x11) // _SUN: Slot User Number
+ Name (_ADR, 0x00110000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S90)
+ {
+ Name (_SUN, 0x12) // _SUN: Slot User Number
+ Name (_ADR, 0x00120000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S98)
+ {
+ Name (_SUN, 0x13) // _SUN: Slot User Number
+ Name (_ADR, 0x00130000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA0)
+ {
+ Name (_SUN, 0x14) // _SUN: Slot User Number
+ Name (_ADR, 0x00140000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA8)
+ {
+ Name (_SUN, 0x15) // _SUN: Slot User Number
+ Name (_ADR, 0x00150000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB0)
+ {
+ Name (_SUN, 0x16) // _SUN: Slot User Number
+ Name (_ADR, 0x00160000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB8)
+ {
+ Name (_SUN, 0x17) // _SUN: Slot User Number
+ Name (_ADR, 0x00170000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC0)
+ {
+ Name (_SUN, 0x18) // _SUN: Slot User Number
+ Name (_ADR, 0x00180000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC8)
+ {
+ Name (_SUN, 0x19) // _SUN: Slot User Number
+ Name (_ADR, 0x00190000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD0)
+ {
+ Name (_SUN, 0x1A) // _SUN: Slot User Number
+ Name (_ADR, 0x001A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD8)
+ {
+ Name (_SUN, 0x1B) // _SUN: Slot User Number
+ Name (_ADR, 0x001B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE0)
+ {
+ Name (_SUN, 0x1C) // _SUN: Slot User Number
+ Name (_ADR, 0x001C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE8)
+ {
+ Name (_SUN, 0x1D) // _SUN: Slot User Number
+ Name (_ADR, 0x001D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF0)
+ {
+ Name (_SUN, 0x1E) // _SUN: Slot User Number
+ Name (_ADR, 0x001E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF8)
+ {
+ Name (_SUN, 0x1F) // _SUN: Slot User Number
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Method (DVNT, 2, NotSerialized)
+ {
+ If ((Arg0 & 0x08))
+ {
+ Notify (S18, Arg1)
+ }
+
+ If ((Arg0 & 0x10))
+ {
+ Notify (S20, Arg1)
+ }
+
+ If ((Arg0 & 0x20))
+ {
+ Notify (S28, Arg1)
+ }
+
+ If ((Arg0 & 0x40))
+ {
+ Notify (S30, Arg1)
+ }
+
+ If ((Arg0 & 0x80))
+ {
+ Notify (S38, Arg1)
+ }
+
+ If ((Arg0 & 0x0100))
+ {
+ Notify (S40, Arg1)
+ }
+
+ If ((Arg0 & 0x0200))
+ {
+ Notify (S48, Arg1)
+ }
+
+ If ((Arg0 & 0x0400))
+ {
+ Notify (S50, Arg1)
+ }
+
+ If ((Arg0 & 0x0800))
+ {
+ Notify (S58, Arg1)
+ }
+
+ If ((Arg0 & 0x1000))
+ {
+ Notify (S60, Arg1)
+ }
+
+ If ((Arg0 & 0x2000))
+ {
+ Notify (S68, Arg1)
+ }
+
+ If ((Arg0 & 0x4000))
+ {
+ Notify (S70, Arg1)
+ }
+
+ If ((Arg0 & 0x8000))
+ {
+ Notify (S78, Arg1)
+ }
+
+ If ((Arg0 & 0x00010000))
+ {
+ Notify (S80, Arg1)
+ }
+
+ If ((Arg0 & 0x00020000))
+ {
+ Notify (S88, Arg1)
+ }
+
+ If ((Arg0 & 0x00040000))
+ {
+ Notify (S90, Arg1)
+ }
+
+ If ((Arg0 & 0x00080000))
+ {
+ Notify (S98, Arg1)
+ }
+
+ If ((Arg0 & 0x00100000))
+ {
+ Notify (SA0, Arg1)
+ }
+
+ If ((Arg0 & 0x00200000))
+ {
+ Notify (SA8, Arg1)
+ }
+
+ If ((Arg0 & 0x00400000))
+ {
+ Notify (SB0, Arg1)
+ }
+
+ If ((Arg0 & 0x00800000))
+ {
+ Notify (SB8, Arg1)
+ }
+
+ If ((Arg0 & 0x01000000))
+ {
+ Notify (SC0, Arg1)
+ }
+
+ If ((Arg0 & 0x02000000))
+ {
+ Notify (SC8, Arg1)
+ }
+
+ If ((Arg0 & 0x04000000))
+ {
+ Notify (SD0, Arg1)
+ }
+
+ If ((Arg0 & 0x08000000))
+ {
+ Notify (SD8, Arg1)
+ }
+
+ If ((Arg0 & 0x10000000))
+ {
+ Notify (SE0, Arg1)
+ }
+
+ If ((Arg0 & 0x20000000))
+ {
+ Notify (SE8, Arg1)
+ }
+
+ If ((Arg0 & 0x40000000))
+ {
+ Notify (SF0, Arg1)
+ }
+
+ If ((Arg0 & 0x80000000))
+ {
+ Notify (SF8, Arg1)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ BNUM = Zero
+ DVNT (PCIU, One)
+ DVNT (PCID, 0x03)
+ }
+ }
+ }
+}
+
new file mode 100644
@@ -0,0 +1,1625 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/pc/DSDT.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00001895 (6293)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xB2
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ OperationRegion (P40C, PCI_Config, 0x60, 0x04)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F2, // Range Minimum
+ 0x03F2, // Range Maximum
+ 0x00, // Alignment
+ 0x04, // Length
+ )
+ IO (Decode16,
+ 0x03F7, // Range Minimum
+ 0x03F7, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {6}
+ DMA (Compatibility, NotBusMaster, Transfer8, )
+ {2}
+ })
+ Device (FLPA)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information
+ {
+ Zero,
+ 0x05,
+ 0x4F,
+ 0x30,
+ One,
+ 0xAF,
+ 0x02,
+ 0x25,
+ 0x02,
+ 0x12,
+ 0x1B,
+ 0xFF,
+ 0x6C,
+ 0xF6,
+ 0x0F,
+ 0x08
+ })
+ }
+
+ Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate
+ {
+ /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0010 */ 0x02, 0x00, 0x00, 0x00 // ....
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ OperationRegion (PCST, SystemIO, 0xAE00, 0x08)
+ Field (PCST, DWordAcc, NoLock, WriteAsZeros)
+ {
+ PCIU, 32,
+ PCID, 32
+ }
+
+ OperationRegion (SEJ, SystemIO, 0xAE08, 0x04)
+ Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
+ {
+ B0EJ, 32
+ }
+
+ OperationRegion (BNMR, SystemIO, 0xAE10, 0x04)
+ Field (BNMR, DWordAcc, NoLock, WriteAsZeros)
+ {
+ BNUM, 32
+ }
+
+ Mutex (BLCK, 0x00)
+ Method (PCEJ, 2, NotSerialized)
+ {
+ Acquire (BLCK, 0xFFFF)
+ BNUM = Arg0
+ B0EJ = (One << Arg1)
+ Release (BLCK)
+ Return (Zero)
+ }
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Local0 = Package (0x80){}
+ Local1 = Zero
+ While ((Local1 < 0x80))
+ {
+ Local2 = (Local1 >> 0x02)
+ Local3 = ((Local1 + Local2) & 0x03)
+ If ((Local3 == Zero))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKD,
+ Zero
+ }
+ }
+
+ If ((Local3 == One))
+ {
+ If ((Local1 == 0x04))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKS,
+ Zero
+ }
+ }
+ Else
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKA,
+ Zero
+ }
+ }
+ }
+
+ If ((Local3 == 0x02))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKB,
+ Zero
+ }
+ }
+
+ If ((Local3 == 0x03))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKC,
+ Zero
+ }
+ }
+
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
+ Local4 [One] = (Local1 & 0x03)
+ Local0 [Local1] = Local4
+ Local1++
+ }
+
+ Return (Local0)
+ }
+ }
+
+ Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
+ {
+ PRQ0, 8,
+ PRQ1, 8,
+ PRQ2, 8,
+ PRQ3, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ If ((Arg0 < 0x80))
+ {
+ PRRI = Arg0
+ }
+
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ0))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ0 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ0))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ1))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ1 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ1))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ2))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ2 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ2))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ3))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ3 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ3))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKS)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000009,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0B)
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (_PRS) /* \_SB_.LNKS._PRS */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAF00, // Range Minimum
+ 0xAF00, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0xAF00, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Device (\_SB.PCI0.MHPD)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "Memory hotplug resources") // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0A00, // Range Minimum
+ 0x0A00, // Range Maximum
+ 0x00, // Alignment
+ 0x18, // Length
+ )
+ })
+ OperationRegion (HPMR, SystemIO, 0x0A00, 0x18)
+ }
+
+ Device (\_SB.MHPC)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "DIMM devices") // _UID: Unique ID
+ Name (MDNR, 0x03)
+ Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MRBL, 32,
+ MRBH, 32,
+ MRLL, 32,
+ MRLH, 32,
+ MPX, 32
+ }
+
+ Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x14),
+ MES, 1,
+ MINS, 1,
+ MRMV, 1,
+ MEJ, 1
+ }
+
+ Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MSEL, 32,
+ MOEV, 32,
+ MOSC, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0B)
+ }
+
+ Mutex (MLCK, 0x00)
+ Method (MSCN, 0, NotSerialized)
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ While ((Local0 < MDNR))
+ {
+ MSEL = Local0
+ If ((MINS == One))
+ {
+ MTFY (Local0, One)
+ MINS = One
+ }
+ ElseIf ((MRMV == One))
+ {
+ MTFY (Local0, 0x03)
+ MRMV = One
+ }
+
+ Local0 += One
+ }
+
+ Release (MLCK)
+ Return (One)
+ }
+
+ Method (MRST, 1, NotSerialized)
+ {
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ If ((MES == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MCRS, 1, Serialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Name (MR64, ResourceTemplate ()
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Range Minimum
+ 0xFFFFFFFFFFFFFFFE, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0xFFFFFFFFFFFFFFFF, // Length
+ ,, _Y01, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address
+ CreateDWordField (MR64, 0x12, MINH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length
+ CreateDWordField (MR64, 0x2A, LENH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address
+ CreateDWordField (MR64, 0x1A, MAXH)
+ MINH = MRBH /* \_SB_.MHPC.MRBH */
+ MINL = MRBL /* \_SB_.MHPC.MRBL */
+ LENH = MRLH /* \_SB_.MHPC.MRLH */
+ LENL = MRLL /* \_SB_.MHPC.MRLL */
+ MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */
+ MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */
+ If ((MAXL < MINL))
+ {
+ MAXH += One
+ }
+
+ If ((MAXL < One))
+ {
+ MAXH -= One
+ }
+
+ MAXL -= One
+ If ((MAXH == Zero))
+ {
+ Name (MR32, ResourceTemplate ()
+ {
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0xFFFFFFFE, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xFFFFFFFF, // Length
+ ,, _Y02, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length
+ MIN = MINL /* \_SB_.MHPC.MCRS.MINL */
+ MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */
+ LEN = LENL /* \_SB_.MHPC.MCRS.LENL */
+ Release (MLCK)
+ Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */
+ }
+
+ Release (MLCK)
+ Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */
+ }
+
+ Method (MPXM, 1, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Local0 = MPX /* \_SB_.MHPC.MPX_ */
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MOST, 4, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MOEV = Arg1
+ MOSC = Arg2
+ Release (MLCK)
+ }
+
+ Method (MEJ0, 2, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MEJ = One
+ Release (MLCK)
+ }
+
+ Device (MP00)
+ {
+ Name (_UID, "0x00") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Device (MP01)
+ {
+ Name (_UID, "0x01") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Device (MP02)
+ {
+ Name (_UID, "0x02") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Method (MTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (MP00, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (MP01, Arg1)
+ }
+
+ If ((Arg0 == 0x02))
+ {
+ Notify (MP02, Arg1)
+ }
+ }
+ }
+
+ Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.MHPC.MSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ Acquire (\_SB.PCI0.BLCK, 0xFFFF)
+ \_SB.PCI0.PCNT ()
+ Release (\_SB.PCI0.BLCK)
+ }
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xF6C00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000200000000, // Range Minimum
+ 0x000000027FFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000080000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAFE0, // Range Minimum
+ 0xAFE0, // Range Maximum
+ 0x01, // Alignment
+ 0x04, // Length
+ )
+ })
+ }
+
+ Device (PHPR)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "PCI Hotplug resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAE00, // Range Minimum
+ 0xAE00, // Range Maximum
+ 0x01, // Alignment
+ 0x14, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (BSEL, Zero)
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S10)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Device (S18)
+ {
+ Name (_SUN, 0x03) // _SUN: Slot User Number
+ Name (_ADR, 0x00030000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S20)
+ {
+ Name (_SUN, 0x04) // _SUN: Slot User Number
+ Name (_ADR, 0x00040000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S28)
+ {
+ Name (_SUN, 0x05) // _SUN: Slot User Number
+ Name (_ADR, 0x00050000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S30)
+ {
+ Name (_SUN, 0x06) // _SUN: Slot User Number
+ Name (_ADR, 0x00060000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S38)
+ {
+ Name (_SUN, 0x07) // _SUN: Slot User Number
+ Name (_ADR, 0x00070000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S40)
+ {
+ Name (_SUN, 0x08) // _SUN: Slot User Number
+ Name (_ADR, 0x00080000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S48)
+ {
+ Name (_SUN, 0x09) // _SUN: Slot User Number
+ Name (_ADR, 0x00090000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S50)
+ {
+ Name (_SUN, 0x0A) // _SUN: Slot User Number
+ Name (_ADR, 0x000A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S58)
+ {
+ Name (_SUN, 0x0B) // _SUN: Slot User Number
+ Name (_ADR, 0x000B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S60)
+ {
+ Name (_SUN, 0x0C) // _SUN: Slot User Number
+ Name (_ADR, 0x000C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S68)
+ {
+ Name (_SUN, 0x0D) // _SUN: Slot User Number
+ Name (_ADR, 0x000D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S70)
+ {
+ Name (_SUN, 0x0E) // _SUN: Slot User Number
+ Name (_ADR, 0x000E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S78)
+ {
+ Name (_SUN, 0x0F) // _SUN: Slot User Number
+ Name (_ADR, 0x000F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S80)
+ {
+ Name (_SUN, 0x10) // _SUN: Slot User Number
+ Name (_ADR, 0x00100000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S88)
+ {
+ Name (_SUN, 0x11) // _SUN: Slot User Number
+ Name (_ADR, 0x00110000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S90)
+ {
+ Name (_SUN, 0x12) // _SUN: Slot User Number
+ Name (_ADR, 0x00120000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S98)
+ {
+ Name (_SUN, 0x13) // _SUN: Slot User Number
+ Name (_ADR, 0x00130000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA0)
+ {
+ Name (_SUN, 0x14) // _SUN: Slot User Number
+ Name (_ADR, 0x00140000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA8)
+ {
+ Name (_SUN, 0x15) // _SUN: Slot User Number
+ Name (_ADR, 0x00150000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB0)
+ {
+ Name (_SUN, 0x16) // _SUN: Slot User Number
+ Name (_ADR, 0x00160000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB8)
+ {
+ Name (_SUN, 0x17) // _SUN: Slot User Number
+ Name (_ADR, 0x00170000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC0)
+ {
+ Name (_SUN, 0x18) // _SUN: Slot User Number
+ Name (_ADR, 0x00180000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC8)
+ {
+ Name (_SUN, 0x19) // _SUN: Slot User Number
+ Name (_ADR, 0x00190000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD0)
+ {
+ Name (_SUN, 0x1A) // _SUN: Slot User Number
+ Name (_ADR, 0x001A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD8)
+ {
+ Name (_SUN, 0x1B) // _SUN: Slot User Number
+ Name (_ADR, 0x001B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE0)
+ {
+ Name (_SUN, 0x1C) // _SUN: Slot User Number
+ Name (_ADR, 0x001C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE8)
+ {
+ Name (_SUN, 0x1D) // _SUN: Slot User Number
+ Name (_ADR, 0x001D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF0)
+ {
+ Name (_SUN, 0x1E) // _SUN: Slot User Number
+ Name (_ADR, 0x001E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF8)
+ {
+ Name (_SUN, 0x1F) // _SUN: Slot User Number
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Method (DVNT, 2, NotSerialized)
+ {
+ If ((Arg0 & 0x08))
+ {
+ Notify (S18, Arg1)
+ }
+
+ If ((Arg0 & 0x10))
+ {
+ Notify (S20, Arg1)
+ }
+
+ If ((Arg0 & 0x20))
+ {
+ Notify (S28, Arg1)
+ }
+
+ If ((Arg0 & 0x40))
+ {
+ Notify (S30, Arg1)
+ }
+
+ If ((Arg0 & 0x80))
+ {
+ Notify (S38, Arg1)
+ }
+
+ If ((Arg0 & 0x0100))
+ {
+ Notify (S40, Arg1)
+ }
+
+ If ((Arg0 & 0x0200))
+ {
+ Notify (S48, Arg1)
+ }
+
+ If ((Arg0 & 0x0400))
+ {
+ Notify (S50, Arg1)
+ }
+
+ If ((Arg0 & 0x0800))
+ {
+ Notify (S58, Arg1)
+ }
+
+ If ((Arg0 & 0x1000))
+ {
+ Notify (S60, Arg1)
+ }
+
+ If ((Arg0 & 0x2000))
+ {
+ Notify (S68, Arg1)
+ }
+
+ If ((Arg0 & 0x4000))
+ {
+ Notify (S70, Arg1)
+ }
+
+ If ((Arg0 & 0x8000))
+ {
+ Notify (S78, Arg1)
+ }
+
+ If ((Arg0 & 0x00010000))
+ {
+ Notify (S80, Arg1)
+ }
+
+ If ((Arg0 & 0x00020000))
+ {
+ Notify (S88, Arg1)
+ }
+
+ If ((Arg0 & 0x00040000))
+ {
+ Notify (S90, Arg1)
+ }
+
+ If ((Arg0 & 0x00080000))
+ {
+ Notify (S98, Arg1)
+ }
+
+ If ((Arg0 & 0x00100000))
+ {
+ Notify (SA0, Arg1)
+ }
+
+ If ((Arg0 & 0x00200000))
+ {
+ Notify (SA8, Arg1)
+ }
+
+ If ((Arg0 & 0x00400000))
+ {
+ Notify (SB0, Arg1)
+ }
+
+ If ((Arg0 & 0x00800000))
+ {
+ Notify (SB8, Arg1)
+ }
+
+ If ((Arg0 & 0x01000000))
+ {
+ Notify (SC0, Arg1)
+ }
+
+ If ((Arg0 & 0x02000000))
+ {
+ Notify (SC8, Arg1)
+ }
+
+ If ((Arg0 & 0x04000000))
+ {
+ Notify (SD0, Arg1)
+ }
+
+ If ((Arg0 & 0x08000000))
+ {
+ Notify (SD8, Arg1)
+ }
+
+ If ((Arg0 & 0x10000000))
+ {
+ Notify (SE0, Arg1)
+ }
+
+ If ((Arg0 & 0x20000000))
+ {
+ Notify (SE8, Arg1)
+ }
+
+ If ((Arg0 & 0x40000000))
+ {
+ Notify (SF0, Arg1)
+ }
+
+ If ((Arg0 & 0x80000000))
+ {
+ Notify (SF8, Arg1)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ BNUM = Zero
+ DVNT (PCIU, One)
+ DVNT (PCID, 0x03)
+ }
+ }
+ }
+}
+
new file mode 100644
@@ -0,0 +1,1321 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/pc/DSDT.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000134C (4940)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x6A
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ OperationRegion (P40C, PCI_Config, 0x60, 0x04)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F2, // Range Minimum
+ 0x03F2, // Range Maximum
+ 0x00, // Alignment
+ 0x04, // Length
+ )
+ IO (Decode16,
+ 0x03F7, // Range Minimum
+ 0x03F7, // Range Maximum
+ 0x00, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {6}
+ DMA (Compatibility, NotBusMaster, Transfer8, )
+ {2}
+ })
+ Device (FLPA)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information
+ {
+ Zero,
+ 0x05,
+ 0x4F,
+ 0x30,
+ One,
+ 0xAF,
+ 0x02,
+ 0x25,
+ 0x02,
+ 0x12,
+ 0x1B,
+ 0xFF,
+ 0x6C,
+ 0xF6,
+ 0x0F,
+ 0x08
+ })
+ }
+
+ Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate
+ {
+ /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........
+ /* 0010 */ 0x02, 0x00, 0x00, 0x00 // ....
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ OperationRegion (PCST, SystemIO, 0xAE00, 0x08)
+ Field (PCST, DWordAcc, NoLock, WriteAsZeros)
+ {
+ PCIU, 32,
+ PCID, 32
+ }
+
+ OperationRegion (SEJ, SystemIO, 0xAE08, 0x04)
+ Field (SEJ, DWordAcc, NoLock, WriteAsZeros)
+ {
+ B0EJ, 32
+ }
+
+ OperationRegion (BNMR, SystemIO, 0xAE10, 0x04)
+ Field (BNMR, DWordAcc, NoLock, WriteAsZeros)
+ {
+ BNUM, 32
+ }
+
+ Mutex (BLCK, 0x00)
+ Method (PCEJ, 2, NotSerialized)
+ {
+ Acquire (BLCK, 0xFFFF)
+ BNUM = Arg0
+ B0EJ = (One << Arg1)
+ Release (BLCK)
+ Return (Zero)
+ }
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Local0 = Package (0x80){}
+ Local1 = Zero
+ While ((Local1 < 0x80))
+ {
+ Local2 = (Local1 >> 0x02)
+ Local3 = ((Local1 + Local2) & 0x03)
+ If ((Local3 == Zero))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKD,
+ Zero
+ }
+ }
+
+ If ((Local3 == One))
+ {
+ If ((Local1 == 0x04))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKS,
+ Zero
+ }
+ }
+ Else
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKA,
+ Zero
+ }
+ }
+ }
+
+ If ((Local3 == 0x02))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKB,
+ Zero
+ }
+ }
+
+ If ((Local3 == 0x03))
+ {
+ Local4 = Package (0x04)
+ {
+ Zero,
+ Zero,
+ LNKC,
+ Zero
+ }
+ }
+
+ Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF)
+ Local4 [One] = (Local1 & 0x03)
+ Local0 [Local1] = Local4
+ Local1++
+ }
+
+ Return (Local0)
+ }
+ }
+
+ Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
+ {
+ PRQ0, 8,
+ PRQ1, 8,
+ PRQ2, 8,
+ PRQ3, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ If ((Arg0 < 0x80))
+ {
+ PRRI = Arg0
+ }
+
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ0))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ0 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ0))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ1))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ1 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ1))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ2))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ2 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ2))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQ3))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQ3 |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQ3))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKS)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000009,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0B)
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (_PRS) /* \_SB_.LNKS._PRS */
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAF00, // Range Minimum
+ 0xAF00, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0xAF00, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ Acquire (\_SB.PCI0.BLCK, 0xFFFF)
+ \_SB.PCI0.PCNT ()
+ Release (\_SB.PCI0.BLCK)
+ }
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xF6C00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000100000000, // Range Minimum
+ 0x000000017FFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000080000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAFE0, // Range Minimum
+ 0xAFE0, // Range Maximum
+ 0x01, // Alignment
+ 0x04, // Length
+ )
+ })
+ }
+
+ Device (PHPR)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "PCI Hotplug resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0xAE00, // Range Minimum
+ 0xAE00, // Range Maximum
+ 0x01, // Alignment
+ 0x14, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (BSEL, Zero)
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S10)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Device (S18)
+ {
+ Name (_SUN, 0x03) // _SUN: Slot User Number
+ Name (_ADR, 0x00030000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S20)
+ {
+ Name (_SUN, 0x04) // _SUN: Slot User Number
+ Name (_ADR, 0x00040000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S28)
+ {
+ Name (_SUN, 0x05) // _SUN: Slot User Number
+ Name (_ADR, 0x00050000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S30)
+ {
+ Name (_SUN, 0x06) // _SUN: Slot User Number
+ Name (_ADR, 0x00060000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S38)
+ {
+ Name (_SUN, 0x07) // _SUN: Slot User Number
+ Name (_ADR, 0x00070000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S40)
+ {
+ Name (_SUN, 0x08) // _SUN: Slot User Number
+ Name (_ADR, 0x00080000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S48)
+ {
+ Name (_SUN, 0x09) // _SUN: Slot User Number
+ Name (_ADR, 0x00090000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S50)
+ {
+ Name (_SUN, 0x0A) // _SUN: Slot User Number
+ Name (_ADR, 0x000A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S58)
+ {
+ Name (_SUN, 0x0B) // _SUN: Slot User Number
+ Name (_ADR, 0x000B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S60)
+ {
+ Name (_SUN, 0x0C) // _SUN: Slot User Number
+ Name (_ADR, 0x000C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S68)
+ {
+ Name (_SUN, 0x0D) // _SUN: Slot User Number
+ Name (_ADR, 0x000D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S70)
+ {
+ Name (_SUN, 0x0E) // _SUN: Slot User Number
+ Name (_ADR, 0x000E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S78)
+ {
+ Name (_SUN, 0x0F) // _SUN: Slot User Number
+ Name (_ADR, 0x000F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S80)
+ {
+ Name (_SUN, 0x10) // _SUN: Slot User Number
+ Name (_ADR, 0x00100000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S88)
+ {
+ Name (_SUN, 0x11) // _SUN: Slot User Number
+ Name (_ADR, 0x00110000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S90)
+ {
+ Name (_SUN, 0x12) // _SUN: Slot User Number
+ Name (_ADR, 0x00120000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (S98)
+ {
+ Name (_SUN, 0x13) // _SUN: Slot User Number
+ Name (_ADR, 0x00130000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA0)
+ {
+ Name (_SUN, 0x14) // _SUN: Slot User Number
+ Name (_ADR, 0x00140000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SA8)
+ {
+ Name (_SUN, 0x15) // _SUN: Slot User Number
+ Name (_ADR, 0x00150000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB0)
+ {
+ Name (_SUN, 0x16) // _SUN: Slot User Number
+ Name (_ADR, 0x00160000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SB8)
+ {
+ Name (_SUN, 0x17) // _SUN: Slot User Number
+ Name (_ADR, 0x00170000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC0)
+ {
+ Name (_SUN, 0x18) // _SUN: Slot User Number
+ Name (_ADR, 0x00180000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SC8)
+ {
+ Name (_SUN, 0x19) // _SUN: Slot User Number
+ Name (_ADR, 0x00190000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD0)
+ {
+ Name (_SUN, 0x1A) // _SUN: Slot User Number
+ Name (_ADR, 0x001A0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SD8)
+ {
+ Name (_SUN, 0x1B) // _SUN: Slot User Number
+ Name (_ADR, 0x001B0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE0)
+ {
+ Name (_SUN, 0x1C) // _SUN: Slot User Number
+ Name (_ADR, 0x001C0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SE8)
+ {
+ Name (_SUN, 0x1D) // _SUN: Slot User Number
+ Name (_ADR, 0x001D0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF0)
+ {
+ Name (_SUN, 0x1E) // _SUN: Slot User Number
+ Name (_ADR, 0x001E0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Device (SF8)
+ {
+ Name (_SUN, 0x1F) // _SUN: Slot User Number
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ PCEJ (BSEL, _SUN)
+ }
+ }
+
+ Method (DVNT, 2, NotSerialized)
+ {
+ If ((Arg0 & 0x08))
+ {
+ Notify (S18, Arg1)
+ }
+
+ If ((Arg0 & 0x10))
+ {
+ Notify (S20, Arg1)
+ }
+
+ If ((Arg0 & 0x20))
+ {
+ Notify (S28, Arg1)
+ }
+
+ If ((Arg0 & 0x40))
+ {
+ Notify (S30, Arg1)
+ }
+
+ If ((Arg0 & 0x80))
+ {
+ Notify (S38, Arg1)
+ }
+
+ If ((Arg0 & 0x0100))
+ {
+ Notify (S40, Arg1)
+ }
+
+ If ((Arg0 & 0x0200))
+ {
+ Notify (S48, Arg1)
+ }
+
+ If ((Arg0 & 0x0400))
+ {
+ Notify (S50, Arg1)
+ }
+
+ If ((Arg0 & 0x0800))
+ {
+ Notify (S58, Arg1)
+ }
+
+ If ((Arg0 & 0x1000))
+ {
+ Notify (S60, Arg1)
+ }
+
+ If ((Arg0 & 0x2000))
+ {
+ Notify (S68, Arg1)
+ }
+
+ If ((Arg0 & 0x4000))
+ {
+ Notify (S70, Arg1)
+ }
+
+ If ((Arg0 & 0x8000))
+ {
+ Notify (S78, Arg1)
+ }
+
+ If ((Arg0 & 0x00010000))
+ {
+ Notify (S80, Arg1)
+ }
+
+ If ((Arg0 & 0x00020000))
+ {
+ Notify (S88, Arg1)
+ }
+
+ If ((Arg0 & 0x00040000))
+ {
+ Notify (S90, Arg1)
+ }
+
+ If ((Arg0 & 0x00080000))
+ {
+ Notify (S98, Arg1)
+ }
+
+ If ((Arg0 & 0x00100000))
+ {
+ Notify (SA0, Arg1)
+ }
+
+ If ((Arg0 & 0x00200000))
+ {
+ Notify (SA8, Arg1)
+ }
+
+ If ((Arg0 & 0x00400000))
+ {
+ Notify (SB0, Arg1)
+ }
+
+ If ((Arg0 & 0x00800000))
+ {
+ Notify (SB8, Arg1)
+ }
+
+ If ((Arg0 & 0x01000000))
+ {
+ Notify (SC0, Arg1)
+ }
+
+ If ((Arg0 & 0x02000000))
+ {
+ Notify (SC8, Arg1)
+ }
+
+ If ((Arg0 & 0x04000000))
+ {
+ Notify (SD0, Arg1)
+ }
+
+ If ((Arg0 & 0x08000000))
+ {
+ Notify (SD8, Arg1)
+ }
+
+ If ((Arg0 & 0x10000000))
+ {
+ Notify (SE0, Arg1)
+ }
+
+ If ((Arg0 & 0x20000000))
+ {
+ Notify (SE8, Arg1)
+ }
+
+ If ((Arg0 & 0x40000000))
+ {
+ Notify (SF0, Arg1)
+ }
+
+ If ((Arg0 & 0x80000000))
+ {
+ Notify (SF8, Arg1)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ BNUM = Zero
+ DVNT (PCIU, One)
+ DVNT (PCID, 0x03)
+ }
+ }
+ }
+}
+
GIT binary patch
delta 323
zcmeCu=+NYH33dtT5Mf|o{Irp43mcP{-Q)votC@U_C+D*NWpWdnoWmhg&*ALn8ZN~2
zzkngRfH7r}i_qj0#sY?v0>*>_hQviaJQF4-FiuSd3MCXI$LO=f2Rp?FIC~ld1i1z~
z2fO+dFrW)M`?@R;pNcN(;uw;=bOGn&M6UlpYnB$k<m+K(ffOuInG6$$348hlGZrLw
zfE<~~P?`vI)<W|IrWneCe8U)>L);>hxtI$W(aiu#0`-+97ce9(a%GvClvvOVHZX}H
e*_j)p31~yKVL|d_9S&7ipoOJLn{7GIasdD>6JkmL
delta 193
zcmeCs?9$+J33dtL5@BFqe72Em3mcP<+2jLktC{?@C+D*NW%A&goWmi*SHPIC$dP+;
z0%HL~LIJ~MLoQ*z1@0`9WAs_#gPr07oIMQ!f?R{0J^g|iokQFr(ZyXHLl_Gf(M5r(
lf#xpsW?A6DGTDYxQWsqTP#YIBroJHGFrdE8yE)Ht0RUaLHR}KX
new file mode 100644
GIT binary patch
literal 116
zcmZ>BbPgzCU|?We=;ZJ05v<@85#a0w6k`O6f!H7#1{fJQ88!hqA3p#IHi#$-lm_uQ
ffb0kBq2f#oEG$6gfBygc5D^9jBOqgG0|Ns9?p_Z8
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,99 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACP.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 00000074
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : A1
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : F1
+[035h 0053 1] ACPI Disable Value : F0
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 0000AFE0
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 04
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000080A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+Raw Table Data: Length 116 (0x74)
+
+ 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 80 00 00 // ....
new file mode 100644
GIT binary patch
literal 116
zcmZ>BbPgzCU|?We=;ZJ05v<@85#a0w6k`O6f!H7#1{fJQ88!hqA3p#IHi#$-lm_uQ
ffb0kBq2f#oEG$6gfBygc5D^9jBOqgG0|Ns9?p_Z8
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,99 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACP.bridge, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 00000074
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : A1
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : F1
+[035h 0053 1] ACPI Disable Value : F0
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 0000AFE0
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 04
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000080A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+Raw Table Data: Length 116 (0x74)
+
+ 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 80 00 00 // ....
new file mode 100644
GIT binary patch
literal 116
zcmZ>BbPgzCU|?We=;ZJ05v<@85#a0w6k`O6f!H7#1{fJQ88!hqA3p#IHi#$-lm_uQ
ffb0kBq2f#oEG$6gfBygc5D^9jBOqgG0|Ns9?p_Z8
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,99 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACP.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 00000074
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : A1
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : F1
+[035h 0053 1] ACPI Disable Value : F0
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 0000AFE0
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 04
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000080A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+Raw Table Data: Length 116 (0x74)
+
+ 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 80 00 00 // ....
new file mode 100644
GIT binary patch
literal 116
zcmZ>BbPgzCU|?We=;ZJ05v<@85#a0w6k`O6f!H7#1{fJQ88!hqA3p#IHi#$-lm_uQ
ffb0kBq2f#oEG$6gfBygc5D^9jBOqgG0|Ns9?p_Z8
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,99 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACP.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 00000074
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : A1
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : F1
+[035h 0053 1] ACPI Disable Value : F0
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 0000AFE0
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 04
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000080A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+Raw Table Data: Length 116 (0x74)
+
+ 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 80 00 00 // ....
new file mode 100644
@@ -0,0 +1,99 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACP.roothp, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 00000074
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : A1
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : F1
+[035h 0053 1] ACPI Disable Value : F0
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 0000AFE0
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 04
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000080A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+Raw Table Data: Length 116 (0x74)
+
+ 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 80 00 00 // ....
new file mode 100644
GIT binary patch
literal 116
zcmZ>BbPgzCU|?We=;ZJ05v<@85#a0w6k`O6f!H7#1{fJQ88!hqA3p#IHi#$-lm_uQ
ffb0kBq2f#oEG$6gfBygc5D^9jBOqgG0|Ns9?p_Z8
literal 0
HcmV?d00001
new file mode 100644
GIT binary patch
literal 116
zcmZ>BbPgzCU|?We=;ZJ05v<@85#a0w6k`O6f!H7#1{fJQ88!hqA3p#IHi#$-lm_uQ
ffb0kBq2f#oEG$6gfBygc5D^9jBOqgG0|Ns9?p_Z8
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,99 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACP.ipmikcs, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 00000074
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : A1
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : F1
+[035h 0053 1] ACPI Disable Value : F0
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 0000AFE0
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 04
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000080A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+Raw Table Data: Length 116 (0x74)
+
+ 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 80 00 00 // ....
new file mode 100644
GIT binary patch
literal 116
zcmZ>BbPgzCU|?We=;ZJ05v<@85#a0w6k`O6f!H7#1{fJQ88!hqA3p#IHi#$-lm_uQ
ffb0kBq2f#oEG$6gfBygc5D^9jBOqgG0|Ns9?p_Z8
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,99 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACP.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 00000074
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : A1
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : F1
+[035h 0053 1] ACPI Disable Value : F0
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 0000AFE0
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 04
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000080A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+Raw Table Data: Length 116 (0x74)
+
+ 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 80 00 00 // ....
new file mode 100644
GIT binary patch
literal 116
zcmZ>BbPgzCU|?We=;ZJ05v<@85#a0w6k`O6f!H7#1{fJQ88!hqA3p#IHi#$-lm_uQ
ffb0kBq2f#oEG$6gfBygc5D^9jBOqgG0|Ns9?p_Z8
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,99 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACP.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 00000074
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : A1
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : F1
+[035h 0053 1] ACPI Disable Value : F0
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 0000AFE0
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 04
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000080A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+Raw Table Data: Length 116 (0x74)
+
+ 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 80 00 00 // ....
new file mode 100644
GIT binary patch
literal 116
zcmZ>BbPgzCU|?We=;ZJ05v<@85#a0w6k`O6f!H7#1{fJQ88!hqA3p#IHi#$-lm_uQ
ffb0kBq2f#oEG$6gfBygc5D^9jBOqgG0|Ns9?p_Z8
literal 0
HcmV?d00001
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACS.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACS.bridge, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACS.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACS.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACS.roothp, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACS.ipmikcs, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACS.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/FACS.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,132 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/HMAT.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HMAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table]
+[004h 0004 4] Table Length : 00000118
+[008h 0008 1] Revision : 02
+[009h 0009 1] Checksum : 98
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHMAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Reserved : 00000000
+
+[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
+[02Ah 0042 2] Reserved : 0000
+[02Ch 0044 4] Length : 00000028
+[030h 0048 2] Flags (decoded below) : 0001
+ Processor Proximity Domain Valid : 1
+[032h 0050 2] Reserved1 : 0000
+[034h 0052 4] Processor Proximity Domain : 00000000
+[038h 0056 4] Memory Proximity Domain : 00000000
+[03Ch 0060 4] Reserved2 : 00000000
+[040h 0064 8] Reserved3 : 0000000000000000
+[048h 0072 8] Reserved4 : 0000000000000000
+
+[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
+[052h 0082 2] Reserved : 0000
+[054h 0084 4] Length : 00000028
+[058h 0088 2] Flags (decoded below) : 0001
+ Processor Proximity Domain Valid : 1
+[05Ah 0090 2] Reserved1 : 0000
+[05Ch 0092 4] Processor Proximity Domain : 00000000
+[060h 0096 4] Memory Proximity Domain : 00000001
+[064h 0100 4] Reserved2 : 00000000
+[068h 0104 8] Reserved3 : 0000000000000000
+[070h 0112 8] Reserved4 : 0000000000000000
+
+[078h 0120 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
+[07Ah 0122 2] Reserved : 0000
+[07Ch 0124 4] Length : 00000030
+[080h 0128 1] Flags (decoded below) : 00
+ Memory Hierarchy : 0
+[081h 0129 1] Data Type : 00
+[082h 0130 2] Reserved1 : 0000
+[084h 0132 4] Initiator Proximity Domains # : 00000001
+[088h 0136 4] Target Proximity Domains # : 00000002
+[08Ch 0140 4] Reserved2 : 00000000
+[090h 0144 8] Entry Base Unit : 00000000000003E8
+[098h 0152 4] Initiator Proximity Domain List : 00000000
+[09Ch 0156 4] Target Proximity Domain List : 00000000
+[0A0h 0160 4] Target Proximity Domain List : 00000001
+[0A4h 0164 2] Entry : 0001
+[0A6h 0166 2] Entry : FFFE
+
+[0A8h 0168 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
+[0AAh 0170 2] Reserved : 0000
+[0ACh 0172 4] Length : 00000030
+[0B0h 0176 1] Flags (decoded below) : 00
+ Memory Hierarchy : 0
+[0B1h 0177 1] Data Type : 03
+[0B2h 0178 2] Reserved1 : 0000
+[0B4h 0180 4] Initiator Proximity Domains # : 00000001
+[0B8h 0184 4] Target Proximity Domains # : 00000002
+[0BCh 0188 4] Reserved2 : 00000000
+[0C0h 0192 8] Entry Base Unit : 0000000000000001
+[0C8h 0200 4] Initiator Proximity Domain List : 00000000
+[0CCh 0204 4] Target Proximity Domain List : 00000000
+[0D0h 0208 4] Target Proximity Domain List : 00000001
+[0D4h 0212 2] Entry : FFFE
+[0D6h 0214 2] Entry : 7FFF
+
+[0D8h 0216 2] Structure Type : 0002 [Memory Side Cache Information]
+[0DAh 0218 2] Reserved : 0000
+[0DCh 0220 4] Length : 00000020
+[0E0h 0224 4] Memory Proximity Domain : 00000000
+[0E4h 0228 4] Reserved1 : 00000000
+[0E8h 0232 8] Memory Side Cache Size : 0000000000002800
+[0F0h 0240 4] Cache Attributes (decoded below) : 00081111
+ Total Cache Levels : 1
+ Cache Level : 1
+ Cache Associativity : 1
+ Write Policy : 1
+ Cache Line Size : 0008
+[0F4h 0244 2] Reserved2 : 0000
+[0F6h 0246 2] SMBIOS Handle # : 0000
+
+[0F8h 0248 2] Structure Type : 0002 [Memory Side Cache Information]
+[0FAh 0250 2] Reserved : 0000
+[0FCh 0252 4] Length : 00000020
+[100h 0256 4] Memory Proximity Domain : 00000001
+[104h 0260 4] Reserved1 : 00000000
+[108h 0264 8] Memory Side Cache Size : 0000000000002800
+[110h 0272 4] Cache Attributes (decoded below) : 00081111
+ Total Cache Levels : 1
+ Cache Level : 1
+ Cache Associativity : 1
+ Write Policy : 1
+ Cache Line Size : 0008
+[114h 0276 2] Reserved2 : 0000
+[116h 0278 2] SMBIOS Handle # : 0000
+
+Raw Table Data: Length 280 (0x118)
+
+ 0000: 48 4D 41 54 18 01 00 00 02 98 42 4F 43 48 53 20 // HMAT......BOCHS
+ 0010: 42 58 50 43 48 4D 41 54 01 00 00 00 42 58 50 43 // BXPCHMAT....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
+ 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 28 00 00 00 01 00 00 00 00 00 00 00 // ....(...........
+ 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0070: 00 00 00 00 00 00 00 00 01 00 00 00 30 00 00 00 // ............0...
+ 0080: 00 00 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................
+ 0090: E8 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00A0: 01 00 00 00 01 00 FE FF 01 00 00 00 30 00 00 00 // ............0...
+ 00B0: 00 03 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................
+ 00C0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 01 00 00 00 FE FF FF 7F 02 00 00 00 20 00 00 00 // ............ ...
+ 00E0: 00 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(......
+ 00F0: 11 11 08 00 00 00 00 00 02 00 00 00 20 00 00 00 // ............ ...
+ 0100: 01 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(......
+ 0110: 11 11 08 00 00 00 00 00 // ........
new file mode 100644
@@ -0,0 +1,132 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/HMAT.acpihmat, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [HMAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table]
+[004h 0004 4] Table Length : 00000118
+[008h 0008 1] Revision : 02
+[009h 0009 1] Checksum : 98
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHMAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Reserved : 00000000
+
+[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
+[02Ah 0042 2] Reserved : 0000
+[02Ch 0044 4] Length : 00000028
+[030h 0048 2] Flags (decoded below) : 0001
+ Processor Proximity Domain Valid : 1
+[032h 0050 2] Reserved1 : 0000
+[034h 0052 4] Processor Proximity Domain : 00000000
+[038h 0056 4] Memory Proximity Domain : 00000000
+[03Ch 0060 4] Reserved2 : 00000000
+[040h 0064 8] Reserved3 : 0000000000000000
+[048h 0072 8] Reserved4 : 0000000000000000
+
+[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
+[052h 0082 2] Reserved : 0000
+[054h 0084 4] Length : 00000028
+[058h 0088 2] Flags (decoded below) : 0001
+ Processor Proximity Domain Valid : 1
+[05Ah 0090 2] Reserved1 : 0000
+[05Ch 0092 4] Processor Proximity Domain : 00000000
+[060h 0096 4] Memory Proximity Domain : 00000001
+[064h 0100 4] Reserved2 : 00000000
+[068h 0104 8] Reserved3 : 0000000000000000
+[070h 0112 8] Reserved4 : 0000000000000000
+
+[078h 0120 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
+[07Ah 0122 2] Reserved : 0000
+[07Ch 0124 4] Length : 00000030
+[080h 0128 1] Flags (decoded below) : 00
+ Memory Hierarchy : 0
+[081h 0129 1] Data Type : 00
+[082h 0130 2] Reserved1 : 0000
+[084h 0132 4] Initiator Proximity Domains # : 00000001
+[088h 0136 4] Target Proximity Domains # : 00000002
+[08Ch 0140 4] Reserved2 : 00000000
+[090h 0144 8] Entry Base Unit : 00000000000003E8
+[098h 0152 4] Initiator Proximity Domain List : 00000000
+[09Ch 0156 4] Target Proximity Domain List : 00000000
+[0A0h 0160 4] Target Proximity Domain List : 00000001
+[0A4h 0164 2] Entry : 0001
+[0A6h 0166 2] Entry : FFFE
+
+[0A8h 0168 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
+[0AAh 0170 2] Reserved : 0000
+[0ACh 0172 4] Length : 00000030
+[0B0h 0176 1] Flags (decoded below) : 00
+ Memory Hierarchy : 0
+[0B1h 0177 1] Data Type : 03
+[0B2h 0178 2] Reserved1 : 0000
+[0B4h 0180 4] Initiator Proximity Domains # : 00000001
+[0B8h 0184 4] Target Proximity Domains # : 00000002
+[0BCh 0188 4] Reserved2 : 00000000
+[0C0h 0192 8] Entry Base Unit : 0000000000000001
+[0C8h 0200 4] Initiator Proximity Domain List : 00000000
+[0CCh 0204 4] Target Proximity Domain List : 00000000
+[0D0h 0208 4] Target Proximity Domain List : 00000001
+[0D4h 0212 2] Entry : FFFE
+[0D6h 0214 2] Entry : 7FFF
+
+[0D8h 0216 2] Structure Type : 0002 [Memory Side Cache Information]
+[0DAh 0218 2] Reserved : 0000
+[0DCh 0220 4] Length : 00000020
+[0E0h 0224 4] Memory Proximity Domain : 00000000
+[0E4h 0228 4] Reserved1 : 00000000
+[0E8h 0232 8] Memory Side Cache Size : 0000000000002800
+[0F0h 0240 4] Cache Attributes (decoded below) : 00081111
+ Total Cache Levels : 1
+ Cache Level : 1
+ Cache Associativity : 1
+ Write Policy : 1
+ Cache Line Size : 0008
+[0F4h 0244 2] Reserved2 : 0000
+[0F6h 0246 2] SMBIOS Handle # : 0000
+
+[0F8h 0248 2] Structure Type : 0002 [Memory Side Cache Information]
+[0FAh 0250 2] Reserved : 0000
+[0FCh 0252 4] Length : 00000020
+[100h 0256 4] Memory Proximity Domain : 00000001
+[104h 0260 4] Reserved1 : 00000000
+[108h 0264 8] Memory Side Cache Size : 0000000000002800
+[110h 0272 4] Cache Attributes (decoded below) : 00081111
+ Total Cache Levels : 1
+ Cache Level : 1
+ Cache Associativity : 1
+ Write Policy : 1
+ Cache Line Size : 0008
+[114h 0276 2] Reserved2 : 0000
+[116h 0278 2] SMBIOS Handle # : 0000
+
+Raw Table Data: Length 280 (0x118)
+
+ 0000: 48 4D 41 54 18 01 00 00 02 98 42 4F 43 48 53 20 // HMAT......BOCHS
+ 0010: 42 58 50 43 48 4D 41 54 01 00 00 00 42 58 50 43 // BXPCHMAT....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
+ 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 28 00 00 00 01 00 00 00 00 00 00 00 // ....(...........
+ 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0070: 00 00 00 00 00 00 00 00 01 00 00 00 30 00 00 00 // ............0...
+ 0080: 00 00 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................
+ 0090: E8 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00A0: 01 00 00 00 01 00 FE FF 01 00 00 00 30 00 00 00 // ............0...
+ 00B0: 00 03 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................
+ 00C0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 01 00 00 00 FE FF FF 7F 02 00 00 00 20 00 00 00 // ............ ...
+ 00E0: 00 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(......
+ 00F0: 11 11 08 00 00 00 00 00 02 00 00 00 20 00 00 00 // ............ ...
+ 0100: 01 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(......
+ 0110: 11 11 08 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/HPET.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/HPET.bridge, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/HPET.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/HPET.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/HPET.roothp, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/HPET.ipmikcs, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/HPET.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/HPET.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,115 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/NFIT.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [NFIT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table]
+[004h 0004 4] Table Length : 000000F0
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 24
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCNFIT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Reserved : 00000000
+
+[028h 0040 2] Subtable Type : 0000 [System Physical Address Range]
+[02Ah 0042 2] Length : 0038
+
+[02Ch 0044 2] Range Index : 0004
+[02Eh 0046 2] Flags (decoded below) : 0003
+ Add/Online Operation Only : 1
+ Proximity Domain Valid : 1
+[030h 0048 4] Reserved : 00000000
+[034h 0052 4] Proximity Domain : 00000002
+[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB
+[048h 0072 8] Address Range Base : 0000000108000000
+[050h 0080 8] Address Range Length : 0000000008000000
+[058h 0088 8] Memory Map Attribute : 0000000000008008
+
+[060h 0096 2] Subtable Type : 0001 [Memory Range Map]
+[062h 0098 2] Length : 0030
+
+[064h 0100 4] Device Handle : 00000002
+[068h 0104 2] Physical Id : 0000
+[06Ah 0106 2] Region Id : 0000
+[06Ch 0108 2] Range Index : 0004
+[06Eh 0110 2] Control Region Index : 0005
+[070h 0112 8] Region Size : 0000000008000000
+[078h 0120 8] Region Offset : 0000000000000000
+[080h 0128 8] Address Region Base : 0000000000000000
+[088h 0136 2] Interleave Index : 0000
+[08Ah 0138 2] Interleave Ways : 0001
+[08Ch 0140 2] Flags : 0000
+ Save to device failed : 0
+ Restore from device failed : 0
+ Platform flush failed : 0
+ Device not armed : 0
+ Health events observed : 0
+ Health events enabled : 0
+ Mapping failed : 0
+[08Eh 0142 2] Reserved : 0000
+
+[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region]
+[092h 0146 2] Length : 0050
+
+[094h 0148 2] Region Index : 0005
+[096h 0150 2] Vendor Id : 8086
+[098h 0152 2] Device Id : 0001
+[09Ah 0154 2] Revision Id : 0001
+[09Ch 0156 2] Subsystem Vendor Id : 0000
+[09Eh 0158 2] Subsystem Device Id : 0000
+[0A0h 0160 2] Subsystem Revision Id : 0000
+[0A2h 0162 1] Valid Fields : 00
+[0A3h 0163 1] Manufacturing Location : 00
+[0A4h 0164 2] Manufacturing Date : 0000
+[0A6h 0166 2] Reserved : 0000
+[0A8h 0168 4] Serial Number : 00123457
+[0ACh 0172 2] Code : 0301
+[0AEh 0174 2] Window Count : 0000
+[0B0h 0176 8] Window Size : 0000000000000000
+[0B8h 0184 8] Command Offset : 0000000000000000
+[0C0h 0192 8] Command Size : 0000000000000000
+[0C8h 0200 8] Status Offset : 0000000000000000
+[0D0h 0208 8] Status Size : 0000000000000000
+[0D8h 0216 2] Flags : 0000
+ Windows buffered : 0
+[0DAh 0218 6] Reserved1 : 000000000000
+
+[0E0h 0224 2] Subtable Type : 0007 [Platform Capabilities]
+[0E2h 0226 2] Length : 0010
+
+[0E4h 0228 1] Highest Capability : 01
+[0E5h 0229 3] Reserved : 000000
+[0E8h 0232 4] Capabilities (decoded below) : 00000003
+ Cache Flush to NVDIMM : 1
+ Memory Flush to NVDIMM : 1
+ Memory Mirroring : 0
+[0ECh 0236 4] Reserved : 00000000
+
+Raw Table Data: Length 240 (0xF0)
+
+ 0000: 4E 46 49 54 F0 00 00 00 01 24 42 4F 43 48 53 20 // NFIT.....$BOCHS
+ 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8.....
+ 0030: 00 00 00 00 02 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@
+ 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 08 01 00 00 00 // .C.3............
+ 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................
+ 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0.............
+ 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................
+ 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P.............
+ 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4......
+ 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 07 00 10 00 01 00 00 00 03 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,115 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/NFIT.dimmpxm, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [NFIT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table]
+[004h 0004 4] Table Length : 000000F0
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 24
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCNFIT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Reserved : 00000000
+
+[028h 0040 2] Subtable Type : 0000 [System Physical Address Range]
+[02Ah 0042 2] Length : 0038
+
+[02Ch 0044 2] Range Index : 0004
+[02Eh 0046 2] Flags (decoded below) : 0003
+ Add/Online Operation Only : 1
+ Proximity Domain Valid : 1
+[030h 0048 4] Reserved : 00000000
+[034h 0052 4] Proximity Domain : 00000002
+[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB
+[048h 0072 8] Address Range Base : 0000000108000000
+[050h 0080 8] Address Range Length : 0000000008000000
+[058h 0088 8] Memory Map Attribute : 0000000000008008
+
+[060h 0096 2] Subtable Type : 0001 [Memory Range Map]
+[062h 0098 2] Length : 0030
+
+[064h 0100 4] Device Handle : 00000002
+[068h 0104 2] Physical Id : 0000
+[06Ah 0106 2] Region Id : 0000
+[06Ch 0108 2] Range Index : 0004
+[06Eh 0110 2] Control Region Index : 0005
+[070h 0112 8] Region Size : 0000000008000000
+[078h 0120 8] Region Offset : 0000000000000000
+[080h 0128 8] Address Region Base : 0000000000000000
+[088h 0136 2] Interleave Index : 0000
+[08Ah 0138 2] Interleave Ways : 0001
+[08Ch 0140 2] Flags : 0000
+ Save to device failed : 0
+ Restore from device failed : 0
+ Platform flush failed : 0
+ Device not armed : 0
+ Health events observed : 0
+ Health events enabled : 0
+ Mapping failed : 0
+[08Eh 0142 2] Reserved : 0000
+
+[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region]
+[092h 0146 2] Length : 0050
+
+[094h 0148 2] Region Index : 0005
+[096h 0150 2] Vendor Id : 8086
+[098h 0152 2] Device Id : 0001
+[09Ah 0154 2] Revision Id : 0001
+[09Ch 0156 2] Subsystem Vendor Id : 0000
+[09Eh 0158 2] Subsystem Device Id : 0000
+[0A0h 0160 2] Subsystem Revision Id : 0000
+[0A2h 0162 1] Valid Fields : 00
+[0A3h 0163 1] Manufacturing Location : 00
+[0A4h 0164 2] Manufacturing Date : 0000
+[0A6h 0166 2] Reserved : 0000
+[0A8h 0168 4] Serial Number : 00123457
+[0ACh 0172 2] Code : 0301
+[0AEh 0174 2] Window Count : 0000
+[0B0h 0176 8] Window Size : 0000000000000000
+[0B8h 0184 8] Command Offset : 0000000000000000
+[0C0h 0192 8] Command Size : 0000000000000000
+[0C8h 0200 8] Status Offset : 0000000000000000
+[0D0h 0208 8] Status Size : 0000000000000000
+[0D8h 0216 2] Flags : 0000
+ Windows buffered : 0
+[0DAh 0218 6] Reserved1 : 000000000000
+
+[0E0h 0224 2] Subtable Type : 0007 [Platform Capabilities]
+[0E2h 0226 2] Length : 0010
+
+[0E4h 0228 1] Highest Capability : 01
+[0E5h 0229 3] Reserved : 000000
+[0E8h 0232 4] Capabilities (decoded below) : 00000003
+ Cache Flush to NVDIMM : 1
+ Memory Flush to NVDIMM : 1
+ Memory Mirroring : 0
+[0ECh 0236 4] Reserved : 00000000
+
+Raw Table Data: Length 240 (0xF0)
+
+ 0000: 4E 46 49 54 F0 00 00 00 01 24 42 4F 43 48 53 20 // NFIT.....$BOCHS
+ 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8.....
+ 0030: 00 00 00 00 02 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@
+ 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 08 01 00 00 00 // .C.3............
+ 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................
+ 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0.............
+ 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................
+ 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P.............
+ 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4......
+ 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 07 00 10 00 01 00 00 00 03 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/SLIT.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SLIT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SLIT" [System Locality Information Table]
+[004h 0004 4] Table Length : 00000030
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 2C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSLIT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Localities : 0000000000000002
+[02Ch 0044 2] Locality 0 : 0A 15
+[02Eh 0046 2] Locality 1 : 15 0A
+
+Raw Table Data: Length 48 (0x30)
+
+ 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS
+ 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC
+ 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/SLIT.memhp, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [SLIT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SLIT" [System Locality Information Table]
+[004h 0004 4] Table Length : 00000030
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 2C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSLIT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Localities : 0000000000000002
+[02Ch 0044 2] Locality 0 : 0A 15
+[02Eh 0046 2] Locality 1 : 15 0A
+
+Raw Table Data: Length 48 (0x30)
+
+ 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS
+ 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC
+ 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/SLIT.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SLIT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SLIT" [System Locality Information Table]
+[004h 0004 4] Table Length : 00000030
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 2C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSLIT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Localities : 0000000000000002
+[02Ch 0044 2] Locality 0 : 0A 15
+[02Eh 0046 2] Locality 1 : 15 0A
+
+Raw Table Data: Length 48 (0x30)
+
+ 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS
+ 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC
+ 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................
new file mode 100644
@@ -0,0 +1,137 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/SRAT.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 00000118
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : C0
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[031h 0049 1] Length : 10
+
+[032h 0050 1] Proximity Domain Low(8) : 00
+[033h 0051 1] Apic ID : 00
+[034h 0052 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[038h 0056 1] Local Sapic EID : 00
+[039h 0057 3] Proximity Domain High(24) : 000000
+[03Ch 0060 4] Clock Domain : 00000000
+
+[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[041h 0065 1] Length : 10
+
+[042h 0066 1] Proximity Domain Low(8) : 00
+[043h 0067 1] Apic ID : 01
+[044h 0068 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[048h 0072 1] Local Sapic EID : 00
+[049h 0073 3] Proximity Domain High(24) : 000000
+[04Ch 0076 4] Clock Domain : 00000000
+
+[050h 0080 1] Subtable Type : 01 [Memory Affinity]
+[051h 0081 1] Length : 28
+
+[052h 0082 4] Proximity Domain : 00000000
+[056h 0086 2] Reserved1 : 0000
+[058h 0088 8] Base Address : 0000000000000000
+[060h 0096 8] Address Length : 00000000000A0000
+[068h 0104 4] Reserved2 : 00000000
+[06Ch 0108 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[070h 0112 8] Reserved3 : 0000000000000000
+
+[078h 0120 1] Subtable Type : 01 [Memory Affinity]
+[079h 0121 1] Length : 28
+
+[07Ah 0122 4] Proximity Domain : 00000000
+[07Eh 0126 2] Reserved1 : 0000
+[080h 0128 8] Base Address : 0000000000100000
+[088h 0136 8] Address Length : 0000000003F00000
+[090h 0144 4] Reserved2 : 00000000
+[094h 0148 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[098h 0152 8] Reserved3 : 0000000000000000
+
+[0A0h 0160 1] Subtable Type : 01 [Memory Affinity]
+[0A1h 0161 1] Length : 28
+
+[0A2h 0162 4] Proximity Domain : 00000001
+[0A6h 0166 2] Reserved1 : 0000
+[0A8h 0168 8] Base Address : 0000000004000000
+[0B0h 0176 8] Address Length : 0000000004000000
+[0B8h 0184 4] Reserved2 : 00000000
+[0BCh 0188 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0C0h 0192 8] Reserved3 : 0000000000000000
+
+[0C8h 0200 1] Subtable Type : 01 [Memory Affinity]
+[0C9h 0201 1] Length : 28
+
+[0CAh 0202 4] Proximity Domain : 00000000
+[0CEh 0206 2] Reserved1 : 0000
+[0D0h 0208 8] Base Address : 0000000000000000
+[0D8h 0216 8] Address Length : 0000000000000000
+[0E0h 0224 4] Reserved2 : 00000000
+[0E4h 0228 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0E8h 0232 8] Reserved3 : 0000000000000000
+
+[0F0h 0240 1] Subtable Type : 01 [Memory Affinity]
+[0F1h 0241 1] Length : 28
+
+[0F2h 0242 4] Proximity Domain : 00000001
+[0F6h 0246 2] Reserved1 : 0000
+[0F8h 0248 8] Base Address : 0000000100000000
+[100h 0256 8] Address Length : 00000000B8000000
+[108h 0264 4] Reserved2 : 00000000
+[10Ch 0268 4] Flags (decoded below) : 00000003
+ Enabled : 1
+ Hot Pluggable : 1
+ Non-Volatile : 0
+[110h 0272 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 280 (0x118)
+
+ 0000: 53 52 41 54 18 01 00 00 01 C0 42 4F 43 48 53 20 // SRAT......BOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 10 00 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 0060: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0070: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 0080: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................
+ 0090: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00A0: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(..............
+ 00B0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00F0: 01 28 01 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(..............
+ 0100: 00 00 00 B8 00 00 00 00 00 00 00 00 03 00 00 00 // ................
+ 0110: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
@@ -0,0 +1,168 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/SRAT.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 00000130
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 36
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[031h 0049 1] Length : 10
+
+[032h 0050 1] Proximity Domain Low(8) : 00
+[033h 0051 1] Apic ID : 00
+[034h 0052 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[038h 0056 1] Local Sapic EID : 00
+[039h 0057 3] Proximity Domain High(24) : 000000
+[03Ch 0060 4] Clock Domain : 00000000
+
+[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[041h 0065 1] Length : 10
+
+[042h 0066 1] Proximity Domain Low(8) : 00
+[043h 0067 1] Apic ID : 01
+[044h 0068 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[048h 0072 1] Local Sapic EID : 00
+[049h 0073 3] Proximity Domain High(24) : 000000
+[04Ch 0076 4] Clock Domain : 00000000
+
+[050h 0080 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[051h 0081 1] Length : 10
+
+[052h 0082 1] Proximity Domain Low(8) : 00
+[053h 0083 1] Apic ID : 02
+[054h 0084 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[058h 0088 1] Local Sapic EID : 00
+[059h 0089 3] Proximity Domain High(24) : 000000
+[05Ch 0092 4] Clock Domain : 00000000
+
+[060h 0096 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[061h 0097 1] Length : 10
+
+[062h 0098 1] Proximity Domain Low(8) : 01
+[063h 0099 1] Apic ID : 04
+[064h 0100 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[068h 0104 1] Local Sapic EID : 00
+[069h 0105 3] Proximity Domain High(24) : 000000
+[06Ch 0108 4] Clock Domain : 00000000
+
+[070h 0112 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[071h 0113 1] Length : 10
+
+[072h 0114 1] Proximity Domain Low(8) : 01
+[073h 0115 1] Apic ID : 05
+[074h 0116 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[078h 0120 1] Local Sapic EID : 00
+[079h 0121 3] Proximity Domain High(24) : 000000
+[07Ch 0124 4] Clock Domain : 00000000
+
+[080h 0128 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[081h 0129 1] Length : 10
+
+[082h 0130 1] Proximity Domain Low(8) : 01
+[083h 0131 1] Apic ID : 06
+[084h 0132 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[088h 0136 1] Local Sapic EID : 00
+[089h 0137 3] Proximity Domain High(24) : 000000
+[08Ch 0140 4] Clock Domain : 00000000
+
+[090h 0144 1] Subtable Type : 01 [Memory Affinity]
+[091h 0145 1] Length : 28
+
+[092h 0146 4] Proximity Domain : 00000000
+[096h 0150 2] Reserved1 : 0000
+[098h 0152 8] Base Address : 0000000000000000
+[0A0h 0160 8] Address Length : 00000000000A0000
+[0A8h 0168 4] Reserved2 : 00000000
+[0ACh 0172 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0B0h 0176 8] Reserved3 : 0000000000000000
+
+[0B8h 0184 1] Subtable Type : 01 [Memory Affinity]
+[0B9h 0185 1] Length : 28
+
+[0BAh 0186 4] Proximity Domain : 00000000
+[0BEh 0190 2] Reserved1 : 0000
+[0C0h 0192 8] Base Address : 0000000000100000
+[0C8h 0200 8] Address Length : 0000000003F00000
+[0D0h 0208 4] Reserved2 : 00000000
+[0D4h 0212 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0D8h 0216 8] Reserved3 : 0000000000000000
+
+[0E0h 0224 1] Subtable Type : 01 [Memory Affinity]
+[0E1h 0225 1] Length : 28
+
+[0E2h 0226 4] Proximity Domain : 00000001
+[0E6h 0230 2] Reserved1 : 0000
+[0E8h 0232 8] Base Address : 0000000004000000
+[0F0h 0240 8] Address Length : 0000000004000000
+[0F8h 0248 4] Reserved2 : 00000000
+[0FCh 0252 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[100h 0256 8] Reserved3 : 0000000000000000
+
+[108h 0264 1] Subtable Type : 01 [Memory Affinity]
+[109h 0265 1] Length : 28
+
+[10Ah 0266 4] Proximity Domain : 00000000
+[10Eh 0270 2] Reserved1 : 0000
+[110h 0272 8] Base Address : 0000000000000000
+[118h 0280 8] Address Length : 0000000000000000
+[120h 0288 4] Reserved2 : 00000000
+[124h 0292 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[128h 0296 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 304 (0x130)
+
+ 0000: 53 52 41 54 30 01 00 00 01 36 42 4F 43 48 53 20 // SRAT0....6BOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 10 00 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 00 10 00 02 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0060: 00 10 01 04 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0070: 00 10 01 05 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 10 01 06 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 00A0: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 00C0: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................
+ 00D0: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(..............
+ 00F0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0100: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 0110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,194 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/SRAT.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 00000188
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 68
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[031h 0049 1] Length : 10
+
+[032h 0050 1] Proximity Domain Low(8) : 00
+[033h 0051 1] Apic ID : 00
+[034h 0052 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[038h 0056 1] Local Sapic EID : 00
+[039h 0057 3] Proximity Domain High(24) : 000000
+[03Ch 0060 4] Clock Domain : 00000000
+
+[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[041h 0065 1] Length : 10
+
+[042h 0066 1] Proximity Domain Low(8) : 01
+[043h 0067 1] Apic ID : 01
+[044h 0068 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[048h 0072 1] Local Sapic EID : 00
+[049h 0073 3] Proximity Domain High(24) : 000000
+[04Ch 0076 4] Clock Domain : 00000000
+
+[050h 0080 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[051h 0081 1] Length : 10
+
+[052h 0082 1] Proximity Domain Low(8) : 02
+[053h 0083 1] Apic ID : 02
+[054h 0084 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[058h 0088 1] Local Sapic EID : 00
+[059h 0089 3] Proximity Domain High(24) : 000000
+[05Ch 0092 4] Clock Domain : 00000000
+
+[060h 0096 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[061h 0097 1] Length : 10
+
+[062h 0098 1] Proximity Domain Low(8) : 03
+[063h 0099 1] Apic ID : 03
+[064h 0100 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[068h 0104 1] Local Sapic EID : 00
+[069h 0105 3] Proximity Domain High(24) : 000000
+[06Ch 0108 4] Clock Domain : 00000000
+
+[070h 0112 1] Subtable Type : 01 [Memory Affinity]
+[071h 0113 1] Length : 28
+
+[072h 0114 4] Proximity Domain : 00000000
+[076h 0118 2] Reserved1 : 0000
+[078h 0120 8] Base Address : 0000000000000000
+[080h 0128 8] Address Length : 00000000000A0000
+[088h 0136 4] Reserved2 : 00000000
+[08Ch 0140 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[090h 0144 8] Reserved3 : 0000000000000000
+
+[098h 0152 1] Subtable Type : 01 [Memory Affinity]
+[099h 0153 1] Length : 28
+
+[09Ah 0154 4] Proximity Domain : 00000000
+[09Eh 0158 2] Reserved1 : 0000
+[0A0h 0160 8] Base Address : 0000000000100000
+[0A8h 0168 8] Address Length : 0000000001F00000
+[0B0h 0176 4] Reserved2 : 00000000
+[0B4h 0180 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0B8h 0184 8] Reserved3 : 0000000000000000
+
+[0C0h 0192 1] Subtable Type : 01 [Memory Affinity]
+[0C1h 0193 1] Length : 28
+
+[0C2h 0194 4] Proximity Domain : 00000001
+[0C6h 0198 2] Reserved1 : 0000
+[0C8h 0200 8] Base Address : 0000000002000000
+[0D0h 0208 8] Address Length : 0000000002000000
+[0D8h 0216 4] Reserved2 : 00000000
+[0DCh 0220 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0E0h 0224 8] Reserved3 : 0000000000000000
+
+[0E8h 0232 1] Subtable Type : 01 [Memory Affinity]
+[0E9h 0233 1] Length : 28
+
+[0EAh 0234 4] Proximity Domain : 00000002
+[0EEh 0238 2] Reserved1 : 0000
+[0F0h 0240 8] Base Address : 0000000004000000
+[0F8h 0248 8] Address Length : 0000000002000000
+[100h 0256 4] Reserved2 : 00000000
+[104h 0260 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[108h 0264 8] Reserved3 : 0000000000000000
+
+[110h 0272 1] Subtable Type : 01 [Memory Affinity]
+[111h 0273 1] Length : 28
+
+[112h 0274 4] Proximity Domain : 00000003
+[116h 0278 2] Reserved1 : 0000
+[118h 0280 8] Base Address : 0000000006000000
+[120h 0288 8] Address Length : 0000000002000000
+[128h 0296 4] Reserved2 : 00000000
+[12Ch 0300 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[130h 0304 8] Reserved3 : 0000000000000000
+
+[138h 0312 1] Subtable Type : 01 [Memory Affinity]
+[139h 0313 1] Length : 28
+
+[13Ah 0314 4] Proximity Domain : 00000002
+[13Eh 0318 2] Reserved1 : 0000
+[140h 0320 8] Base Address : 0000000108000000
+[148h 0328 8] Address Length : 0000000008000000
+[150h 0336 4] Reserved2 : 00000000
+[154h 0340 4] Flags (decoded below) : 00000005
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 1
+[158h 0344 8] Reserved3 : 0000000000000000
+
+[160h 0352 1] Subtable Type : 01 [Memory Affinity]
+[161h 0353 1] Length : 28
+
+[162h 0354 4] Proximity Domain : 00000003
+[166h 0358 2] Reserved1 : 0000
+[168h 0360 8] Base Address : 0000000100000000
+[170h 0368 8] Address Length : 00000000F8000000
+[178h 0376 4] Reserved2 : 00000000
+[17Ch 0380 4] Flags (decoded below) : 00000003
+ Enabled : 1
+ Hot Pluggable : 1
+ Non-Volatile : 0
+[180h 0384 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 392 (0x188)
+
+ 0000: 53 52 41 54 88 01 00 00 01 68 42 4F 43 48 53 20 // SRAT.....hBOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 10 01 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 00 10 02 02 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0060: 00 10 03 03 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0070: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 0080: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0090: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 00A0: 00 00 10 00 00 00 00 00 00 00 F0 01 00 00 00 00 // ................
+ 00B0: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 01 28 01 00 00 00 00 00 00 00 00 02 00 00 00 00 // .(..............
+ 00D0: 00 00 00 02 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 00E0: 00 00 00 00 00 00 00 00 01 28 02 00 00 00 00 00 // .........(......
+ 00F0: 00 00 00 04 00 00 00 00 00 00 00 02 00 00 00 00 // ................
+ 0100: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0110: 01 28 03 00 00 00 00 00 00 00 00 06 00 00 00 00 // .(..............
+ 0120: 00 00 00 02 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0130: 00 00 00 00 00 00 00 00 01 28 02 00 00 00 00 00 // .........(......
+ 0140: 00 00 00 08 01 00 00 00 00 00 00 08 00 00 00 00 // ................
+ 0150: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0160: 01 28 03 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(..............
+ 0170: 00 00 00 F8 00 00 00 00 00 00 00 00 03 00 00 00 // ................
+ 0180: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
@@ -0,0 +1,108 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/SRAT.numamem, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 000000E0
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : F5
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[031h 0049 1] Length : 10
+
+[032h 0050 1] Proximity Domain Low(8) : 00
+[033h 0051 1] Apic ID : 00
+[034h 0052 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[038h 0056 1] Local Sapic EID : 00
+[039h 0057 3] Proximity Domain High(24) : 000000
+[03Ch 0060 4] Clock Domain : 00000000
+
+[040h 0064 1] Subtable Type : 01 [Memory Affinity]
+[041h 0065 1] Length : 28
+
+[042h 0066 4] Proximity Domain : 00000001
+[046h 0070 2] Reserved1 : 0000
+[048h 0072 8] Base Address : 0000000000000000
+[050h 0080 8] Address Length : 00000000000A0000
+[058h 0088 4] Reserved2 : 00000000
+[05Ch 0092 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[060h 0096 8] Reserved3 : 0000000000000000
+
+[068h 0104 1] Subtable Type : 01 [Memory Affinity]
+[069h 0105 1] Length : 28
+
+[06Ah 0106 4] Proximity Domain : 00000001
+[06Eh 0110 2] Reserved1 : 0000
+[070h 0112 8] Base Address : 0000000000100000
+[078h 0120 8] Address Length : 0000000007F00000
+[080h 0128 4] Reserved2 : 00000000
+[084h 0132 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[088h 0136 8] Reserved3 : 0000000000000000
+
+[090h 0144 1] Subtable Type : 01 [Memory Affinity]
+[091h 0145 1] Length : 28
+
+[092h 0146 4] Proximity Domain : 00000000
+[096h 0150 2] Reserved1 : 0000
+[098h 0152 8] Base Address : 0000000000000000
+[0A0h 0160 8] Address Length : 0000000000000000
+[0A8h 0168 4] Reserved2 : 00000000
+[0ACh 0172 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0B0h 0176 8] Reserved3 : 0000000000000000
+
+[0B8h 0184 1] Subtable Type : 01 [Memory Affinity]
+[0B9h 0185 1] Length : 28
+
+[0BAh 0186 4] Proximity Domain : 00000000
+[0BEh 0190 2] Reserved1 : 0000
+[0C0h 0192 8] Base Address : 0000000000000000
+[0C8h 0200 8] Address Length : 0000000000000000
+[0D0h 0208 4] Reserved2 : 00000000
+[0D4h 0212 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0D8h 0216 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 224 (0xE0)
+
+ 0000: 53 52 41 54 E0 00 00 00 01 F5 42 4F 43 48 53 20 // SRAT......BOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 01 28 01 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 01 28 01 00 00 00 00 00 // .........(......
+ 0070: 00 00 10 00 00 00 00 00 00 00 F0 07 00 00 00 00 // ................
+ 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,125 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/SRAT.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 00000108
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : A2
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[031h 0049 1] Length : 10
+
+[032h 0050 1] Proximity Domain Low(8) : 00
+[033h 0051 1] Apic ID : 00
+[034h 0052 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[038h 0056 1] Local Sapic EID : 00
+[039h 0057 3] Proximity Domain High(24) : 000000
+[03Ch 0060 4] Clock Domain : 00000000
+
+[040h 0064 1] Subtable Type : 01 [Memory Affinity]
+[041h 0065 1] Length : 28
+
+[042h 0066 4] Proximity Domain : 00000000
+[046h 0070 2] Reserved1 : 0000
+[048h 0072 8] Base Address : 0000000000000000
+[050h 0080 8] Address Length : 00000000000A0000
+[058h 0088 4] Reserved2 : 00000000
+[05Ch 0092 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[060h 0096 8] Reserved3 : 0000000000000000
+
+[068h 0104 1] Subtable Type : 01 [Memory Affinity]
+[069h 0105 1] Length : 28
+
+[06Ah 0106 4] Proximity Domain : 00000000
+[06Eh 0110 2] Reserved1 : 0000
+[070h 0112 8] Base Address : 0000000000100000
+[078h 0120 8] Address Length : 0000000003F00000
+[080h 0128 4] Reserved2 : 00000000
+[084h 0132 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[088h 0136 8] Reserved3 : 0000000000000000
+
+[090h 0144 1] Subtable Type : 01 [Memory Affinity]
+[091h 0145 1] Length : 28
+
+[092h 0146 4] Proximity Domain : 00000001
+[096h 0150 2] Reserved1 : 0000
+[098h 0152 8] Base Address : 0000000004000000
+[0A0h 0160 8] Address Length : 0000000004000000
+[0A8h 0168 4] Reserved2 : 00000000
+[0ACh 0172 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0B0h 0176 8] Reserved3 : 0000000000000000
+
+[0B8h 0184 1] Subtable Type : 01 [Memory Affinity]
+[0B9h 0185 1] Length : 28
+
+[0BAh 0186 4] Proximity Domain : 00000000
+[0BEh 0190 2] Reserved1 : 0000
+[0C0h 0192 8] Base Address : 0000000000000000
+[0C8h 0200 8] Address Length : 0000000000000000
+[0D0h 0208 4] Reserved2 : 00000000
+[0D4h 0212 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0D8h 0216 8] Reserved3 : 0000000000000000
+
+[0E0h 0224 1] Subtable Type : 01 [Memory Affinity]
+[0E1h 0225 1] Length : 28
+
+[0E2h 0226 4] Proximity Domain : 00000001
+[0E6h 0230 2] Reserved1 : 0000
+[0E8h 0232 8] Base Address : 0000000100000000
+[0F0h 0240 8] Address Length : 00000000F8000000
+[0F8h 0248 4] Reserved2 : 00000000
+[0FCh 0252 4] Flags (decoded below) : 00000003
+ Enabled : 1
+ Hot Pluggable : 1
+ Non-Volatile : 0
+[100h 0256 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 264 (0x108)
+
+ 0000: 53 52 41 54 08 01 00 00 01 A2 42 4F 43 48 53 20 // SRAT......BOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 0070: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................
+ 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(..............
+ 00A0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 01 28 01 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(..............
+ 00F0: 00 00 00 F8 00 00 00 00 00 00 00 00 03 00 00 00 // ................
+ 0100: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
@@ -0,0 +1,108 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/SRAT.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 000000E0
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : F5
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[031h 0049 1] Length : 10
+
+[032h 0050 1] Proximity Domain Low(8) : 00
+[033h 0051 1] Apic ID : 00
+[034h 0052 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[038h 0056 1] Local Sapic EID : 00
+[039h 0057 3] Proximity Domain High(24) : 000000
+[03Ch 0060 4] Clock Domain : 00000000
+
+[040h 0064 1] Subtable Type : 01 [Memory Affinity]
+[041h 0065 1] Length : 28
+
+[042h 0066 4] Proximity Domain : 00000001
+[046h 0070 2] Reserved1 : 0000
+[048h 0072 8] Base Address : 0000000000000000
+[050h 0080 8] Address Length : 00000000000A0000
+[058h 0088 4] Reserved2 : 00000000
+[05Ch 0092 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[060h 0096 8] Reserved3 : 0000000000000000
+
+[068h 0104 1] Subtable Type : 01 [Memory Affinity]
+[069h 0105 1] Length : 28
+
+[06Ah 0106 4] Proximity Domain : 00000001
+[06Eh 0110 2] Reserved1 : 0000
+[070h 0112 8] Base Address : 0000000000100000
+[078h 0120 8] Address Length : 0000000007F00000
+[080h 0128 4] Reserved2 : 00000000
+[084h 0132 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[088h 0136 8] Reserved3 : 0000000000000000
+
+[090h 0144 1] Subtable Type : 01 [Memory Affinity]
+[091h 0145 1] Length : 28
+
+[092h 0146 4] Proximity Domain : 00000000
+[096h 0150 2] Reserved1 : 0000
+[098h 0152 8] Base Address : 0000000000000000
+[0A0h 0160 8] Address Length : 0000000000000000
+[0A8h 0168 4] Reserved2 : 00000000
+[0ACh 0172 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0B0h 0176 8] Reserved3 : 0000000000000000
+
+[0B8h 0184 1] Subtable Type : 01 [Memory Affinity]
+[0B9h 0185 1] Length : 28
+
+[0BAh 0186 4] Proximity Domain : 00000000
+[0BEh 0190 2] Reserved1 : 0000
+[0C0h 0192 8] Base Address : 0000000000000000
+[0C8h 0200 8] Address Length : 0000000000000000
+[0D0h 0208 4] Reserved2 : 00000000
+[0D4h 0212 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0D8h 0216 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 224 (0xE0)
+
+ 0000: 53 52 41 54 E0 00 00 00 01 F5 42 4F 43 48 53 20 // SRAT......BOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 01 28 01 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 01 28 01 00 00 00 00 00 // .........(......
+ 0070: 00 00 10 00 00 00 00 00 00 00 F0 07 00 00 00 00 // ................
+ 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,205 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/pc/SSDT.dimmpxm, Mon Sep 28 17:24:38 2020
+ *
+ * Original Table Header:
+ * Signature "SSDT"
+ * Length 0x000002DE (734)
+ * Revision 0x01
+ * Checksum 0x56
+ * OEM ID "BOCHS "
+ * OEM Table ID "NVDIMM"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001)
+{
+ Scope (\_SB)
+ {
+ Device (NVDR)
+ {
+ Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Hardware ID
+ Method (NCAL, 5, Serialized)
+ {
+ Local6 = MEMA /* \MEMA */
+ OperationRegion (NPIO, SystemIO, 0x0A18, 0x04)
+ OperationRegion (NRAM, SystemMemory, Local6, 0x1000)
+ Field (NPIO, DWordAcc, NoLock, Preserve)
+ {
+ NTFI, 32
+ }
+
+ Field (NRAM, DWordAcc, NoLock, Preserve)
+ {
+ HDLE, 32,
+ REVS, 32,
+ FUNC, 32,
+ FARG, 32672
+ }
+
+ Field (NRAM, DWordAcc, NoLock, Preserve)
+ {
+ RLEN, 32,
+ ODAT, 32736
+ }
+
+ If ((Arg4 == Zero))
+ {
+ Local0 = ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75cba")
+ }
+ ElseIf ((Arg4 == 0x00010000))
+ {
+ Local0 = ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62")
+ }
+ Else
+ {
+ Local0 = ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66")
+ }
+
+ If (((Local6 == Zero) | (Arg0 != Local0)))
+ {
+ If ((Arg2 == Zero))
+ {
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+
+ Return (Buffer (One)
+ {
+ 0x01 // .
+ })
+ }
+
+ HDLE = Arg4
+ REVS = Arg1
+ FUNC = Arg2
+ If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One)))
+ {
+ Local2 = Arg3 [Zero]
+ Local3 = DerefOf (Local2)
+ FARG = Local3
+ }
+
+ NTFI = Local6
+ Local1 = (RLEN - 0x04)
+ If ((Local1 < 0x08))
+ {
+ Local2 = Zero
+ Name (TBUF, Buffer (One)
+ {
+ 0x00 // .
+ })
+ Local7 = Buffer (Zero){}
+ While ((Local2 < Local1))
+ {
+ TBUF [Zero] = DerefOf (ODAT [Local2])
+ Concatenate (Local7, TBUF, Local7)
+ Local2++
+ }
+
+ Return (Local7)
+ }
+
+ Local1 = (Local1 << 0x03)
+ CreateField (ODAT, Zero, Local1, OBUF)
+ Return (OBUF) /* \_SB_.NVDR.NCAL.OBUF */
+ }
+
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ Return (NCAL (Arg0, Arg1, Arg2, Arg3, Zero))
+ }
+
+ Name (RSTA, Zero)
+ Method (RFIT, 1, Serialized)
+ {
+ Name (OFST, Zero)
+ OFST = Arg0
+ Local0 = NCAL (ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62"), One, One, Package (0x01)
+ {
+ OFST
+ }, 0x00010000)
+ CreateDWordField (Local0, Zero, STAU)
+ RSTA = STAU /* \_SB_.NVDR.RFIT.STAU */
+ If ((Zero != STAU))
+ {
+ Return (Buffer (Zero){})
+ }
+
+ Local1 = SizeOf (Local0)
+ Local1 -= 0x04
+ If ((Local1 == Zero))
+ {
+ Return (Buffer (Zero){})
+ }
+
+ CreateField (Local0, 0x20, (Local1 << 0x03), BUFF)
+ Return (BUFF) /* \_SB_.NVDR.RFIT.BUFF */
+ }
+
+ Method (_FIT, 0, Serialized) // _FIT: Firmware Interface Table
+ {
+ Local2 = Buffer (Zero){}
+ Local3 = Zero
+ While (One)
+ {
+ Local0 = RFIT (Local3)
+ Local1 = SizeOf (Local0)
+ If ((RSTA == 0x0100))
+ {
+ Local2 = Buffer (Zero){}
+ Local3 = Zero
+ }
+ Else
+ {
+ If ((Local1 == Zero))
+ {
+ Return (Local2)
+ }
+
+ Local3 += Local1
+ Concatenate (Local2, Local0, Local2)
+ }
+ }
+ }
+
+ Device (NV00)
+ {
+ Name (_ADR, One) // _ADR: Address
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ Return (NCAL (Arg0, Arg1, Arg2, Arg3, One))
+ }
+ }
+
+ Device (NV01)
+ {
+ Name (_ADR, 0x02) // _ADR: Address
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x02))
+ }
+ }
+
+ Device (NV02)
+ {
+ Name (_ADR, 0x03) // _ADR: Address
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x03))
+ }
+ }
+ }
+ }
+
+ Name (MEMA, 0x07FFE000)
+}
+
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/WAET.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/WAET.bridge, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/WAET.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/WAET.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/WAET.roothp, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/WAET.ipmikcs, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/WAET.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/pc/WAET.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,112 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/APIC.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000080
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : DA
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[03Ch 0060 1] Subtable Type : 01 [I/O APIC]
+[03Dh 0061 1] Length : 0C
+[03Eh 0062 1] I/O Apic ID : 00
+[03Fh 0063 1] Reserved : 00
+[040h 0064 4] Address : FEC00000
+[044h 0068 4] Interrupt : 00000000
+
+[048h 0072 1] Subtable Type : 02 [Interrupt Source Override]
+[049h 0073 1] Length : 0A
+[04Ah 0074 1] Bus : 00
+[04Bh 0075 1] Source : 00
+[04Ch 0076 4] Interrupt : 00000002
+[050h 0080 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[052h 0082 1] Subtable Type : 02 [Interrupt Source Override]
+[053h 0083 1] Length : 0A
+[054h 0084 1] Bus : 00
+[055h 0085 1] Source : 05
+[056h 0086 4] Interrupt : 00000005
+[05Ah 0090 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[05Ch 0092 1] Subtable Type : 02 [Interrupt Source Override]
+[05Dh 0093 1] Length : 0A
+[05Eh 0094 1] Bus : 00
+[05Fh 0095 1] Source : 09
+[060h 0096 4] Interrupt : 00000009
+[064h 0100 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[066h 0102 1] Subtable Type : 02 [Interrupt Source Override]
+[067h 0103 1] Length : 0A
+[068h 0104 1] Bus : 00
+[069h 0105 1] Source : 0A
+[06Ah 0106 4] Interrupt : 0000000A
+[06Eh 0110 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[070h 0112 1] Subtable Type : 02 [Interrupt Source Override]
+[071h 0113 1] Length : 0A
+[072h 0114 1] Bus : 00
+[073h 0115 1] Source : 0B
+[074h 0116 4] Interrupt : 0000000B
+[078h 0120 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[07Ah 0122 1] Subtable Type : 04 [Local APIC NMI]
+[07Bh 0123 1] Length : 06
+[07Ch 0124 1] Processor ID : FF
+[07Dh 0125 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[07Fh 0127 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 128 (0x80)
+
+ 0000: 41 50 49 43 80 00 00 00 01 DA 42 4F 43 48 53 20 // APIC......BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 00 08 01 01 01 00 00 00 01 0C 00 00 // ................
+ 0040: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................
+ 0050: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................
+ 0060: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................
+ 0070: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................
new file mode 100644
GIT binary patch
literal 120
zcmZ<^@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2jnsGfW!{`1CdNz
hKn!AlSgfo-nis_4<b<)ffC?aD+}vOm3)_F75db|X4FLcE
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,104 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/APIC.bridge, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000078
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : ED
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 01 [I/O APIC]
+[035h 0053 1] Length : 0C
+[036h 0054 1] I/O Apic ID : 00
+[037h 0055 1] Reserved : 00
+[038h 0056 4] Address : FEC00000
+[03Ch 0060 4] Interrupt : 00000000
+
+[040h 0064 1] Subtable Type : 02 [Interrupt Source Override]
+[041h 0065 1] Length : 0A
+[042h 0066 1] Bus : 00
+[043h 0067 1] Source : 00
+[044h 0068 4] Interrupt : 00000002
+[048h 0072 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override]
+[04Bh 0075 1] Length : 0A
+[04Ch 0076 1] Bus : 00
+[04Dh 0077 1] Source : 05
+[04Eh 0078 4] Interrupt : 00000005
+[052h 0082 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[054h 0084 1] Subtable Type : 02 [Interrupt Source Override]
+[055h 0085 1] Length : 0A
+[056h 0086 1] Bus : 00
+[057h 0087 1] Source : 09
+[058h 0088 4] Interrupt : 00000009
+[05Ch 0092 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override]
+[05Fh 0095 1] Length : 0A
+[060h 0096 1] Bus : 00
+[061h 0097 1] Source : 0A
+[062h 0098 4] Interrupt : 0000000A
+[066h 0102 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
+[069h 0105 1] Length : 0A
+[06Ah 0106 1] Bus : 00
+[06Bh 0107 1] Source : 0B
+[06Ch 0108 4] Interrupt : 0000000B
+[070h 0112 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[072h 0114 1] Subtable Type : 04 [Local APIC NMI]
+[073h 0115 1] Length : 06
+[074h 0116 1] Processor ID : FF
+[075h 0117 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[077h 0119 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 120 (0x78)
+
+ 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................
+ 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................
+ 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................
+ 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................
+ 0070: 0D 00 04 06 FF 00 00 01 // ........
new file mode 100644
@@ -0,0 +1,146 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/APIC.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 000000A0
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 7B
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[03Ch 0060 1] Subtable Type : 00 [Processor Local APIC]
+[03Dh 0061 1] Length : 08
+[03Eh 0062 1] Processor ID : 02
+[03Fh 0063 1] Local Apic ID : 02
+[040h 0064 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[044h 0068 1] Subtable Type : 00 [Processor Local APIC]
+[045h 0069 1] Length : 08
+[046h 0070 1] Processor ID : 03
+[047h 0071 1] Local Apic ID : 04
+[048h 0072 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[04Ch 0076 1] Subtable Type : 00 [Processor Local APIC]
+[04Dh 0077 1] Length : 08
+[04Eh 0078 1] Processor ID : 04
+[04Fh 0079 1] Local Apic ID : 05
+[050h 0080 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[054h 0084 1] Subtable Type : 00 [Processor Local APIC]
+[055h 0085 1] Length : 08
+[056h 0086 1] Processor ID : 05
+[057h 0087 1] Local Apic ID : 06
+[058h 0088 4] Flags (decoded below) : 00000000
+ Processor Enabled : 0
+ Runtime Online Capable : 0
+
+[05Ch 0092 1] Subtable Type : 01 [I/O APIC]
+[05Dh 0093 1] Length : 0C
+[05Eh 0094 1] I/O Apic ID : 00
+[05Fh 0095 1] Reserved : 00
+[060h 0096 4] Address : FEC00000
+[064h 0100 4] Interrupt : 00000000
+
+[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
+[069h 0105 1] Length : 0A
+[06Ah 0106 1] Bus : 00
+[06Bh 0107 1] Source : 00
+[06Ch 0108 4] Interrupt : 00000002
+[070h 0112 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[072h 0114 1] Subtable Type : 02 [Interrupt Source Override]
+[073h 0115 1] Length : 0A
+[074h 0116 1] Bus : 00
+[075h 0117 1] Source : 05
+[076h 0118 4] Interrupt : 00000005
+[07Ah 0122 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[07Ch 0124 1] Subtable Type : 02 [Interrupt Source Override]
+[07Dh 0125 1] Length : 0A
+[07Eh 0126 1] Bus : 00
+[07Fh 0127 1] Source : 09
+[080h 0128 4] Interrupt : 00000009
+[084h 0132 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[086h 0134 1] Subtable Type : 02 [Interrupt Source Override]
+[087h 0135 1] Length : 0A
+[088h 0136 1] Bus : 00
+[089h 0137 1] Source : 0A
+[08Ah 0138 4] Interrupt : 0000000A
+[08Eh 0142 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[090h 0144 1] Subtable Type : 02 [Interrupt Source Override]
+[091h 0145 1] Length : 0A
+[092h 0146 1] Bus : 00
+[093h 0147 1] Source : 0B
+[094h 0148 4] Interrupt : 0000000B
+[098h 0152 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[09Ah 0154 1] Subtable Type : 04 [Local APIC NMI]
+[09Bh 0155 1] Length : 06
+[09Ch 0156 1] Processor ID : FF
+[09Dh 0157 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[09Fh 0159 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 160 (0xA0)
+
+ 0000: 41 50 49 43 A0 00 00 00 01 7B 42 4F 43 48 53 20 // APIC.....{BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 00 08 01 01 01 00 00 00 00 08 02 02 // ................
+ 0040: 00 00 00 00 00 08 03 04 00 00 00 00 00 08 04 05 // ................
+ 0050: 00 00 00 00 00 08 05 06 00 00 00 00 01 0C 00 00 // ................
+ 0060: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................
+ 0070: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................
+ 0080: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................
+ 0090: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................
new file mode 100644
@@ -0,0 +1,129 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/APIC.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000090
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : AE
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[03Ch 0060 1] Subtable Type : 00 [Processor Local APIC]
+[03Dh 0061 1] Length : 08
+[03Eh 0062 1] Processor ID : 02
+[03Fh 0063 1] Local Apic ID : 02
+[040h 0064 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[044h 0068 1] Subtable Type : 00 [Processor Local APIC]
+[045h 0069 1] Length : 08
+[046h 0070 1] Processor ID : 03
+[047h 0071 1] Local Apic ID : 03
+[048h 0072 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[04Ch 0076 1] Subtable Type : 01 [I/O APIC]
+[04Dh 0077 1] Length : 0C
+[04Eh 0078 1] I/O Apic ID : 00
+[04Fh 0079 1] Reserved : 00
+[050h 0080 4] Address : FEC00000
+[054h 0084 4] Interrupt : 00000000
+
+[058h 0088 1] Subtable Type : 02 [Interrupt Source Override]
+[059h 0089 1] Length : 0A
+[05Ah 0090 1] Bus : 00
+[05Bh 0091 1] Source : 00
+[05Ch 0092 4] Interrupt : 00000002
+[060h 0096 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[062h 0098 1] Subtable Type : 02 [Interrupt Source Override]
+[063h 0099 1] Length : 0A
+[064h 0100 1] Bus : 00
+[065h 0101 1] Source : 05
+[066h 0102 4] Interrupt : 00000005
+[06Ah 0106 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[06Ch 0108 1] Subtable Type : 02 [Interrupt Source Override]
+[06Dh 0109 1] Length : 0A
+[06Eh 0110 1] Bus : 00
+[06Fh 0111 1] Source : 09
+[070h 0112 4] Interrupt : 00000009
+[074h 0116 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[076h 0118 1] Subtable Type : 02 [Interrupt Source Override]
+[077h 0119 1] Length : 0A
+[078h 0120 1] Bus : 00
+[079h 0121 1] Source : 0A
+[07Ah 0122 4] Interrupt : 0000000A
+[07Eh 0126 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[080h 0128 1] Subtable Type : 02 [Interrupt Source Override]
+[081h 0129 1] Length : 0A
+[082h 0130 1] Bus : 00
+[083h 0131 1] Source : 0B
+[084h 0132 4] Interrupt : 0000000B
+[088h 0136 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[08Ah 0138 1] Subtable Type : 04 [Local APIC NMI]
+[08Bh 0139 1] Length : 06
+[08Ch 0140 1] Processor ID : FF
+[08Dh 0141 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[08Fh 0143 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 144 (0x90)
+
+ 0000: 41 50 49 43 90 00 00 00 01 AE 42 4F 43 48 53 20 // APIC......BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 00 08 01 01 01 00 00 00 00 08 02 02 // ................
+ 0040: 01 00 00 00 00 08 03 03 01 00 00 00 01 0C 00 00 // ................
+ 0050: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................
+ 0060: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................
+ 0070: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................
+ 0080: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................
new file mode 100644
@@ -0,0 +1,104 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/APIC.tis, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000078
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : ED
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 01 [I/O APIC]
+[035h 0053 1] Length : 0C
+[036h 0054 1] I/O Apic ID : 00
+[037h 0055 1] Reserved : 00
+[038h 0056 4] Address : FEC00000
+[03Ch 0060 4] Interrupt : 00000000
+
+[040h 0064 1] Subtable Type : 02 [Interrupt Source Override]
+[041h 0065 1] Length : 0A
+[042h 0066 1] Bus : 00
+[043h 0067 1] Source : 00
+[044h 0068 4] Interrupt : 00000002
+[048h 0072 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override]
+[04Bh 0075 1] Length : 0A
+[04Ch 0076 1] Bus : 00
+[04Dh 0077 1] Source : 05
+[04Eh 0078 4] Interrupt : 00000005
+[052h 0082 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[054h 0084 1] Subtable Type : 02 [Interrupt Source Override]
+[055h 0085 1] Length : 0A
+[056h 0086 1] Bus : 00
+[057h 0087 1] Source : 09
+[058h 0088 4] Interrupt : 00000009
+[05Ch 0092 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override]
+[05Fh 0095 1] Length : 0A
+[060h 0096 1] Bus : 00
+[061h 0097 1] Source : 0A
+[062h 0098 4] Interrupt : 0000000A
+[066h 0102 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
+[069h 0105 1] Length : 0A
+[06Ah 0106 1] Bus : 00
+[06Bh 0107 1] Source : 0B
+[06Ch 0108 4] Interrupt : 0000000B
+[070h 0112 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[072h 0114 1] Subtable Type : 04 [Local APIC NMI]
+[073h 0115 1] Length : 06
+[074h 0116 1] Processor ID : FF
+[075h 0117 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[077h 0119 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 120 (0x78)
+
+ 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................
+ 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................
+ 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................
+ 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................
+ 0070: 0D 00 04 06 FF 00 00 01 // ........
new file mode 100644
GIT binary patch
literal 120
zcmZ<^@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2jnsGfW!{`1CdNz
hKn!AlSgfo-nis_4<b<)ffC?aD+}vOm3)_F75db|X4FLcE
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,104 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/APIC.ipmibt, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000078
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : ED
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 01 [I/O APIC]
+[035h 0053 1] Length : 0C
+[036h 0054 1] I/O Apic ID : 00
+[037h 0055 1] Reserved : 00
+[038h 0056 4] Address : FEC00000
+[03Ch 0060 4] Interrupt : 00000000
+
+[040h 0064 1] Subtable Type : 02 [Interrupt Source Override]
+[041h 0065 1] Length : 0A
+[042h 0066 1] Bus : 00
+[043h 0067 1] Source : 00
+[044h 0068 4] Interrupt : 00000002
+[048h 0072 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override]
+[04Bh 0075 1] Length : 0A
+[04Ch 0076 1] Bus : 00
+[04Dh 0077 1] Source : 05
+[04Eh 0078 4] Interrupt : 00000005
+[052h 0082 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[054h 0084 1] Subtable Type : 02 [Interrupt Source Override]
+[055h 0085 1] Length : 0A
+[056h 0086 1] Bus : 00
+[057h 0087 1] Source : 09
+[058h 0088 4] Interrupt : 00000009
+[05Ch 0092 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override]
+[05Fh 0095 1] Length : 0A
+[060h 0096 1] Bus : 00
+[061h 0097 1] Source : 0A
+[062h 0098 4] Interrupt : 0000000A
+[066h 0102 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
+[069h 0105 1] Length : 0A
+[06Ah 0106 1] Bus : 00
+[06Bh 0107 1] Source : 0B
+[06Ch 0108 4] Interrupt : 0000000B
+[070h 0112 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[072h 0114 1] Subtable Type : 04 [Local APIC NMI]
+[073h 0115 1] Length : 06
+[074h 0116 1] Processor ID : FF
+[075h 0117 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[077h 0119 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 120 (0x78)
+
+ 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................
+ 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................
+ 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................
+ 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................
+ 0070: 0D 00 04 06 FF 00 00 01 // ........
new file mode 100644
GIT binary patch
literal 120
zcmZ<^@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2jnsGfW!{`1CdNz
hKn!AlSgfo-nis_4<b<)ffC?aD+}vOm3)_F75db|X4FLcE
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,104 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/APIC.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000078
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : ED
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 01 [I/O APIC]
+[035h 0053 1] Length : 0C
+[036h 0054 1] I/O Apic ID : 00
+[037h 0055 1] Reserved : 00
+[038h 0056 4] Address : FEC00000
+[03Ch 0060 4] Interrupt : 00000000
+
+[040h 0064 1] Subtable Type : 02 [Interrupt Source Override]
+[041h 0065 1] Length : 0A
+[042h 0066 1] Bus : 00
+[043h 0067 1] Source : 00
+[044h 0068 4] Interrupt : 00000002
+[048h 0072 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override]
+[04Bh 0075 1] Length : 0A
+[04Ch 0076 1] Bus : 00
+[04Dh 0077 1] Source : 05
+[04Eh 0078 4] Interrupt : 00000005
+[052h 0082 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[054h 0084 1] Subtable Type : 02 [Interrupt Source Override]
+[055h 0085 1] Length : 0A
+[056h 0086 1] Bus : 00
+[057h 0087 1] Source : 09
+[058h 0088 4] Interrupt : 00000009
+[05Ch 0092 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override]
+[05Fh 0095 1] Length : 0A
+[060h 0096 1] Bus : 00
+[061h 0097 1] Source : 0A
+[062h 0098 4] Interrupt : 0000000A
+[066h 0102 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
+[069h 0105 1] Length : 0A
+[06Ah 0106 1] Bus : 00
+[06Bh 0107 1] Source : 0B
+[06Ch 0108 4] Interrupt : 0000000B
+[070h 0112 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[072h 0114 1] Subtable Type : 04 [Local APIC NMI]
+[073h 0115 1] Length : 06
+[074h 0116 1] Processor ID : FF
+[075h 0117 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[077h 0119 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 120 (0x78)
+
+ 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................
+ 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................
+ 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................
+ 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................
+ 0070: 0D 00 04 06 FF 00 00 01 // ........
new file mode 100644
GIT binary patch
literal 120
zcmZ<^@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2jnsGfW!{`1CdNz
hKn!AlSgfo-nis_4<b<)ffC?aD+}vOm3)_F75db|X4FLcE
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,104 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/APIC.mmio64, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000078
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : ED
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 01 [I/O APIC]
+[035h 0053 1] Length : 0C
+[036h 0054 1] I/O Apic ID : 00
+[037h 0055 1] Reserved : 00
+[038h 0056 4] Address : FEC00000
+[03Ch 0060 4] Interrupt : 00000000
+
+[040h 0064 1] Subtable Type : 02 [Interrupt Source Override]
+[041h 0065 1] Length : 0A
+[042h 0066 1] Bus : 00
+[043h 0067 1] Source : 00
+[044h 0068 4] Interrupt : 00000002
+[048h 0072 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override]
+[04Bh 0075 1] Length : 0A
+[04Ch 0076 1] Bus : 00
+[04Dh 0077 1] Source : 05
+[04Eh 0078 4] Interrupt : 00000005
+[052h 0082 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[054h 0084 1] Subtable Type : 02 [Interrupt Source Override]
+[055h 0085 1] Length : 0A
+[056h 0086 1] Bus : 00
+[057h 0087 1] Source : 09
+[058h 0088 4] Interrupt : 00000009
+[05Ch 0092 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override]
+[05Fh 0095 1] Length : 0A
+[060h 0096 1] Bus : 00
+[061h 0097 1] Source : 0A
+[062h 0098 4] Interrupt : 0000000A
+[066h 0102 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
+[069h 0105 1] Length : 0A
+[06Ah 0106 1] Bus : 00
+[06Bh 0107 1] Source : 0B
+[06Ch 0108 4] Interrupt : 0000000B
+[070h 0112 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[072h 0114 1] Subtable Type : 04 [Local APIC NMI]
+[073h 0115 1] Length : 06
+[074h 0116 1] Processor ID : FF
+[075h 0117 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[077h 0119 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 120 (0x78)
+
+ 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................
+ 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................
+ 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................
+ 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................
+ 0070: 0D 00 04 06 FF 00 00 01 // ........
new file mode 100644
GIT binary patch
literal 120
zcmZ<^@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2jnsGfW!{`1CdNz
hKn!AlSgfo-nis_4<b<)ffC?aD+}vOm3)_F75db|X4FLcE
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,104 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/APIC.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000078
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : ED
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 01 [I/O APIC]
+[035h 0053 1] Length : 0C
+[036h 0054 1] I/O Apic ID : 00
+[037h 0055 1] Reserved : 00
+[038h 0056 4] Address : FEC00000
+[03Ch 0060 4] Interrupt : 00000000
+
+[040h 0064 1] Subtable Type : 02 [Interrupt Source Override]
+[041h 0065 1] Length : 0A
+[042h 0066 1] Bus : 00
+[043h 0067 1] Source : 00
+[044h 0068 4] Interrupt : 00000002
+[048h 0072 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override]
+[04Bh 0075 1] Length : 0A
+[04Ch 0076 1] Bus : 00
+[04Dh 0077 1] Source : 05
+[04Eh 0078 4] Interrupt : 00000005
+[052h 0082 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[054h 0084 1] Subtable Type : 02 [Interrupt Source Override]
+[055h 0085 1] Length : 0A
+[056h 0086 1] Bus : 00
+[057h 0087 1] Source : 09
+[058h 0088 4] Interrupt : 00000009
+[05Ch 0092 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override]
+[05Fh 0095 1] Length : 0A
+[060h 0096 1] Bus : 00
+[061h 0097 1] Source : 0A
+[062h 0098 4] Interrupt : 0000000A
+[066h 0102 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
+[069h 0105 1] Length : 0A
+[06Ah 0106 1] Bus : 00
+[06Bh 0107 1] Source : 0B
+[06Ch 0108 4] Interrupt : 0000000B
+[070h 0112 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[072h 0114 1] Subtable Type : 04 [Local APIC NMI]
+[073h 0115 1] Length : 06
+[074h 0116 1] Processor ID : FF
+[075h 0117 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[077h 0119 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 120 (0x78)
+
+ 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................
+ 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................
+ 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................
+ 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................
+ 0070: 0D 00 04 06 FF 00 00 01 // ........
new file mode 100644
GIT binary patch
literal 120
zcmZ<^@N}+VU|?W;>*Vk35v<@85#a0y6k`O6f!H9Lf#JbFFwFr}2jnsGfW!{`1CdNz
hKn!AlSgfo-nis_4<b<)ffC?aD+}vOm3)_F75db|X4FLcE
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,104 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/APIC.tis, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 00000078
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : ED
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Runtime Online Capable : 0
+
+[034h 0052 1] Subtable Type : 01 [I/O APIC]
+[035h 0053 1] Length : 0C
+[036h 0054 1] I/O Apic ID : 00
+[037h 0055 1] Reserved : 00
+[038h 0056 4] Address : FEC00000
+[03Ch 0060 4] Interrupt : 00000000
+
+[040h 0064 1] Subtable Type : 02 [Interrupt Source Override]
+[041h 0065 1] Length : 0A
+[042h 0066 1] Bus : 00
+[043h 0067 1] Source : 00
+[044h 0068 4] Interrupt : 00000002
+[048h 0072 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override]
+[04Bh 0075 1] Length : 0A
+[04Ch 0076 1] Bus : 00
+[04Dh 0077 1] Source : 05
+[04Eh 0078 4] Interrupt : 00000005
+[052h 0082 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[054h 0084 1] Subtable Type : 02 [Interrupt Source Override]
+[055h 0085 1] Length : 0A
+[056h 0086 1] Bus : 00
+[057h 0087 1] Source : 09
+[058h 0088 4] Interrupt : 00000009
+[05Ch 0092 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override]
+[05Fh 0095 1] Length : 0A
+[060h 0096 1] Bus : 00
+[061h 0097 1] Source : 0A
+[062h 0098 4] Interrupt : 0000000A
+[066h 0102 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[068h 0104 1] Subtable Type : 02 [Interrupt Source Override]
+[069h 0105 1] Length : 0A
+[06Ah 0106 1] Bus : 00
+[06Bh 0107 1] Source : 0B
+[06Ch 0108 4] Interrupt : 0000000B
+[070h 0112 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+[072h 0114 1] Subtable Type : 04 [Local APIC NMI]
+[073h 0115 1] Length : 06
+[074h 0116 1] Processor ID : FF
+[075h 0117 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+[077h 0119 1] Interrupt Input LINT : 01
+
+Raw Table Data: Length 120 (0x78)
+
+ 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................
+ 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................
+ 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................
+ 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................
+ 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................
+ 0070: 0D 00 04 06 FF 00 00 01 // ........
GIT binary patch
delta 33
ocmexk^TmeCCD<jTM2>-hQE4NWiX5jKOH6#QQ@nuPWD7Z40H)^%$^ZZW
delta 42
xcmexj^T&qECD<jTMvj4jar;It6*(?HmYDcpr+5K3mdWOFw(KHo0nUCQ3;+zI3ef-n
GIT binary patch
delta 33
ocmZ4KzR;b^CD<iop)vyl<Nb|Xfy$h2EHUxHPVoYElT(##0jn<wjQ{`u
delta 42
xcmZ4JzS5n`CD<ior7{BpW64IYKxHmJmYDcpr+5K3mdPo~w(KHo0nUCQ3;_Fv3X}i<
new file mode 100644
@@ -0,0 +1,3436 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/q35/DSDT.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000232A (9002)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x79
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ Local0 &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != Local0))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = Local0
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ }
+
+ Return (Arg3)
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Name (PICF, Zero)
+ Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model
+ {
+ PICF = Arg0
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (PRTP, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ }
+ })
+ Name (PRTA, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSID,
+ Zero
+ }
+ })
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If ((PICF == Zero))
+ {
+ Return (PRTP) /* \_SB_.PCI0.PRTP */
+ }
+ Else
+ {
+ Return (PRTA) /* \_SB_.PCI0.PRTA */
+ }
+ }
+ }
+
+ Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PRQA, 8,
+ PRQB, 8,
+ PRQC, 8,
+ PRQD, 8,
+ Offset (0x08),
+ PRQE, 8,
+ PRQF, 8,
+ PRQG, 8,
+ PRQH, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ PRRI = (Arg0 & 0x0F)
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQA))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQA |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQA))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQB))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQB |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQB))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQC))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQC |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQC))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQD))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQD |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQD))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQE))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQE |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQE))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */
+ }
+ }
+
+ Device (LNKF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQF))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQF |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQF))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */
+ }
+ }
+
+ Device (LNKG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQG))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQG |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQG))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */
+ }
+ }
+
+ Device (LNKH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQH))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQH |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQH))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */
+ }
+ }
+
+ Device (GSIA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x11) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x12) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSID)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x13) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x16) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x17) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (SMB0)
+ {
+ Name (_ADR, 0x001F0003) // _ADR: Address
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0CD8, // Range Minimum
+ 0x0CD8, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (C001, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Device (\_SB.PCI0.MHPD)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "Memory hotplug resources") // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0A00, // Range Minimum
+ 0x0A00, // Range Maximum
+ 0x00, // Alignment
+ 0x18, // Length
+ )
+ })
+ OperationRegion (HPMR, SystemIO, 0x0A00, 0x18)
+ }
+
+ Device (\_SB.MHPC)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "DIMM devices") // _UID: Unique ID
+ Name (MDNR, 0x02)
+ Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MRBL, 32,
+ MRBH, 32,
+ MRLL, 32,
+ MRLH, 32,
+ MPX, 32
+ }
+
+ Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x14),
+ MES, 1,
+ MINS, 1,
+ MRMV, 1,
+ MEJ, 1
+ }
+
+ Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MSEL, 32,
+ MOEV, 32,
+ MOSC, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0B)
+ }
+
+ Mutex (MLCK, 0x00)
+ Method (MSCN, 0, NotSerialized)
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ While ((Local0 < MDNR))
+ {
+ MSEL = Local0
+ If ((MINS == One))
+ {
+ MTFY (Local0, One)
+ MINS = One
+ }
+ ElseIf ((MRMV == One))
+ {
+ MTFY (Local0, 0x03)
+ MRMV = One
+ }
+
+ Local0 += One
+ }
+
+ Release (MLCK)
+ Return (One)
+ }
+
+ Method (MRST, 1, NotSerialized)
+ {
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ If ((MES == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MCRS, 1, Serialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Name (MR64, ResourceTemplate ()
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Range Minimum
+ 0xFFFFFFFFFFFFFFFE, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0xFFFFFFFFFFFFFFFF, // Length
+ ,, _Y01, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address
+ CreateDWordField (MR64, 0x12, MINH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length
+ CreateDWordField (MR64, 0x2A, LENH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address
+ CreateDWordField (MR64, 0x1A, MAXH)
+ MINH = MRBH /* \_SB_.MHPC.MRBH */
+ MINL = MRBL /* \_SB_.MHPC.MRBL */
+ LENH = MRLH /* \_SB_.MHPC.MRLH */
+ LENL = MRLL /* \_SB_.MHPC.MRLL */
+ MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */
+ MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */
+ If ((MAXL < MINL))
+ {
+ MAXH += One
+ }
+
+ If ((MAXL < One))
+ {
+ MAXH -= One
+ }
+
+ MAXL -= One
+ If ((MAXH == Zero))
+ {
+ Name (MR32, ResourceTemplate ()
+ {
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0xFFFFFFFE, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xFFFFFFFF, // Length
+ ,, _Y02, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length
+ MIN = MINL /* \_SB_.MHPC.MCRS.MINL */
+ MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */
+ LEN = LENL /* \_SB_.MHPC.MCRS.LENL */
+ Release (MLCK)
+ Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */
+ }
+
+ Release (MLCK)
+ Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */
+ }
+
+ Method (MPXM, 1, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Local0 = MPX /* \_SB_.MHPC.MPX_ */
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MOST, 4, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MOEV = Arg1
+ MOSC = Arg2
+ Release (MLCK)
+ }
+
+ Method (MEJ0, 2, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MEJ = One
+ Release (MLCK)
+ }
+
+ Device (MP00)
+ {
+ Name (_UID, "0x00") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Device (MP01)
+ {
+ Name (_UID, "0x01") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Method (MTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (MP00, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (MP01, Arg1)
+ }
+ }
+ }
+
+ Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.MHPC.MSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xAFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xA8000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xC0000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x3EC00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x00000001C0000000, // Range Minimum
+ 0x00000009BFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000800000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0620, // Range Minimum
+ 0x0620, // Range Maximum
+ 0x01, // Alignment
+ 0x10, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S08)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ }
+ }
+ }
+}
+
GIT binary patch
delta 33
ocmeCRZL{Ta33dr-lVf0D+`W-YMUK;hH6}jTDPF)~vbmf;0GQ4QumAu6
delta 41
wcmZp(?X~4{33dtTm1AIF4ByD5BFE{^8WSJv6ffXD*<8+_U4$*b*)N0v0NR)dw*UYD
new file mode 100644
@@ -0,0 +1,3141 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/q35/DSDT.bridge, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00001E0F (7695)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x4B
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ Local0 &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != Local0))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = Local0
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ }
+
+ Return (Arg3)
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Name (PICF, Zero)
+ Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model
+ {
+ PICF = Arg0
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (PRTP, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ }
+ })
+ Name (PRTA, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSID,
+ Zero
+ }
+ })
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If ((PICF == Zero))
+ {
+ Return (PRTP) /* \_SB_.PCI0.PRTP */
+ }
+ Else
+ {
+ Return (PRTA) /* \_SB_.PCI0.PRTA */
+ }
+ }
+ }
+
+ Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PRQA, 8,
+ PRQB, 8,
+ PRQC, 8,
+ PRQD, 8,
+ Offset (0x08),
+ PRQE, 8,
+ PRQF, 8,
+ PRQG, 8,
+ PRQH, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ PRRI = (Arg0 & 0x0F)
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQA))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQA |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQA))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQB))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQB |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQB))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQC))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQC |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQC))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQD))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQD |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQD))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQE))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQE |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQE))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */
+ }
+ }
+
+ Device (LNKF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQF))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQF |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQF))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */
+ }
+ }
+
+ Device (LNKG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQG))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQG |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQG))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */
+ }
+ }
+
+ Device (LNKH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQH))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQH |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQH))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */
+ }
+ }
+
+ Device (GSIA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x11) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x12) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSID)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x13) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x16) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x17) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (SMB0)
+ {
+ Name (_ADR, 0x001F0003) // _ADR: Address
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0CD8, // Range Minimum
+ 0x0CD8, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xAFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xA8000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xC0000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x3EC00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000100000000, // Range Minimum
+ 0x00000008FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000800000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0620, // Range Minimum
+ 0x0620, // Range Maximum
+ 0x01, // Alignment
+ 0x10, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S08)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Device (S10)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ }
+ }
+ }
+}
+
GIT binary patch
delta 33
ocmX@(aKwSjCD<jzMS+2Vv27#Q7kN%MmYDcpr+5Lo$s7u{0IPfnO8@`>
delta 42
xcmX@&aK?elCD<jzM}dKXQF<fS7kMr}mYDcpr+5K3mdWf2w(KHo0nUCQ3;_Az3Q_<7
new file mode 100644
@@ -0,0 +1,3283 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/q35/DSDT.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00001FCD (8141)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x25
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ Local0 &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != Local0))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = Local0
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ }
+
+ Return (Arg3)
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Name (PICF, Zero)
+ Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model
+ {
+ PICF = Arg0
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (PRTP, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ }
+ })
+ Name (PRTA, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSID,
+ Zero
+ }
+ })
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If ((PICF == Zero))
+ {
+ Return (PRTP) /* \_SB_.PCI0.PRTP */
+ }
+ Else
+ {
+ Return (PRTA) /* \_SB_.PCI0.PRTA */
+ }
+ }
+ }
+
+ Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PRQA, 8,
+ PRQB, 8,
+ PRQC, 8,
+ PRQD, 8,
+ Offset (0x08),
+ PRQE, 8,
+ PRQF, 8,
+ PRQG, 8,
+ PRQH, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ PRRI = (Arg0 & 0x0F)
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQA))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQA |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQA))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQB))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQB |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQB))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQC))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQC |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQC))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQD))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQD |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQD))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQE))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQE |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQE))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */
+ }
+ }
+
+ Device (LNKF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQF))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQF |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQF))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */
+ }
+ }
+
+ Device (LNKG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQG))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQG |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQG))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */
+ }
+ }
+
+ Device (LNKH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQH))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQH |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQH))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */
+ }
+ }
+
+ Device (GSIA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x11) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x12) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSID)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x13) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x16) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x17) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (SMB0)
+ {
+ Name (_ADR, 0x001F0003) // _ADR: Address
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0CD8, // Range Minimum
+ 0x0CD8, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (C001, Arg1)
+ }
+
+ If ((Arg0 == 0x02))
+ {
+ Notify (C002, Arg1)
+ }
+
+ If ((Arg0 == 0x03))
+ {
+ Notify (C003, Arg1)
+ }
+
+ If ((Arg0 == 0x04))
+ {
+ Notify (C004, Arg1)
+ }
+
+ If ((Arg0 == 0x05))
+ {
+ Notify (C005, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+
+ Processor (C002, 0x02, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x02))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x02)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x02, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+
+ Processor (C003, 0x03, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x03))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x03, 0x04, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x03)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x03, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, One) // _PXM: Device Proximity
+ }
+
+ Processor (C004, 0x04, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x04))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x04, 0x05, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x04)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x04, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, One) // _PXM: Device Proximity
+ }
+
+ Processor (C005, 0x05, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x05))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x05, 0x06, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x05)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x05, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, One) // _PXM: Device Proximity
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xAFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xA8000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xC0000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x3EC00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000100000000, // Range Minimum
+ 0x00000008FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000800000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0620, // Range Minimum
+ 0x0620, // Range Maximum
+ 0x01, // Alignment
+ 0x10, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S08)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ }
+ }
+ }
+}
+
GIT binary patch
delta 33
pcmez5`O1^aCD<k8l?np`W6(yfSt^`vEHUxHPVoYElh>)(0sz0?3UmMf
delta 42
ycmaFm`N@;ZCD<k8lL`X^<MWMNvsAeJSYqOXo#F-DSSGJkv1J!w3vl)eVE_O$8Vq{?
new file mode 100644
@@ -0,0 +1,3535 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/q35/DSDT.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00002473 (9331)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xEE
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ External (_SB_.NVDR, UnknownObj)
+
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ Local0 &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != Local0))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = Local0
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ }
+
+ Return (Arg3)
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Name (PICF, Zero)
+ Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model
+ {
+ PICF = Arg0
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (PRTP, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
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+ 0x0011FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSID,
+ Zero
+ }
+ })
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If ((PICF == Zero))
+ {
+ Return (PRTP) /* \_SB_.PCI0.PRTP */
+ }
+ Else
+ {
+ Return (PRTA) /* \_SB_.PCI0.PRTA */
+ }
+ }
+ }
+
+ Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PRQA, 8,
+ PRQB, 8,
+ PRQC, 8,
+ PRQD, 8,
+ Offset (0x08),
+ PRQE, 8,
+ PRQF, 8,
+ PRQG, 8,
+ PRQH, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ PRRI = (Arg0 & 0x0F)
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQA))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQA |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQA))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQB))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQB |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQB))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQC))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQC |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQC))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQD))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQD |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQD))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQE))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQE |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQE))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */
+ }
+ }
+
+ Device (LNKF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQF))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQF |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQF))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */
+ }
+ }
+
+ Device (LNKG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQG))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQG |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQG))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */
+ }
+ }
+
+ Device (LNKH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQH))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQH |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQH))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */
+ }
+ }
+
+ Device (GSIA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x11) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x12) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSID)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x13) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x16) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x17) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (SMB0)
+ {
+ Name (_ADR, 0x001F0003) // _ADR: Address
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0CD8, // Range Minimum
+ 0x0CD8, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (C001, Arg1)
+ }
+
+ If ((Arg0 == 0x02))
+ {
+ Notify (C002, Arg1)
+ }
+
+ If ((Arg0 == 0x03))
+ {
+ Notify (C003, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+
+ Processor (C001, 0x01, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (One))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (One)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (One, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, One) // _PXM: Device Proximity
+ }
+
+ Processor (C002, 0x02, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x02))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x02)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x02, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, 0x02) // _PXM: Device Proximity
+ }
+
+ Processor (C003, 0x03, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (0x03))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ CEJ0 (0x03)
+ }
+
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (0x03, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, 0x03) // _PXM: Device Proximity
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Device (\_SB.PCI0.MHPD)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "Memory hotplug resources") // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0A00, // Range Minimum
+ 0x0A00, // Range Maximum
+ 0x00, // Alignment
+ 0x18, // Length
+ )
+ })
+ OperationRegion (HPMR, SystemIO, 0x0A00, 0x18)
+ }
+
+ Device (\_SB.MHPC)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "DIMM devices") // _UID: Unique ID
+ Name (MDNR, 0x03)
+ Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MRBL, 32,
+ MRBH, 32,
+ MRLL, 32,
+ MRLH, 32,
+ MPX, 32
+ }
+
+ Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x14),
+ MES, 1,
+ MINS, 1,
+ MRMV, 1,
+ MEJ, 1
+ }
+
+ Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MSEL, 32,
+ MOEV, 32,
+ MOSC, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0B)
+ }
+
+ Mutex (MLCK, 0x00)
+ Method (MSCN, 0, NotSerialized)
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ While ((Local0 < MDNR))
+ {
+ MSEL = Local0
+ If ((MINS == One))
+ {
+ MTFY (Local0, One)
+ MINS = One
+ }
+ ElseIf ((MRMV == One))
+ {
+ MTFY (Local0, 0x03)
+ MRMV = One
+ }
+
+ Local0 += One
+ }
+
+ Release (MLCK)
+ Return (One)
+ }
+
+ Method (MRST, 1, NotSerialized)
+ {
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ If ((MES == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MCRS, 1, Serialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Name (MR64, ResourceTemplate ()
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Range Minimum
+ 0xFFFFFFFFFFFFFFFE, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0xFFFFFFFFFFFFFFFF, // Length
+ ,, _Y01, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address
+ CreateDWordField (MR64, 0x12, MINH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length
+ CreateDWordField (MR64, 0x2A, LENH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address
+ CreateDWordField (MR64, 0x1A, MAXH)
+ MINH = MRBH /* \_SB_.MHPC.MRBH */
+ MINL = MRBL /* \_SB_.MHPC.MRBL */
+ LENH = MRLH /* \_SB_.MHPC.MRLH */
+ LENL = MRLL /* \_SB_.MHPC.MRLL */
+ MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */
+ MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */
+ If ((MAXL < MINL))
+ {
+ MAXH += One
+ }
+
+ If ((MAXL < One))
+ {
+ MAXH -= One
+ }
+
+ MAXL -= One
+ If ((MAXH == Zero))
+ {
+ Name (MR32, ResourceTemplate ()
+ {
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0xFFFFFFFE, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xFFFFFFFF, // Length
+ ,, _Y02, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length
+ MIN = MINL /* \_SB_.MHPC.MCRS.MINL */
+ MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */
+ LEN = LENL /* \_SB_.MHPC.MCRS.LENL */
+ Release (MLCK)
+ Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */
+ }
+
+ Release (MLCK)
+ Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */
+ }
+
+ Method (MPXM, 1, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Local0 = MPX /* \_SB_.MHPC.MPX_ */
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MOST, 4, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MOEV = Arg1
+ MOSC = Arg2
+ Release (MLCK)
+ }
+
+ Method (MEJ0, 2, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MEJ = One
+ Release (MLCK)
+ }
+
+ Device (MP00)
+ {
+ Name (_UID, "0x00") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Device (MP01)
+ {
+ Name (_UID, "0x01") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Device (MP02)
+ {
+ Name (_UID, "0x02") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Method (MTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (MP00, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (MP01, Arg1)
+ }
+
+ If ((Arg0 == 0x02))
+ {
+ Notify (MP02, Arg1)
+ }
+ }
+ }
+
+ Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.MHPC.MSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ Method (_E04, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ Notify (\_SB.NVDR, 0x80) // Status Change
+ }
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xAFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xA8000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xC0000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x3EC00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000200000000, // Range Minimum
+ 0x00000009FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000800000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0620, // Range Minimum
+ 0x0620, // Range Maximum
+ 0x01, // Alignment
+ 0x10, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S08)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ }
+ }
+ }
+}
+
new file mode 100644
@@ -0,0 +1,3351 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/q35/DSDT.tis, Mon Sep 28 17:24:38 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x000020D2 (8402)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xF4
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ Local0 &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != Local0))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = Local0
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ }
+
+ Return (Arg3)
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Name (PICF, Zero)
+ Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model
+ {
+ PICF = Arg0
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (PRTP, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ }
+ })
+ Name (PRTA, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSID,
+ Zero
+ }
+ })
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If ((PICF == Zero))
+ {
+ Return (PRTP) /* \_SB_.PCI0.PRTP */
+ }
+ Else
+ {
+ Return (PRTA) /* \_SB_.PCI0.PRTA */
+ }
+ }
+ }
+
+ Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PRQA, 8,
+ PRQB, 8,
+ PRQC, 8,
+ PRQD, 8,
+ Offset (0x08),
+ PRQE, 8,
+ PRQF, 8,
+ PRQG, 8,
+ PRQH, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ PRRI = (Arg0 & 0x0F)
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQA))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQA |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQA))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQB))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQB |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQB))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQC))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQC |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQC))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQD))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQD |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQD))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQE))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQE |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQE))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */
+ }
+ }
+
+ Device (LNKF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQF))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQF |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQF))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */
+ }
+ }
+
+ Device (LNKG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQG))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQG |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQG))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */
+ }
+ }
+
+ Device (LNKH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQH))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQH |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQH))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */
+ }
+ }
+
+ Device (GSIA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x11) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x12) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSID)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x13) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x16) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x17) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (SMB0)
+ {
+ Name (_ADR, 0x001F0003) // _ADR: Address
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0CD8, // Range Minimum
+ 0x0CD8, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Name (CNEW, Package (0xFF){})
+ Local3 = Zero
+ Local4 = One
+ While ((Local4 == One))
+ {
+ Local4 = Zero
+ Local0 = One
+ Local1 = Zero
+ While (((Local0 == One) && (Local3 < One)))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CSEL = Local3
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CDAT < Local3))
+ {
+ Break
+ }
+
+ If ((Local1 == 0xFF))
+ {
+ Local4 = One
+ Break
+ }
+
+ Local3 = \_SB.PCI0.PRES.CDAT
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CNEW [Local1] = Local3
+ Local1++
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (Local3, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+
+ Local3++
+ }
+
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ Local3 = DerefOf (CNEW [Local2])
+ CTFY (Local3, One)
+ Debug = Local3
+ \_SB.PCI0.PRES.CSEL = Local3
+ \_SB.PCI0.PRES.CINS = One
+ Local2++
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xAFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xA8000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xC0000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x3EC00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000100000000, // Range Minimum
+ 0x00000008FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000800000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ Memory32Fixed (ReadWrite,
+ 0xFED40000, // Address Base
+ 0x00005000, // Address Length
+ )
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0620, // Range Minimum
+ 0x0620, // Range Maximum
+ 0x01, // Alignment
+ 0x10, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S08)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Device (TPM)
+ {
+ Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xFED40000, // Address Base
+ 0x00005000, // Address Length
+ )
+ })
+ OperationRegion (TPP2, SystemMemory, 0xFED45100, 0x5A)
+ Field (TPP2, AnyAcc, NoLock, Preserve)
+ {
+ PPIN, 8,
+ PPIP, 32,
+ PPRP, 32,
+ PPRQ, 32,
+ PPRM, 32,
+ LPPR, 32
+ }
+
+ OperationRegion (TPP3, SystemMemory, 0xFED4515A, One)
+ Field (TPP3, ByteAcc, NoLock, Preserve)
+ {
+ MOVV, 8
+ }
+
+ Method (TPFN, 1, Serialized)
+ {
+ If ((Arg0 >= 0x0100))
+ {
+ Return (Zero)
+ }
+
+ OperationRegion (TPP1, SystemMemory, (0xFED45000 + Arg0), One)
+ Field (TPP1, ByteAcc, NoLock, Preserve)
+ {
+ TPPF, 8
+ }
+
+ Return (TPPF) /* \_SB_.PCI0.TPM_.TPFN.TPPF */
+ }
+
+ Name (TPM2, Package (0x02)
+ {
+ Zero,
+ Zero
+ })
+ Name (TPM3, Package (0x03)
+ {
+ Zero,
+ Zero,
+ Zero
+ })
+ Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
+ {
+ If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */))
+ {
+ If ((Arg2 == Zero))
+ {
+ Return (Buffer (0x02)
+ {
+ 0xFF, 0x01 // ..
+ })
+ }
+
+ If ((Arg2 == One))
+ {
+ Return ("1.3")
+ }
+
+ If ((Arg2 == 0x02))
+ {
+ Local0 = DerefOf (Arg3 [Zero])
+ Local1 = TPFN (Local0)
+ If (((Local1 & 0x07) == Zero))
+ {
+ Return (One)
+ }
+
+ PPRQ = Local0
+ PPRM = Zero
+ Return (Zero)
+ }
+
+ If ((Arg2 == 0x03))
+ {
+ If ((Arg1 == One))
+ {
+ TPM2 [One] = PPRQ /* \_SB_.PCI0.TPM_.PPRQ */
+ Return (TPM2) /* \_SB_.PCI0.TPM_.TPM2 */
+ }
+
+ If ((Arg1 == 0x02))
+ {
+ TPM3 [One] = PPRQ /* \_SB_.PCI0.TPM_.PPRQ */
+ TPM3 [0x02] = PPRM /* \_SB_.PCI0.TPM_.PPRM */
+ Return (TPM3) /* \_SB_.PCI0.TPM_.TPM3 */
+ }
+ }
+
+ If ((Arg2 == 0x04))
+ {
+ Return (0x02)
+ }
+
+ If ((Arg2 == 0x05))
+ {
+ TPM3 [One] = LPPR /* \_SB_.PCI0.TPM_.LPPR */
+ TPM3 [0x02] = PPRP /* \_SB_.PCI0.TPM_.PPRP */
+ Return (TPM3) /* \_SB_.PCI0.TPM_.TPM3 */
+ }
+
+ If ((Arg2 == 0x06))
+ {
+ Return (0x03)
+ }
+
+ If ((Arg2 == 0x07))
+ {
+ Local0 = DerefOf (Arg3 [Zero])
+ Local1 = TPFN (Local0)
+ If (((Local1 & 0x07) == Zero))
+ {
+ Return (One)
+ }
+
+ If (((Local1 & 0x07) == 0x02))
+ {
+ Return (0x03)
+ }
+
+ If ((Arg1 == One))
+ {
+ PPRQ = Local0
+ PPRM = Zero
+ }
+
+ If ((Arg1 == 0x02))
+ {
+ PPRQ = Local0
+ PPRM = DerefOf (Arg3 [One])
+ }
+
+ Return (Zero)
+ }
+
+ If ((Arg2 == 0x08))
+ {
+ Local0 = DerefOf (Arg3 [Zero])
+ Local1 = TPFN (Local0)
+ Return ((Local1 & 0x07))
+ }
+
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+
+ If ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))
+ {
+ If ((Arg2 == Zero))
+ {
+ Return (Buffer (One)
+ {
+ 0x03 // .
+ })
+ }
+
+ If ((Arg2 == One))
+ {
+ Local0 = DerefOf (Arg3 [Zero])
+ MOVV = Local0
+ Return (Zero)
+ }
+ }
+ }
+ }
+ }
+ }
+}
+
GIT binary patch
delta 33
ocmX?ZyWf_}CD<iozZ?StW7tNnd^t`xmYDcpr+5Lo$<1=M0IFIEcK`qY
delta 42
xcmdmQd)$`GCD<k8xEuom<LixF`Ep!-EHUxHPVoY6ER&n$Y}rNF0-XIq7yuRF3w{6q
new file mode 100644
@@ -0,0 +1,3156 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/q35/DSDT.ipmibt, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00001E49 (7753)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0xDF
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ Local0 &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != Local0))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = Local0
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ }
+
+ Return (Arg3)
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (MI1)
+ {
+ Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID
+ Name (_STR, "ipmi_bt") // _STR: Description String
+ Name (_UID, One) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x00E4, // Range Minimum
+ 0x00E6, // Range Maximum
+ 0x01, // Alignment
+ 0x03, // Length
+ )
+ IRQNoFlags ()
+ {5}
+ })
+ Name (_IFT, 0x03) // _IFT: IPMI Interface Type
+ Name (_SRV, 0x0200) // _SRV: IPMI Spec Revision
+ }
+
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Name (PICF, Zero)
+ Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model
+ {
+ PICF = Arg0
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (PRTP, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ }
+ })
+ Name (PRTA, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSID,
+ Zero
+ }
+ })
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If ((PICF == Zero))
+ {
+ Return (PRTP) /* \_SB_.PCI0.PRTP */
+ }
+ Else
+ {
+ Return (PRTA) /* \_SB_.PCI0.PRTA */
+ }
+ }
+ }
+
+ Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PRQA, 8,
+ PRQB, 8,
+ PRQC, 8,
+ PRQD, 8,
+ Offset (0x08),
+ PRQE, 8,
+ PRQF, 8,
+ PRQG, 8,
+ PRQH, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ PRRI = (Arg0 & 0x0F)
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQA))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQA |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQA))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQB))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQB |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQB))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQC))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQC |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQC))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQD))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQD |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQD))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQE))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQE |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQE))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */
+ }
+ }
+
+ Device (LNKF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQF))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQF |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQF))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */
+ }
+ }
+
+ Device (LNKG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQG))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQG |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQG))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */
+ }
+ }
+
+ Device (LNKH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQH))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQH |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQH))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */
+ }
+ }
+
+ Device (GSIA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x11) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x12) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSID)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x13) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x16) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x17) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (SMB0)
+ {
+ Name (_ADR, 0x001F0003) // _ADR: Address
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0CD8, // Range Minimum
+ 0x0CD8, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xAFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xA8000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xC0000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x3EC00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000100000000, // Range Minimum
+ 0x00000008FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000800000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0620, // Range Minimum
+ 0x0620, // Range Maximum
+ 0x01, // Alignment
+ 0x10, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S08)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ }
+ }
+ }
+}
+
GIT binary patch
delta 33
ocmX@@e%PJMCD<k8urdP!qsT_CVr5P@mYDcpr+5Lo$?eLv0IF08YybcN
delta 42
xcmX@?e%hVOCD<k8v@!z&<I0U(#mZcMEHUxHPVoY6ER)-mZP`WG0-XIq7yuP-3v&Pf
new file mode 100644
@@ -0,0 +1,3442 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/q35/DSDT.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000234D (9037)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x9D
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ Local0 &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != Local0))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = Local0
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ }
+
+ Return (Arg3)
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Name (PICF, Zero)
+ Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model
+ {
+ PICF = Arg0
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (PRTP, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
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+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSID,
+ Zero
+ }
+ })
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If ((PICF == Zero))
+ {
+ Return (PRTP) /* \_SB_.PCI0.PRTP */
+ }
+ Else
+ {
+ Return (PRTA) /* \_SB_.PCI0.PRTA */
+ }
+ }
+ }
+
+ Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PRQA, 8,
+ PRQB, 8,
+ PRQC, 8,
+ PRQD, 8,
+ Offset (0x08),
+ PRQE, 8,
+ PRQF, 8,
+ PRQG, 8,
+ PRQH, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ PRRI = (Arg0 & 0x0F)
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQA))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQA |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQA))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQB))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQB |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQB))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQC))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQC |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQC))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQD))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQD |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQD))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQE))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQE |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQE))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */
+ }
+ }
+
+ Device (LNKF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQF))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQF |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQF))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */
+ }
+ }
+
+ Device (LNKG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQG))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQG |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQG))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */
+ }
+ }
+
+ Device (LNKH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQH))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQH |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQH))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */
+ }
+ }
+
+ Device (GSIA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x11) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x12) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSID)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x13) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x16) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x17) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (SMB0)
+ {
+ Name (_ADR, 0x001F0003) // _ADR: Address
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0CD8, // Range Minimum
+ 0x0CD8, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Device (\_SB.PCI0.MHPD)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "Memory hotplug resources") // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0A00, // Range Minimum
+ 0x0A00, // Range Maximum
+ 0x00, // Alignment
+ 0x18, // Length
+ )
+ })
+ OperationRegion (HPMR, SystemIO, 0x0A00, 0x18)
+ }
+
+ Device (\_SB.MHPC)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "DIMM devices") // _UID: Unique ID
+ Name (MDNR, 0x03)
+ Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MRBL, 32,
+ MRBH, 32,
+ MRLL, 32,
+ MRLH, 32,
+ MPX, 32
+ }
+
+ Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x14),
+ MES, 1,
+ MINS, 1,
+ MRMV, 1,
+ MEJ, 1
+ }
+
+ Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MSEL, 32,
+ MOEV, 32,
+ MOSC, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0B)
+ }
+
+ Mutex (MLCK, 0x00)
+ Method (MSCN, 0, NotSerialized)
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ While ((Local0 < MDNR))
+ {
+ MSEL = Local0
+ If ((MINS == One))
+ {
+ MTFY (Local0, One)
+ MINS = One
+ }
+ ElseIf ((MRMV == One))
+ {
+ MTFY (Local0, 0x03)
+ MRMV = One
+ }
+
+ Local0 += One
+ }
+
+ Release (MLCK)
+ Return (One)
+ }
+
+ Method (MRST, 1, NotSerialized)
+ {
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ If ((MES == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MCRS, 1, Serialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Name (MR64, ResourceTemplate ()
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Range Minimum
+ 0xFFFFFFFFFFFFFFFE, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0xFFFFFFFFFFFFFFFF, // Length
+ ,, _Y01, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address
+ CreateDWordField (MR64, 0x12, MINH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length
+ CreateDWordField (MR64, 0x2A, LENH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address
+ CreateDWordField (MR64, 0x1A, MAXH)
+ MINH = MRBH /* \_SB_.MHPC.MRBH */
+ MINL = MRBL /* \_SB_.MHPC.MRBL */
+ LENH = MRLH /* \_SB_.MHPC.MRLH */
+ LENL = MRLL /* \_SB_.MHPC.MRLL */
+ MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */
+ MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */
+ If ((MAXL < MINL))
+ {
+ MAXH += One
+ }
+
+ If ((MAXL < One))
+ {
+ MAXH -= One
+ }
+
+ MAXL -= One
+ If ((MAXH == Zero))
+ {
+ Name (MR32, ResourceTemplate ()
+ {
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0xFFFFFFFE, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xFFFFFFFF, // Length
+ ,, _Y02, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length
+ MIN = MINL /* \_SB_.MHPC.MCRS.MINL */
+ MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */
+ LEN = LENL /* \_SB_.MHPC.MCRS.LENL */
+ Release (MLCK)
+ Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */
+ }
+
+ Release (MLCK)
+ Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */
+ }
+
+ Method (MPXM, 1, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Local0 = MPX /* \_SB_.MHPC.MPX_ */
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MOST, 4, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MOEV = Arg1
+ MOSC = Arg2
+ Release (MLCK)
+ }
+
+ Method (MEJ0, 2, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MEJ = One
+ Release (MLCK)
+ }
+
+ Device (MP00)
+ {
+ Name (_UID, "0x00") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Device (MP01)
+ {
+ Name (_UID, "0x01") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Device (MP02)
+ {
+ Name (_UID, "0x02") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Method (MTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (MP00, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (MP01, Arg1)
+ }
+
+ If ((Arg0 == 0x02))
+ {
+ Notify (MP02, Arg1)
+ }
+ }
+ }
+
+ Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.MHPC.MSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xAFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xA8000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xC0000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x3EC00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000200000000, // Range Minimum
+ 0x00000009FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000800000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0620, // Range Minimum
+ 0x0620, // Range Maximum
+ 0x01, // Alignment
+ 0x10, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S08)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ }
+ }
+ }
+}
+
GIT binary patch
delta 33
pcmaFndf%1HCD<k8z7hii<H?O&wMv{GtTFMyPVoW`lP4(o0|3FB3YP!?
delta 41
wcmccb`plKfCD<k8nGyp7W9mk(S|v_@)|mKUr+5MP$rF_P*+tj_oc%%=01~VVo&W#<
new file mode 100644
@@ -0,0 +1,3377 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/q35/DSDT.mmio64, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00002268 (8808)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x59
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ Local0 &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != Local0))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = Local0
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ }
+
+ Return (Arg3)
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Name (PICF, Zero)
+ Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model
+ {
+ PICF = Arg0
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (PRTP, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
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+ {
+ 0x0014FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSID,
+ Zero
+ }
+ })
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If ((PICF == Zero))
+ {
+ Return (PRTP) /* \_SB_.PCI0.PRTP */
+ }
+ Else
+ {
+ Return (PRTA) /* \_SB_.PCI0.PRTA */
+ }
+ }
+ }
+
+ Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PRQA, 8,
+ PRQB, 8,
+ PRQC, 8,
+ PRQD, 8,
+ Offset (0x08),
+ PRQE, 8,
+ PRQF, 8,
+ PRQG, 8,
+ PRQH, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ PRRI = (Arg0 & 0x0F)
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQA))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQA |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQA))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQB))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQB |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQB))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQC))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQC |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQC))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQD))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQD |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQD))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQE))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQE |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQE))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */
+ }
+ }
+
+ Device (LNKF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQF))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQF |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQF))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */
+ }
+ }
+
+ Device (LNKG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQG))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQG |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQG))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */
+ }
+ }
+
+ Device (LNKH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQH))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQH |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQH))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */
+ }
+ }
+
+ Device (GSIA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x11) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x12) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSID)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x13) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x16) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x17) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (SMB0)
+ {
+ Name (_ADR, 0x001F0003) // _ADR: Address
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0CD8, // Range Minimum
+ 0x0CD8, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Device (\_SB.PCI0.MHPD)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "Memory hotplug resources") // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0A00, // Range Minimum
+ 0x0A00, // Range Maximum
+ 0x00, // Alignment
+ 0x18, // Length
+ )
+ })
+ OperationRegion (HPMR, SystemIO, 0x0A00, 0x18)
+ }
+
+ Device (\_SB.MHPC)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "DIMM devices") // _UID: Unique ID
+ Name (MDNR, One)
+ Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MRBL, 32,
+ MRBH, 32,
+ MRLL, 32,
+ MRLH, 32,
+ MPX, 32
+ }
+
+ Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x14),
+ MES, 1,
+ MINS, 1,
+ MRMV, 1,
+ MEJ, 1
+ }
+
+ Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MSEL, 32,
+ MOEV, 32,
+ MOSC, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0B)
+ }
+
+ Mutex (MLCK, 0x00)
+ Method (MSCN, 0, NotSerialized)
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ While ((Local0 < MDNR))
+ {
+ MSEL = Local0
+ If ((MINS == One))
+ {
+ MTFY (Local0, One)
+ MINS = One
+ }
+ ElseIf ((MRMV == One))
+ {
+ MTFY (Local0, 0x03)
+ MRMV = One
+ }
+
+ Local0 += One
+ }
+
+ Release (MLCK)
+ Return (One)
+ }
+
+ Method (MRST, 1, NotSerialized)
+ {
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ If ((MES == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MCRS, 1, Serialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Name (MR64, ResourceTemplate ()
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Range Minimum
+ 0xFFFFFFFFFFFFFFFE, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0xFFFFFFFFFFFFFFFF, // Length
+ ,, _Y01, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address
+ CreateDWordField (MR64, 0x12, MINH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length
+ CreateDWordField (MR64, 0x2A, LENH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address
+ CreateDWordField (MR64, 0x1A, MAXH)
+ MINH = MRBH /* \_SB_.MHPC.MRBH */
+ MINL = MRBL /* \_SB_.MHPC.MRBL */
+ LENH = MRLH /* \_SB_.MHPC.MRLH */
+ LENL = MRLL /* \_SB_.MHPC.MRLL */
+ MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */
+ MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */
+ If ((MAXL < MINL))
+ {
+ MAXH += One
+ }
+
+ If ((MAXL < One))
+ {
+ MAXH -= One
+ }
+
+ MAXL -= One
+ If ((MAXH == Zero))
+ {
+ Name (MR32, ResourceTemplate ()
+ {
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0xFFFFFFFE, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xFFFFFFFF, // Length
+ ,, _Y02, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length
+ MIN = MINL /* \_SB_.MHPC.MCRS.MINL */
+ MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */
+ LEN = LENL /* \_SB_.MHPC.MCRS.LENL */
+ Release (MLCK)
+ Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */
+ }
+
+ Release (MLCK)
+ Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */
+ }
+
+ Method (MPXM, 1, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Local0 = MPX /* \_SB_.MHPC.MPX_ */
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MOST, 4, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MOEV = Arg1
+ MOSC = Arg2
+ Release (MLCK)
+ }
+
+ Method (MEJ0, 2, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MEJ = One
+ Release (MLCK)
+ }
+
+ Device (MP00)
+ {
+ Name (_UID, "0x00") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Method (MTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (MP00, Arg1)
+ }
+ }
+ }
+
+ Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.MHPC.MSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xAFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xA8000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xC0000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x3EC00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000200000000, // Range Minimum
+ 0x00000009FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000800000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0620, // Range Minimum
+ 0x0620, // Range Maximum
+ 0x01, // Alignment
+ 0x10, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S08)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Device (S10)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ }
+ }
+ }
+}
+
GIT binary patch
delta 33
ocmZp&{bj@D66_LECC9+PcxEG)mK>)WOH6#QQ@nuPWIH)q0Hvo16951J
delta 42
xcmexm(`3u#66_MvB*(zOn7ENkOODHrB_=-DDPF*hWwNcDExQO?fU{o+0|4^g3K{?a
new file mode 100644
@@ -0,0 +1,3138 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/q35/DSDT.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00001E04 (7684)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x55
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ Local0 &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != Local0))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = Local0
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ }
+
+ Return (Arg3)
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Name (PICF, Zero)
+ Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model
+ {
+ PICF = Arg0
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (PRTP, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
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+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSID,
+ Zero
+ }
+ })
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If ((PICF == Zero))
+ {
+ Return (PRTP) /* \_SB_.PCI0.PRTP */
+ }
+ Else
+ {
+ Return (PRTA) /* \_SB_.PCI0.PRTA */
+ }
+ }
+ }
+
+ Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PRQA, 8,
+ PRQB, 8,
+ PRQC, 8,
+ PRQD, 8,
+ Offset (0x08),
+ PRQE, 8,
+ PRQF, 8,
+ PRQG, 8,
+ PRQH, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ PRRI = (Arg0 & 0x0F)
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQA))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQA |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQA))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQB))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQB |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQB))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQC))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQC |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQC))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQD))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQD |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQD))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQE))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQE |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQE))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */
+ }
+ }
+
+ Device (LNKF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQF))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQF |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQF))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */
+ }
+ }
+
+ Device (LNKG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQG))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQG |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQG))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */
+ }
+ }
+
+ Device (LNKH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQH))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQH |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQH))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */
+ }
+ }
+
+ Device (GSIA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x11) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x12) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSID)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x13) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x16) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x17) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (SMB0)
+ {
+ Name (_ADR, 0x001F0003) // _ADR: Address
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0CD8, // Range Minimum
+ 0x0CD8, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+
+ Name (_PXM, Zero) // _PXM: Device Proximity
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xAFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xA8000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xC0000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x3EC00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000100000000, // Range Minimum
+ 0x00000008FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000800000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0620, // Range Minimum
+ 0x0620, // Range Maximum
+ 0x01, // Alignment
+ 0x10, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S08)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ }
+ }
+ }
+}
+
GIT binary patch
delta 38
ucmccVc*&8=CD<k8k^%z*<Cl$G26CJpnlbUgPVoW`lbz-4Hh0JcG64Ydc?+%p
delta 45
zcmccQc+-)~CD<k8rUC;4<AjY|26CMKnlbUgPVoZnlbz-4*hJU@oc%&JH^>Ds0RTDD
B46OhF
new file mode 100644
@@ -0,0 +1,3321 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/q35/DSDT.tis, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000205B (8283)
+ * Revision 0x01 **** 32-bit table (V1), no 64-bit math support
+ * Checksum 0x84
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\)
+ {
+ OperationRegion (DBG, SystemIO, 0x0402, One)
+ Field (DBG, ByteAcc, NoLock, Preserve)
+ {
+ DBGB, 8
+ }
+
+ Method (DBUG, 1, NotSerialized)
+ {
+ ToHexString (Arg0, Local0)
+ ToBuffer (Local0, Local0)
+ Local1 = (SizeOf (Local0) - One)
+ Local2 = Zero
+ While ((Local2 < Local1))
+ {
+ DBGB = DerefOf (Local0 [Local2])
+ Local2++
+ }
+
+ DBGB = 0x0A
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_UID, Zero) // _UID: Unique ID
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ Local0 &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != Local0))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = Local0
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ }
+
+ Return (Arg3)
+ }
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400)
+ Field (HPTM, DWordAcc, Lock, Preserve)
+ {
+ VEND, 32,
+ PRD, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Local0 = VEND /* \_SB_.HPET.VEND */
+ Local1 = PRD /* \_SB_.HPET.PRD_ */
+ Local0 >>= 0x10
+ If (((Local0 == Zero) || (Local0 == 0xFFFF)))
+ {
+ Return (Zero)
+ }
+
+ If (((Local1 == Zero) || (Local1 > 0x05F5E100)))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ )
+ })
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (ISA)
+ {
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C)
+ }
+ }
+
+ Scope (_SB.PCI0.ISA)
+ {
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0060, // Range Minimum
+ 0x0060, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0064, // Range Minimum
+ 0x0064, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {1}
+ })
+ }
+
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IRQNoFlags ()
+ {12}
+ })
+ }
+
+ Device (LPT1)
+ {
+ Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0378, // Range Minimum
+ 0x0378, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {7}
+ })
+ }
+
+ Device (COM1)
+ {
+ Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x00, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {4}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {8}
+ })
+ }
+ }
+
+ Name (PICF, Zero)
+ Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model
+ {
+ PICF = Arg0
+ }
+
+ Scope (_SB)
+ {
+ Scope (PCI0)
+ {
+ Name (PRTP, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ LNKG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ LNKD,
+ Zero
+ }
+ })
+ Name (PRTA, Package (0x80)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ GSID,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ GSIE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ GSIF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ GSIG,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ GSIH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ GSIA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ GSIB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ GSIC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSID,
+ Zero
+ }
+ })
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If ((PICF == Zero))
+ {
+ Return (PRTP) /* \_SB_.PCI0.PRTP */
+ }
+ Else
+ {
+ Return (PRTA) /* \_SB_.PCI0.PRTA */
+ }
+ }
+ }
+
+ Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PRQA, 8,
+ PRQB, 8,
+ PRQC, 8,
+ PRQD, 8,
+ Offset (0x08),
+ PRQE, 8,
+ PRQF, 8,
+ PRQG, 8,
+ PRQH, 8
+ }
+
+ Method (IQST, 1, NotSerialized)
+ {
+ If ((0x80 & Arg0))
+ {
+ Return (0x09)
+ }
+
+ Return (0x0B)
+ }
+
+ Method (IQCR, 1, Serialized)
+ {
+ Name (PRR0, ResourceTemplate ()
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00)
+ {
+ 0x00000000,
+ }
+ })
+ CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts
+ PRRI = (Arg0 & 0x0F)
+ Return (PRR0) /* \_SB_.IQCR.PRR0 */
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQA))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQA |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQA))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQB))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQB |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQB))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQC))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQC |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQC))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQD))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQD |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQD))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */
+ }
+ }
+
+ Device (LNKE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQE))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQE |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQE))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */
+ }
+ }
+
+ Device (LNKF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQF))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQF |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQF))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */
+ }
+ }
+
+ Device (LNKG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQG))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQG |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQG))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */
+ }
+ }
+
+ Device (LNKH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000005,
+ 0x0000000A,
+ 0x0000000B,
+ }
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (IQST (PRQH))
+ }
+
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ PRQH |= 0x80
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (IQCR (PRQH))
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ CreateDWordField (Arg0, 0x05, PRRI)
+ PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */
+ }
+ }
+
+ Device (GSIA)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000010,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIB)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x11) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000011,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIC)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x12) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000012,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSID)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x13) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000013,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIE)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000014,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIF)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000015,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIG)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x16) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000016,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSIH)
+ {
+ Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x17) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, )
+ {
+ 0x00000017,
+ }
+ })
+ Method (_DIS, 0, NotSerialized) // _DIS: Disable Device
+ {
+ }
+
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+ }
+
+ Scope (_SB.PCI0)
+ {
+ Device (SMB0)
+ {
+ Name (_ADR, 0x001F0003) // _ADR: Address
+ }
+ }
+
+ Scope (_SB)
+ {
+ Device (\_SB.PCI0.PRES)
+ {
+ Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "CPU Hotplug resources") // _UID: Unique ID
+ Mutex (CPLK, 0x00)
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0CD8, // Range Minimum
+ 0x0CD8, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C)
+ Field (PRST, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x04),
+ CPEN, 1,
+ CINS, 1,
+ CRMV, 1,
+ CEJ0, 1,
+ Offset (0x05),
+ CCMD, 8
+ }
+
+ Field (PRST, DWordAcc, NoLock, Preserve)
+ {
+ CSEL, 32,
+ Offset (0x08),
+ CDAT, 32
+ }
+
+ Method (_INI, 0, Serialized) // _INI: Initialize
+ {
+ CSEL = Zero
+ }
+ }
+
+ Device (\_SB.CPUS)
+ {
+ Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID
+ Method (CTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (C000, Arg1)
+ }
+ }
+
+ Method (CSTA, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ Local0 = Zero
+ If ((\_SB.PCI0.PRES.CPEN == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ Return (Local0)
+ }
+
+ Method (CEJ0, 1, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CEJ0 = One
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (CSCN, 0, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ Local0 = One
+ While ((Local0 == One))
+ {
+ Local0 = Zero
+ \_SB.PCI0.PRES.CCMD = Zero
+ If ((\_SB.PCI0.PRES.CINS == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, One)
+ \_SB.PCI0.PRES.CINS = One
+ Local0 = One
+ }
+ ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+ {
+ CTFY (\_SB.PCI0.PRES.CDAT, 0x03)
+ \_SB.PCI0.PRES.CRMV = One
+ Local0 = One
+ }
+ }
+
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Method (COST, 4, Serialized)
+ {
+ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
+ \_SB.PCI0.PRES.CSEL = Arg0
+ \_SB.PCI0.PRES.CCMD = One
+ \_SB.PCI0.PRES.CDAT = Arg1
+ \_SB.PCI0.PRES.CCMD = 0x02
+ \_SB.PCI0.PRES.CDAT = Arg2
+ Release (\_SB.PCI0.PRES.CPLK)
+ }
+
+ Processor (C000, 0x00, 0x00000000, 0x00)
+ {
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ Return (CSTA (Zero))
+ }
+
+ Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry
+ {
+ 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........
+ })
+ Method (_OST, 3, Serialized) // _OST: OSPM Status Indication
+ {
+ COST (Zero, Arg0, Arg1, Arg2)
+ }
+ }
+ }
+ }
+
+ Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF
+ {
+ \_SB.CPUS.CSCN ()
+ }
+
+ Scope (_GPE)
+ {
+ Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x0CF7, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0CF8, // Length
+ ,, , TypeStatic, DenseTranslation)
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Granularity
+ 0x0D00, // Range Minimum
+ 0xFFFF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0xF300, // Length
+ ,, , TypeStatic, DenseTranslation)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x08000000, // Range Minimum
+ 0xAFFFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xA8000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xC0000000, // Range Minimum
+ 0xFEBFFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x3EC00000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000100000000, // Range Minimum
+ 0x00000008FFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000800000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ Memory32Fixed (ReadWrite,
+ 0xFED40000, // Address Base
+ 0x00005000, // Address Length
+ )
+ })
+ Device (GPE0)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "GPE0 resources") // _UID: Unique ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0620, // Range Minimum
+ 0x0620, // Range Maximum
+ 0x01, // Alignment
+ 0x10, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\)
+ {
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ One,
+ One,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x02,
+ 0x02,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ }
+
+ Scope (\_SB.PCI0)
+ {
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0510, // Range Minimum
+ 0x0510, // Range Maximum
+ 0x01, // Alignment
+ 0x0C, // Length
+ )
+ })
+ }
+ }
+
+ Scope (\_SB)
+ {
+ Scope (PCI0)
+ {
+ Device (S00)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ }
+
+ Device (S08)
+ {
+ Name (_ADR, 0x00010000) // _ADR: Address
+ Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State
+ {
+ Return (Zero)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (Zero)
+ }
+ }
+
+ Method (PCNT, 0, NotSerialized)
+ {
+ }
+
+ Device (TPM)
+ {
+ Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */) // _HID: Hardware ID
+ Name (_STA, 0x0F) // _STA: Status
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0xFED40000, // Address Base
+ 0x00005000, // Address Length
+ )
+ })
+ OperationRegion (TPP2, SystemMemory, 0xFED45100, 0x5A)
+ Field (TPP2, AnyAcc, NoLock, Preserve)
+ {
+ PPIN, 8,
+ PPIP, 32,
+ PPRP, 32,
+ PPRQ, 32,
+ PPRM, 32,
+ LPPR, 32
+ }
+
+ OperationRegion (TPP3, SystemMemory, 0xFED4515A, One)
+ Field (TPP3, ByteAcc, NoLock, Preserve)
+ {
+ MOVV, 8
+ }
+
+ Method (TPFN, 1, Serialized)
+ {
+ If ((Arg0 >= 0x0100))
+ {
+ Return (Zero)
+ }
+
+ OperationRegion (TPP1, SystemMemory, (0xFED45000 + Arg0), One)
+ Field (TPP1, ByteAcc, NoLock, Preserve)
+ {
+ TPPF, 8
+ }
+
+ Return (TPPF) /* \_SB_.PCI0.TPM_.TPFN.TPPF */
+ }
+
+ Name (TPM2, Package (0x02)
+ {
+ Zero,
+ Zero
+ })
+ Name (TPM3, Package (0x03)
+ {
+ Zero,
+ Zero,
+ Zero
+ })
+ Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method
+ {
+ If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */))
+ {
+ If ((Arg2 == Zero))
+ {
+ Return (Buffer (0x02)
+ {
+ 0xFF, 0x01 // ..
+ })
+ }
+
+ If ((Arg2 == One))
+ {
+ Return ("1.3")
+ }
+
+ If ((Arg2 == 0x02))
+ {
+ Local0 = DerefOf (Arg3 [Zero])
+ Local1 = TPFN (Local0)
+ If (((Local1 & 0x07) == Zero))
+ {
+ Return (One)
+ }
+
+ PPRQ = Local0
+ PPRM = Zero
+ Return (Zero)
+ }
+
+ If ((Arg2 == 0x03))
+ {
+ If ((Arg1 == One))
+ {
+ TPM2 [One] = PPRQ /* \_SB_.PCI0.TPM_.PPRQ */
+ Return (TPM2) /* \_SB_.PCI0.TPM_.TPM2 */
+ }
+
+ If ((Arg1 == 0x02))
+ {
+ TPM3 [One] = PPRQ /* \_SB_.PCI0.TPM_.PPRQ */
+ TPM3 [0x02] = PPRM /* \_SB_.PCI0.TPM_.PPRM */
+ Return (TPM3) /* \_SB_.PCI0.TPM_.TPM3 */
+ }
+ }
+
+ If ((Arg2 == 0x04))
+ {
+ Return (0x02)
+ }
+
+ If ((Arg2 == 0x05))
+ {
+ TPM3 [One] = LPPR /* \_SB_.PCI0.TPM_.LPPR */
+ TPM3 [0x02] = PPRP /* \_SB_.PCI0.TPM_.PPRP */
+ Return (TPM3) /* \_SB_.PCI0.TPM_.TPM3 */
+ }
+
+ If ((Arg2 == 0x06))
+ {
+ Return (0x03)
+ }
+
+ If ((Arg2 == 0x07))
+ {
+ Local0 = DerefOf (Arg3 [Zero])
+ Local1 = TPFN (Local0)
+ If (((Local1 & 0x07) == Zero))
+ {
+ Return (One)
+ }
+
+ If (((Local1 & 0x07) == 0x02))
+ {
+ Return (0x03)
+ }
+
+ If ((Arg1 == One))
+ {
+ PPRQ = Local0
+ PPRM = Zero
+ }
+
+ If ((Arg1 == 0x02))
+ {
+ PPRQ = Local0
+ PPRM = DerefOf (Arg3 [One])
+ }
+
+ Return (Zero)
+ }
+
+ If ((Arg2 == 0x08))
+ {
+ Local0 = DerefOf (Arg3 [Zero])
+ Local1 = TPFN (Local0)
+ Return ((Local1 & 0x07))
+ }
+
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+
+ If ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d")))
+ {
+ If ((Arg2 == Zero))
+ {
+ Return (Buffer (One)
+ {
+ 0x03 // .
+ })
+ }
+
+ If ((Arg2 == One))
+ {
+ Local0 = DerefOf (Arg3 [Zero])
+ MOVV = Local0
+ Return (Zero)
+ }
+ }
+ }
+ }
+ }
+ }
+}
+
new file mode 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!hqOw2%n4I;_{r9nIn
zAX@<@&cwhX02KSr|DPYCl7Ybp$XMFKz`)4C!0?j?A_|v;DFV`r3P1wMTp$k&7=Z>N
X+XoXzrWq9=?f{7~HXz&s;==#{<X{c~
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,179 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACP.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 1F
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000084A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+Raw Table Data: Length 244 (0xF4)
+
+ 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ...............
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................
+ 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... ..........
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................
+ 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . ..............
+ 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ...............
+ 00F0: 00 00 00 00 // ....
new file mode 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!hqOw2%n4I;_{r9nIn
zAX@<@&cwhX02KSr|DPYCl7Ybp$XMFKz`)4C!0?j?A_|v;DFV`r3P1wMTp$k&7=Z>N
X+XoXzrWq9=?f{7~HXz&s;==#{<X{c~
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,179 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACP.bridge, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 1F
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000084A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+Raw Table Data: Length 244 (0xF4)
+
+ 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ...............
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................
+ 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... ..........
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................
+ 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . ..............
+ 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ...............
+ 00F0: 00 00 00 00 // ....
new file mode 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!hqOw2%n4I;_{r9nIn
zAX@<@&cwhX02KSr|DPYCl7Ybp$XMFKz`)4C!0?j?A_|v;DFV`r3P1wMTp$k&7=Z>N
X+XoXzrWq9=?f{7~HXz&s;==#{<X{c~
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,179 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACP.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 1F
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000084A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+Raw Table Data: Length 244 (0xF4)
+
+ 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ...............
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................
+ 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... ..........
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................
+ 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . ..............
+ 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ...............
+ 00F0: 00 00 00 00 // ....
new file mode 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!hqOw2%n4I;_{r9nIn
zAX@<@&cwhX02KSr|DPYCl7Ybp$XMFKz`)4C!0?j?A_|v;DFV`r3P1wMTp$k&7=Z>N
X+XoXzrWq9=?f{7~HXz&s;==#{<X{c~
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,179 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACP.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 1F
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000084A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+Raw Table Data: Length 244 (0xF4)
+
+ 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ...............
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................
+ 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... ..........
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................
+ 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . ..............
+ 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ...............
+ 00F0: 00 00 00 00 // ....
new file mode 100644
@@ -0,0 +1,179 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACP.tis, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 1F
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000084A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+Raw Table Data: Length 244 (0xF4)
+
+ 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ...............
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................
+ 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... ..........
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................
+ 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . ..............
+ 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ...............
+ 00F0: 00 00 00 00 // ....
new file mode 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!hqOw2%n4I;_{r9nIn
zAX@<@&cwhX02KSr|DPYCl7Ybp$XMFKz`)4C!0?j?A_|v;DFV`r3P1wMTp$k&7=Z>N
X+XoXzrWq9=?f{7~HXz&s;==#{<X{c~
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,179 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACP.ipmibt, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 1F
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000084A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+Raw Table Data: Length 244 (0xF4)
+
+ 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ...............
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................
+ 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... ..........
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................
+ 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . ..............
+ 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ...............
+ 00F0: 00 00 00 00 // ....
new file mode 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!hqOw2%n4I;_{r9nIn
zAX@<@&cwhX02KSr|DPYCl7Ybp$XMFKz`)4C!0?j?A_|v;DFV`r3P1wMTp$k&7=Z>N
X+XoXzrWq9=?f{7~HXz&s;==#{<X{c~
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,179 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACP.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 1F
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000084A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+Raw Table Data: Length 244 (0xF4)
+
+ 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ...............
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................
+ 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... ..........
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................
+ 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . ..............
+ 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ...............
+ 00F0: 00 00 00 00 // ....
new file mode 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!hqOw2%n4I;_{r9nIn
zAX@<@&cwhX02KSr|DPYCl7Ybp$XMFKz`)4C!0?j?A_|v;DFV`r3P1wMTp$k&7=Z>N
X+XoXzrWq9=?f{7~HXz&s;==#{<X{c~
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,179 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACP.mmio64, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 1F
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000084A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+Raw Table Data: Length 244 (0xF4)
+
+ 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ...............
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................
+ 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... ..........
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................
+ 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . ..............
+ 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ...............
+ 00F0: 00 00 00 00 // ....
new file mode 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!hqOw2%n4I;_{r9nIn
zAX@<@&cwhX02KSr|DPYCl7Ybp$XMFKz`)4C!0?j?A_|v;DFV`r3P1wMTp$k&7=Z>N
X+XoXzrWq9=?f{7~HXz&s;==#{<X{c~
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,179 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACP.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 1F
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000084A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+Raw Table Data: Length 244 (0xF4)
+
+ 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ...............
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................
+ 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... ..........
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................
+ 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . ..............
+ 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ...............
+ 00F0: 00 00 00 00 // ....
new file mode 100644
GIT binary patch
literal 244
zcmZ>BbPo8!z`(#P@8s|75v<@85#a0w6k`O6f!H7#1{fJQ88!hqOw2%n4I;_{r9nIn
zAX@<@&cwhX02KSr|DPYCl7Ybp$XMFKz`)4C!0?j?A_|v;DFV`r3P1wMTp$k&7=Z>N
X+XoXzrWq9=?f{7~HXz&s;==#{<X{c~
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,179 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACP.tis, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 1F
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : 02
+[035h 0053 1] ACPI Disable Value : 03
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000600
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000604
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000608
+[050h 0080 4] GPE0 Block Address : 00000620
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0FFF
+[062h 0098 2] C3 Latency : 0FFF
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 32
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 000084A5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 0F
+[081h 0129 2] ARM Flags (decoded below) : 0000
+ PSCI Compliant : 0
+ Must use HVC for PSCI : 0
+
+[083h 0131 1] FADT Minor Revision : 00
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000600
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000604
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000608
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000620
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+Raw Table Data: Length 244 (0xF4)
+
+ 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................
+ 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................
+ 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................
+ 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ...............
+ 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2...
+ 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................
+ 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... ..........
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................
+ 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . ..............
+ 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ...............
+ 00F0: 00 00 00 00 // ....
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACS.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACS.bridge, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACS.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACS.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACS.tis, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACS.ipmibt, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACS.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACS.mmio64, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACS.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
GIT binary patch
literal 64
PcmZ>BbPjf4ARhn#RKNjV
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/FACS.tis, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 00
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,132 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/HMAT.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HMAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table]
+[004h 0004 4] Table Length : 00000118
+[008h 0008 1] Revision : 02
+[009h 0009 1] Checksum : 98
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHMAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Reserved : 00000000
+
+[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
+[02Ah 0042 2] Reserved : 0000
+[02Ch 0044 4] Length : 00000028
+[030h 0048 2] Flags (decoded below) : 0001
+ Processor Proximity Domain Valid : 1
+[032h 0050 2] Reserved1 : 0000
+[034h 0052 4] Processor Proximity Domain : 00000000
+[038h 0056 4] Memory Proximity Domain : 00000000
+[03Ch 0060 4] Reserved2 : 00000000
+[040h 0064 8] Reserved3 : 0000000000000000
+[048h 0072 8] Reserved4 : 0000000000000000
+
+[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
+[052h 0082 2] Reserved : 0000
+[054h 0084 4] Length : 00000028
+[058h 0088 2] Flags (decoded below) : 0001
+ Processor Proximity Domain Valid : 1
+[05Ah 0090 2] Reserved1 : 0000
+[05Ch 0092 4] Processor Proximity Domain : 00000000
+[060h 0096 4] Memory Proximity Domain : 00000001
+[064h 0100 4] Reserved2 : 00000000
+[068h 0104 8] Reserved3 : 0000000000000000
+[070h 0112 8] Reserved4 : 0000000000000000
+
+[078h 0120 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
+[07Ah 0122 2] Reserved : 0000
+[07Ch 0124 4] Length : 00000030
+[080h 0128 1] Flags (decoded below) : 00
+ Memory Hierarchy : 0
+[081h 0129 1] Data Type : 00
+[082h 0130 2] Reserved1 : 0000
+[084h 0132 4] Initiator Proximity Domains # : 00000001
+[088h 0136 4] Target Proximity Domains # : 00000002
+[08Ch 0140 4] Reserved2 : 00000000
+[090h 0144 8] Entry Base Unit : 00000000000003E8
+[098h 0152 4] Initiator Proximity Domain List : 00000000
+[09Ch 0156 4] Target Proximity Domain List : 00000000
+[0A0h 0160 4] Target Proximity Domain List : 00000001
+[0A4h 0164 2] Entry : 0001
+[0A6h 0166 2] Entry : FFFE
+
+[0A8h 0168 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
+[0AAh 0170 2] Reserved : 0000
+[0ACh 0172 4] Length : 00000030
+[0B0h 0176 1] Flags (decoded below) : 00
+ Memory Hierarchy : 0
+[0B1h 0177 1] Data Type : 03
+[0B2h 0178 2] Reserved1 : 0000
+[0B4h 0180 4] Initiator Proximity Domains # : 00000001
+[0B8h 0184 4] Target Proximity Domains # : 00000002
+[0BCh 0188 4] Reserved2 : 00000000
+[0C0h 0192 8] Entry Base Unit : 0000000000000001
+[0C8h 0200 4] Initiator Proximity Domain List : 00000000
+[0CCh 0204 4] Target Proximity Domain List : 00000000
+[0D0h 0208 4] Target Proximity Domain List : 00000001
+[0D4h 0212 2] Entry : FFFE
+[0D6h 0214 2] Entry : 7FFF
+
+[0D8h 0216 2] Structure Type : 0002 [Memory Side Cache Information]
+[0DAh 0218 2] Reserved : 0000
+[0DCh 0220 4] Length : 00000020
+[0E0h 0224 4] Memory Proximity Domain : 00000000
+[0E4h 0228 4] Reserved1 : 00000000
+[0E8h 0232 8] Memory Side Cache Size : 0000000000002800
+[0F0h 0240 4] Cache Attributes (decoded below) : 00081111
+ Total Cache Levels : 1
+ Cache Level : 1
+ Cache Associativity : 1
+ Write Policy : 1
+ Cache Line Size : 0008
+[0F4h 0244 2] Reserved2 : 0000
+[0F6h 0246 2] SMBIOS Handle # : 0000
+
+[0F8h 0248 2] Structure Type : 0002 [Memory Side Cache Information]
+[0FAh 0250 2] Reserved : 0000
+[0FCh 0252 4] Length : 00000020
+[100h 0256 4] Memory Proximity Domain : 00000001
+[104h 0260 4] Reserved1 : 00000000
+[108h 0264 8] Memory Side Cache Size : 0000000000002800
+[110h 0272 4] Cache Attributes (decoded below) : 00081111
+ Total Cache Levels : 1
+ Cache Level : 1
+ Cache Associativity : 1
+ Write Policy : 1
+ Cache Line Size : 0008
+[114h 0276 2] Reserved2 : 0000
+[116h 0278 2] SMBIOS Handle # : 0000
+
+Raw Table Data: Length 280 (0x118)
+
+ 0000: 48 4D 41 54 18 01 00 00 02 98 42 4F 43 48 53 20 // HMAT......BOCHS
+ 0010: 42 58 50 43 48 4D 41 54 01 00 00 00 42 58 50 43 // BXPCHMAT....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
+ 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 28 00 00 00 01 00 00 00 00 00 00 00 // ....(...........
+ 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0070: 00 00 00 00 00 00 00 00 01 00 00 00 30 00 00 00 // ............0...
+ 0080: 00 00 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................
+ 0090: E8 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00A0: 01 00 00 00 01 00 FE FF 01 00 00 00 30 00 00 00 // ............0...
+ 00B0: 00 03 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................
+ 00C0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 01 00 00 00 FE FF FF 7F 02 00 00 00 20 00 00 00 // ............ ...
+ 00E0: 00 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(......
+ 00F0: 11 11 08 00 00 00 00 00 02 00 00 00 20 00 00 00 // ............ ...
+ 0100: 01 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(......
+ 0110: 11 11 08 00 00 00 00 00 // ........
new file mode 100644
@@ -0,0 +1,132 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/HMAT.acpihmat, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [HMAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table]
+[004h 0004 4] Table Length : 00000118
+[008h 0008 1] Revision : 02
+[009h 0009 1] Checksum : 98
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHMAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Reserved : 00000000
+
+[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
+[02Ah 0042 2] Reserved : 0000
+[02Ch 0044 4] Length : 00000028
+[030h 0048 2] Flags (decoded below) : 0001
+ Processor Proximity Domain Valid : 1
+[032h 0050 2] Reserved1 : 0000
+[034h 0052 4] Processor Proximity Domain : 00000000
+[038h 0056 4] Memory Proximity Domain : 00000000
+[03Ch 0060 4] Reserved2 : 00000000
+[040h 0064 8] Reserved3 : 0000000000000000
+[048h 0072 8] Reserved4 : 0000000000000000
+
+[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes]
+[052h 0082 2] Reserved : 0000
+[054h 0084 4] Length : 00000028
+[058h 0088 2] Flags (decoded below) : 0001
+ Processor Proximity Domain Valid : 1
+[05Ah 0090 2] Reserved1 : 0000
+[05Ch 0092 4] Processor Proximity Domain : 00000000
+[060h 0096 4] Memory Proximity Domain : 00000001
+[064h 0100 4] Reserved2 : 00000000
+[068h 0104 8] Reserved3 : 0000000000000000
+[070h 0112 8] Reserved4 : 0000000000000000
+
+[078h 0120 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
+[07Ah 0122 2] Reserved : 0000
+[07Ch 0124 4] Length : 00000030
+[080h 0128 1] Flags (decoded below) : 00
+ Memory Hierarchy : 0
+[081h 0129 1] Data Type : 00
+[082h 0130 2] Reserved1 : 0000
+[084h 0132 4] Initiator Proximity Domains # : 00000001
+[088h 0136 4] Target Proximity Domains # : 00000002
+[08Ch 0140 4] Reserved2 : 00000000
+[090h 0144 8] Entry Base Unit : 00000000000003E8
+[098h 0152 4] Initiator Proximity Domain List : 00000000
+[09Ch 0156 4] Target Proximity Domain List : 00000000
+[0A0h 0160 4] Target Proximity Domain List : 00000001
+[0A4h 0164 2] Entry : 0001
+[0A6h 0166 2] Entry : FFFE
+
+[0A8h 0168 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information]
+[0AAh 0170 2] Reserved : 0000
+[0ACh 0172 4] Length : 00000030
+[0B0h 0176 1] Flags (decoded below) : 00
+ Memory Hierarchy : 0
+[0B1h 0177 1] Data Type : 03
+[0B2h 0178 2] Reserved1 : 0000
+[0B4h 0180 4] Initiator Proximity Domains # : 00000001
+[0B8h 0184 4] Target Proximity Domains # : 00000002
+[0BCh 0188 4] Reserved2 : 00000000
+[0C0h 0192 8] Entry Base Unit : 0000000000000001
+[0C8h 0200 4] Initiator Proximity Domain List : 00000000
+[0CCh 0204 4] Target Proximity Domain List : 00000000
+[0D0h 0208 4] Target Proximity Domain List : 00000001
+[0D4h 0212 2] Entry : FFFE
+[0D6h 0214 2] Entry : 7FFF
+
+[0D8h 0216 2] Structure Type : 0002 [Memory Side Cache Information]
+[0DAh 0218 2] Reserved : 0000
+[0DCh 0220 4] Length : 00000020
+[0E0h 0224 4] Memory Proximity Domain : 00000000
+[0E4h 0228 4] Reserved1 : 00000000
+[0E8h 0232 8] Memory Side Cache Size : 0000000000002800
+[0F0h 0240 4] Cache Attributes (decoded below) : 00081111
+ Total Cache Levels : 1
+ Cache Level : 1
+ Cache Associativity : 1
+ Write Policy : 1
+ Cache Line Size : 0008
+[0F4h 0244 2] Reserved2 : 0000
+[0F6h 0246 2] SMBIOS Handle # : 0000
+
+[0F8h 0248 2] Structure Type : 0002 [Memory Side Cache Information]
+[0FAh 0250 2] Reserved : 0000
+[0FCh 0252 4] Length : 00000020
+[100h 0256 4] Memory Proximity Domain : 00000001
+[104h 0260 4] Reserved1 : 00000000
+[108h 0264 8] Memory Side Cache Size : 0000000000002800
+[110h 0272 4] Cache Attributes (decoded below) : 00081111
+ Total Cache Levels : 1
+ Cache Level : 1
+ Cache Associativity : 1
+ Write Policy : 1
+ Cache Line Size : 0008
+[114h 0276 2] Reserved2 : 0000
+[116h 0278 2] SMBIOS Handle # : 0000
+
+Raw Table Data: Length 280 (0x118)
+
+ 0000: 48 4D 41 54 18 01 00 00 02 98 42 4F 43 48 53 20 // HMAT......BOCHS
+ 0010: 42 58 50 43 48 4D 41 54 01 00 00 00 42 58 50 43 // BXPCHMAT....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(...
+ 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 28 00 00 00 01 00 00 00 00 00 00 00 // ....(...........
+ 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0070: 00 00 00 00 00 00 00 00 01 00 00 00 30 00 00 00 // ............0...
+ 0080: 00 00 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................
+ 0090: E8 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00A0: 01 00 00 00 01 00 FE FF 01 00 00 00 30 00 00 00 // ............0...
+ 00B0: 00 03 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................
+ 00C0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 01 00 00 00 FE FF FF 7F 02 00 00 00 20 00 00 00 // ............ ...
+ 00E0: 00 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(......
+ 00F0: 11 11 08 00 00 00 00 00 02 00 00 00 20 00 00 00 // ............ ...
+ 0100: 01 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(......
+ 0110: 11 11 08 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/HPET.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/HPET.bridge, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/HPET.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/HPET.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/HPET.tis, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/HPET.ipmibt, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/HPET.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/HPET.mmio64, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/HPET.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 56
xcmeYWa1F6wU|?WmcJg=j2v%^42ypfQiZKGkKx`1rxTviGNCClxe-N610RT2D3IPBB
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/HPET.tis, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 03
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCHPET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Hardware Block ID : 8086A201
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 00
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0000
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS
+ 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC
+ 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................
+ 0030: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 60
rcmeZuc5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cC}|AS}%SE304
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,36 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/MCFG.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [MCFG]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table]
+[004h 0004 4] Table Length : 0000003C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : EF
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCMCFG"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Reserved : 0000000000000000
+
+[02Ch 0044 8] Base Address : 00000000B0000000
+[034h 0052 2] Segment Group Number : 0000
+[036h 0054 1] Start Bus Number : 00
+[037h 0055 1] End Bus Number : FF
+[038h 0056 4] Reserved : 00000000
+
+Raw Table Data: Length 60 (0x3C)
+
+ 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS
+ 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................
+ 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............
new file mode 100644
GIT binary patch
literal 60
rcmeZuc5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cC}|AS}%SE304
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,36 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/MCFG.bridge, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [MCFG]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table]
+[004h 0004 4] Table Length : 0000003C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : EF
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCMCFG"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Reserved : 0000000000000000
+
+[02Ch 0044 8] Base Address : 00000000B0000000
+[034h 0052 2] Segment Group Number : 0000
+[036h 0054 1] Start Bus Number : 00
+[037h 0055 1] End Bus Number : FF
+[038h 0056 4] Reserved : 00000000
+
+Raw Table Data: Length 60 (0x3C)
+
+ 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS
+ 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................
+ 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............
new file mode 100644
GIT binary patch
literal 60
rcmeZuc5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cC}|AS}%SE304
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,36 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/MCFG.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [MCFG]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table]
+[004h 0004 4] Table Length : 0000003C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : EF
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCMCFG"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Reserved : 0000000000000000
+
+[02Ch 0044 8] Base Address : 00000000B0000000
+[034h 0052 2] Segment Group Number : 0000
+[036h 0054 1] Start Bus Number : 00
+[037h 0055 1] End Bus Number : FF
+[038h 0056 4] Reserved : 00000000
+
+Raw Table Data: Length 60 (0x3C)
+
+ 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS
+ 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................
+ 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............
new file mode 100644
GIT binary patch
literal 60
rcmeZuc5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cC}|AS}%SE304
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,36 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/MCFG.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [MCFG]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table]
+[004h 0004 4] Table Length : 0000003C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : EF
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCMCFG"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Reserved : 0000000000000000
+
+[02Ch 0044 8] Base Address : 00000000B0000000
+[034h 0052 2] Segment Group Number : 0000
+[036h 0054 1] Start Bus Number : 00
+[037h 0055 1] End Bus Number : FF
+[038h 0056 4] Reserved : 00000000
+
+Raw Table Data: Length 60 (0x3C)
+
+ 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS
+ 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................
+ 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............
new file mode 100644
@@ -0,0 +1,36 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/MCFG.tis, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [MCFG]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table]
+[004h 0004 4] Table Length : 0000003C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : EF
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCMCFG"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Reserved : 0000000000000000
+
+[02Ch 0044 8] Base Address : 00000000B0000000
+[034h 0052 2] Segment Group Number : 0000
+[036h 0054 1] Start Bus Number : 00
+[037h 0055 1] End Bus Number : FF
+[038h 0056 4] Reserved : 00000000
+
+Raw Table Data: Length 60 (0x3C)
+
+ 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS
+ 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................
+ 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............
new file mode 100644
GIT binary patch
literal 60
rcmeZuc5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cC}|AS}%SE304
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,36 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/MCFG.ipmibt, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [MCFG]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table]
+[004h 0004 4] Table Length : 0000003C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : EF
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCMCFG"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Reserved : 0000000000000000
+
+[02Ch 0044 8] Base Address : 00000000B0000000
+[034h 0052 2] Segment Group Number : 0000
+[036h 0054 1] Start Bus Number : 00
+[037h 0055 1] End Bus Number : FF
+[038h 0056 4] Reserved : 00000000
+
+Raw Table Data: Length 60 (0x3C)
+
+ 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS
+ 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................
+ 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............
new file mode 100644
GIT binary patch
literal 60
rcmeZuc5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cC}|AS}%SE304
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,36 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/MCFG.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [MCFG]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table]
+[004h 0004 4] Table Length : 0000003C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : EF
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCMCFG"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Reserved : 0000000000000000
+
+[02Ch 0044 8] Base Address : 00000000B0000000
+[034h 0052 2] Segment Group Number : 0000
+[036h 0054 1] Start Bus Number : 00
+[037h 0055 1] End Bus Number : FF
+[038h 0056 4] Reserved : 00000000
+
+Raw Table Data: Length 60 (0x3C)
+
+ 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS
+ 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................
+ 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............
new file mode 100644
GIT binary patch
literal 60
rcmeZuc5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cC}|AS}%SE304
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,36 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/MCFG.mmio64, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [MCFG]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table]
+[004h 0004 4] Table Length : 0000003C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : EF
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCMCFG"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Reserved : 0000000000000000
+
+[02Ch 0044 8] Base Address : 00000000B0000000
+[034h 0052 2] Segment Group Number : 0000
+[036h 0054 1] Start Bus Number : 00
+[037h 0055 1] End Bus Number : FF
+[038h 0056 4] Reserved : 00000000
+
+Raw Table Data: Length 60 (0x3C)
+
+ 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS
+ 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................
+ 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............
new file mode 100644
GIT binary patch
literal 60
rcmeZuc5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cC}|AS}%SE304
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,36 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/MCFG.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [MCFG]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table]
+[004h 0004 4] Table Length : 0000003C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : EF
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCMCFG"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Reserved : 0000000000000000
+
+[02Ch 0044 8] Base Address : 00000000B0000000
+[034h 0052 2] Segment Group Number : 0000
+[036h 0054 1] Start Bus Number : 00
+[037h 0055 1] End Bus Number : FF
+[038h 0056 4] Reserved : 00000000
+
+Raw Table Data: Length 60 (0x3C)
+
+ 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS
+ 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................
+ 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............
new file mode 100644
GIT binary patch
literal 60
rcmeZuc5}C3U|?W;@8s|75v<@85#a0#6k`O6f!H7#32cC}|AS}%SE304
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,36 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/MCFG.tis, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [MCFG]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table]
+[004h 0004 4] Table Length : 0000003C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : EF
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCMCFG"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Reserved : 0000000000000000
+
+[02Ch 0044 8] Base Address : 00000000B0000000
+[034h 0052 2] Segment Group Number : 0000
+[036h 0054 1] Start Bus Number : 00
+[037h 0055 1] End Bus Number : FF
+[038h 0056 4] Reserved : 00000000
+
+Raw Table Data: Length 60 (0x3C)
+
+ 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS
+ 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................
+ 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............
new file mode 100644
@@ -0,0 +1,115 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/NFIT.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [NFIT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table]
+[004h 0004 4] Table Length : 000000F0
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 24
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCNFIT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Reserved : 00000000
+
+[028h 0040 2] Subtable Type : 0000 [System Physical Address Range]
+[02Ah 0042 2] Length : 0038
+
+[02Ch 0044 2] Range Index : 0004
+[02Eh 0046 2] Flags (decoded below) : 0003
+ Add/Online Operation Only : 1
+ Proximity Domain Valid : 1
+[030h 0048 4] Reserved : 00000000
+[034h 0052 4] Proximity Domain : 00000002
+[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB
+[048h 0072 8] Address Range Base : 0000000108000000
+[050h 0080 8] Address Range Length : 0000000008000000
+[058h 0088 8] Memory Map Attribute : 0000000000008008
+
+[060h 0096 2] Subtable Type : 0001 [Memory Range Map]
+[062h 0098 2] Length : 0030
+
+[064h 0100 4] Device Handle : 00000002
+[068h 0104 2] Physical Id : 0000
+[06Ah 0106 2] Region Id : 0000
+[06Ch 0108 2] Range Index : 0004
+[06Eh 0110 2] Control Region Index : 0005
+[070h 0112 8] Region Size : 0000000008000000
+[078h 0120 8] Region Offset : 0000000000000000
+[080h 0128 8] Address Region Base : 0000000000000000
+[088h 0136 2] Interleave Index : 0000
+[08Ah 0138 2] Interleave Ways : 0001
+[08Ch 0140 2] Flags : 0000
+ Save to device failed : 0
+ Restore from device failed : 0
+ Platform flush failed : 0
+ Device not armed : 0
+ Health events observed : 0
+ Health events enabled : 0
+ Mapping failed : 0
+[08Eh 0142 2] Reserved : 0000
+
+[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region]
+[092h 0146 2] Length : 0050
+
+[094h 0148 2] Region Index : 0005
+[096h 0150 2] Vendor Id : 8086
+[098h 0152 2] Device Id : 0001
+[09Ah 0154 2] Revision Id : 0001
+[09Ch 0156 2] Subsystem Vendor Id : 0000
+[09Eh 0158 2] Subsystem Device Id : 0000
+[0A0h 0160 2] Subsystem Revision Id : 0000
+[0A2h 0162 1] Valid Fields : 00
+[0A3h 0163 1] Manufacturing Location : 00
+[0A4h 0164 2] Manufacturing Date : 0000
+[0A6h 0166 2] Reserved : 0000
+[0A8h 0168 4] Serial Number : 00123457
+[0ACh 0172 2] Code : 0301
+[0AEh 0174 2] Window Count : 0000
+[0B0h 0176 8] Window Size : 0000000000000000
+[0B8h 0184 8] Command Offset : 0000000000000000
+[0C0h 0192 8] Command Size : 0000000000000000
+[0C8h 0200 8] Status Offset : 0000000000000000
+[0D0h 0208 8] Status Size : 0000000000000000
+[0D8h 0216 2] Flags : 0000
+ Windows buffered : 0
+[0DAh 0218 6] Reserved1 : 000000000000
+
+[0E0h 0224 2] Subtable Type : 0007 [Platform Capabilities]
+[0E2h 0226 2] Length : 0010
+
+[0E4h 0228 1] Highest Capability : 01
+[0E5h 0229 3] Reserved : 000000
+[0E8h 0232 4] Capabilities (decoded below) : 00000003
+ Cache Flush to NVDIMM : 1
+ Memory Flush to NVDIMM : 1
+ Memory Mirroring : 0
+[0ECh 0236 4] Reserved : 00000000
+
+Raw Table Data: Length 240 (0xF0)
+
+ 0000: 4E 46 49 54 F0 00 00 00 01 24 42 4F 43 48 53 20 // NFIT.....$BOCHS
+ 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8.....
+ 0030: 00 00 00 00 02 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@
+ 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 08 01 00 00 00 // .C.3............
+ 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................
+ 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0.............
+ 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................
+ 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P.............
+ 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4......
+ 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 07 00 10 00 01 00 00 00 03 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,115 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/NFIT.dimmpxm, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [NFIT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table]
+[004h 0004 4] Table Length : 000000F0
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 24
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCNFIT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Reserved : 00000000
+
+[028h 0040 2] Subtable Type : 0000 [System Physical Address Range]
+[02Ah 0042 2] Length : 0038
+
+[02Ch 0044 2] Range Index : 0004
+[02Eh 0046 2] Flags (decoded below) : 0003
+ Add/Online Operation Only : 1
+ Proximity Domain Valid : 1
+[030h 0048 4] Reserved : 00000000
+[034h 0052 4] Proximity Domain : 00000002
+[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB
+[048h 0072 8] Address Range Base : 0000000108000000
+[050h 0080 8] Address Range Length : 0000000008000000
+[058h 0088 8] Memory Map Attribute : 0000000000008008
+
+[060h 0096 2] Subtable Type : 0001 [Memory Range Map]
+[062h 0098 2] Length : 0030
+
+[064h 0100 4] Device Handle : 00000002
+[068h 0104 2] Physical Id : 0000
+[06Ah 0106 2] Region Id : 0000
+[06Ch 0108 2] Range Index : 0004
+[06Eh 0110 2] Control Region Index : 0005
+[070h 0112 8] Region Size : 0000000008000000
+[078h 0120 8] Region Offset : 0000000000000000
+[080h 0128 8] Address Region Base : 0000000000000000
+[088h 0136 2] Interleave Index : 0000
+[08Ah 0138 2] Interleave Ways : 0001
+[08Ch 0140 2] Flags : 0000
+ Save to device failed : 0
+ Restore from device failed : 0
+ Platform flush failed : 0
+ Device not armed : 0
+ Health events observed : 0
+ Health events enabled : 0
+ Mapping failed : 0
+[08Eh 0142 2] Reserved : 0000
+
+[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region]
+[092h 0146 2] Length : 0050
+
+[094h 0148 2] Region Index : 0005
+[096h 0150 2] Vendor Id : 8086
+[098h 0152 2] Device Id : 0001
+[09Ah 0154 2] Revision Id : 0001
+[09Ch 0156 2] Subsystem Vendor Id : 0000
+[09Eh 0158 2] Subsystem Device Id : 0000
+[0A0h 0160 2] Subsystem Revision Id : 0000
+[0A2h 0162 1] Valid Fields : 00
+[0A3h 0163 1] Manufacturing Location : 00
+[0A4h 0164 2] Manufacturing Date : 0000
+[0A6h 0166 2] Reserved : 0000
+[0A8h 0168 4] Serial Number : 00123457
+[0ACh 0172 2] Code : 0301
+[0AEh 0174 2] Window Count : 0000
+[0B0h 0176 8] Window Size : 0000000000000000
+[0B8h 0184 8] Command Offset : 0000000000000000
+[0C0h 0192 8] Command Size : 0000000000000000
+[0C8h 0200 8] Status Offset : 0000000000000000
+[0D0h 0208 8] Status Size : 0000000000000000
+[0D8h 0216 2] Flags : 0000
+ Windows buffered : 0
+[0DAh 0218 6] Reserved1 : 000000000000
+
+[0E0h 0224 2] Subtable Type : 0007 [Platform Capabilities]
+[0E2h 0226 2] Length : 0010
+
+[0E4h 0228 1] Highest Capability : 01
+[0E5h 0229 3] Reserved : 000000
+[0E8h 0232 4] Capabilities (decoded below) : 00000003
+ Cache Flush to NVDIMM : 1
+ Memory Flush to NVDIMM : 1
+ Memory Mirroring : 0
+[0ECh 0236 4] Reserved : 00000000
+
+Raw Table Data: Length 240 (0xF0)
+
+ 0000: 4E 46 49 54 F0 00 00 00 01 24 42 4F 43 48 53 20 // NFIT.....$BOCHS
+ 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8.....
+ 0030: 00 00 00 00 02 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@
+ 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 08 01 00 00 00 // .C.3............
+ 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................
+ 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0.............
+ 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................
+ 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P.............
+ 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4......
+ 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 07 00 10 00 01 00 00 00 03 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/SLIT.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SLIT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SLIT" [System Locality Information Table]
+[004h 0004 4] Table Length : 00000030
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 2C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSLIT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Localities : 0000000000000002
+[02Ch 0044 2] Locality 0 : 0A 15
+[02Eh 0046 2] Locality 1 : 15 0A
+
+Raw Table Data: Length 48 (0x30)
+
+ 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS
+ 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC
+ 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/SLIT.memhp, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [SLIT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SLIT" [System Locality Information Table]
+[004h 0004 4] Table Length : 00000030
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 2C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSLIT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Localities : 0000000000000002
+[02Ch 0044 2] Locality 0 : 0A 15
+[02Eh 0046 2] Locality 1 : 15 0A
+
+Raw Table Data: Length 48 (0x30)
+
+ 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS
+ 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC
+ 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/SLIT.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SLIT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SLIT" [System Locality Information Table]
+[004h 0004 4] Table Length : 00000030
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 2C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSLIT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Localities : 0000000000000002
+[02Ch 0044 2] Locality 0 : 0A 15
+[02Eh 0046 2] Locality 1 : 15 0A
+
+Raw Table Data: Length 48 (0x30)
+
+ 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS
+ 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC
+ 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................
new file mode 100644
@@ -0,0 +1,137 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/SRAT.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 00000118
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : C0
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[031h 0049 1] Length : 10
+
+[032h 0050 1] Proximity Domain Low(8) : 00
+[033h 0051 1] Apic ID : 00
+[034h 0052 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[038h 0056 1] Local Sapic EID : 00
+[039h 0057 3] Proximity Domain High(24) : 000000
+[03Ch 0060 4] Clock Domain : 00000000
+
+[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[041h 0065 1] Length : 10
+
+[042h 0066 1] Proximity Domain Low(8) : 00
+[043h 0067 1] Apic ID : 01
+[044h 0068 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[048h 0072 1] Local Sapic EID : 00
+[049h 0073 3] Proximity Domain High(24) : 000000
+[04Ch 0076 4] Clock Domain : 00000000
+
+[050h 0080 1] Subtable Type : 01 [Memory Affinity]
+[051h 0081 1] Length : 28
+
+[052h 0082 4] Proximity Domain : 00000000
+[056h 0086 2] Reserved1 : 0000
+[058h 0088 8] Base Address : 0000000000000000
+[060h 0096 8] Address Length : 00000000000A0000
+[068h 0104 4] Reserved2 : 00000000
+[06Ch 0108 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[070h 0112 8] Reserved3 : 0000000000000000
+
+[078h 0120 1] Subtable Type : 01 [Memory Affinity]
+[079h 0121 1] Length : 28
+
+[07Ah 0122 4] Proximity Domain : 00000000
+[07Eh 0126 2] Reserved1 : 0000
+[080h 0128 8] Base Address : 0000000000100000
+[088h 0136 8] Address Length : 0000000003F00000
+[090h 0144 4] Reserved2 : 00000000
+[094h 0148 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[098h 0152 8] Reserved3 : 0000000000000000
+
+[0A0h 0160 1] Subtable Type : 01 [Memory Affinity]
+[0A1h 0161 1] Length : 28
+
+[0A2h 0162 4] Proximity Domain : 00000001
+[0A6h 0166 2] Reserved1 : 0000
+[0A8h 0168 8] Base Address : 0000000004000000
+[0B0h 0176 8] Address Length : 0000000004000000
+[0B8h 0184 4] Reserved2 : 00000000
+[0BCh 0188 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0C0h 0192 8] Reserved3 : 0000000000000000
+
+[0C8h 0200 1] Subtable Type : 01 [Memory Affinity]
+[0C9h 0201 1] Length : 28
+
+[0CAh 0202 4] Proximity Domain : 00000000
+[0CEh 0206 2] Reserved1 : 0000
+[0D0h 0208 8] Base Address : 0000000000000000
+[0D8h 0216 8] Address Length : 0000000000000000
+[0E0h 0224 4] Reserved2 : 00000000
+[0E4h 0228 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0E8h 0232 8] Reserved3 : 0000000000000000
+
+[0F0h 0240 1] Subtable Type : 01 [Memory Affinity]
+[0F1h 0241 1] Length : 28
+
+[0F2h 0242 4] Proximity Domain : 00000001
+[0F6h 0246 2] Reserved1 : 0000
+[0F8h 0248 8] Base Address : 0000000100000000
+[100h 0256 8] Address Length : 00000000B8000000
+[108h 0264 4] Reserved2 : 00000000
+[10Ch 0268 4] Flags (decoded below) : 00000003
+ Enabled : 1
+ Hot Pluggable : 1
+ Non-Volatile : 0
+[110h 0272 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 280 (0x118)
+
+ 0000: 53 52 41 54 18 01 00 00 01 C0 42 4F 43 48 53 20 // SRAT......BOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 10 00 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 0060: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0070: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 0080: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................
+ 0090: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00A0: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(..............
+ 00B0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00F0: 01 28 01 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(..............
+ 0100: 00 00 00 B8 00 00 00 00 00 00 00 00 03 00 00 00 // ................
+ 0110: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
@@ -0,0 +1,168 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/SRAT.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 00000130
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 36
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[031h 0049 1] Length : 10
+
+[032h 0050 1] Proximity Domain Low(8) : 00
+[033h 0051 1] Apic ID : 00
+[034h 0052 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[038h 0056 1] Local Sapic EID : 00
+[039h 0057 3] Proximity Domain High(24) : 000000
+[03Ch 0060 4] Clock Domain : 00000000
+
+[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[041h 0065 1] Length : 10
+
+[042h 0066 1] Proximity Domain Low(8) : 00
+[043h 0067 1] Apic ID : 01
+[044h 0068 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[048h 0072 1] Local Sapic EID : 00
+[049h 0073 3] Proximity Domain High(24) : 000000
+[04Ch 0076 4] Clock Domain : 00000000
+
+[050h 0080 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[051h 0081 1] Length : 10
+
+[052h 0082 1] Proximity Domain Low(8) : 00
+[053h 0083 1] Apic ID : 02
+[054h 0084 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[058h 0088 1] Local Sapic EID : 00
+[059h 0089 3] Proximity Domain High(24) : 000000
+[05Ch 0092 4] Clock Domain : 00000000
+
+[060h 0096 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[061h 0097 1] Length : 10
+
+[062h 0098 1] Proximity Domain Low(8) : 01
+[063h 0099 1] Apic ID : 04
+[064h 0100 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[068h 0104 1] Local Sapic EID : 00
+[069h 0105 3] Proximity Domain High(24) : 000000
+[06Ch 0108 4] Clock Domain : 00000000
+
+[070h 0112 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[071h 0113 1] Length : 10
+
+[072h 0114 1] Proximity Domain Low(8) : 01
+[073h 0115 1] Apic ID : 05
+[074h 0116 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[078h 0120 1] Local Sapic EID : 00
+[079h 0121 3] Proximity Domain High(24) : 000000
+[07Ch 0124 4] Clock Domain : 00000000
+
+[080h 0128 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[081h 0129 1] Length : 10
+
+[082h 0130 1] Proximity Domain Low(8) : 01
+[083h 0131 1] Apic ID : 06
+[084h 0132 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[088h 0136 1] Local Sapic EID : 00
+[089h 0137 3] Proximity Domain High(24) : 000000
+[08Ch 0140 4] Clock Domain : 00000000
+
+[090h 0144 1] Subtable Type : 01 [Memory Affinity]
+[091h 0145 1] Length : 28
+
+[092h 0146 4] Proximity Domain : 00000000
+[096h 0150 2] Reserved1 : 0000
+[098h 0152 8] Base Address : 0000000000000000
+[0A0h 0160 8] Address Length : 00000000000A0000
+[0A8h 0168 4] Reserved2 : 00000000
+[0ACh 0172 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0B0h 0176 8] Reserved3 : 0000000000000000
+
+[0B8h 0184 1] Subtable Type : 01 [Memory Affinity]
+[0B9h 0185 1] Length : 28
+
+[0BAh 0186 4] Proximity Domain : 00000000
+[0BEh 0190 2] Reserved1 : 0000
+[0C0h 0192 8] Base Address : 0000000000100000
+[0C8h 0200 8] Address Length : 0000000003F00000
+[0D0h 0208 4] Reserved2 : 00000000
+[0D4h 0212 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0D8h 0216 8] Reserved3 : 0000000000000000
+
+[0E0h 0224 1] Subtable Type : 01 [Memory Affinity]
+[0E1h 0225 1] Length : 28
+
+[0E2h 0226 4] Proximity Domain : 00000001
+[0E6h 0230 2] Reserved1 : 0000
+[0E8h 0232 8] Base Address : 0000000004000000
+[0F0h 0240 8] Address Length : 0000000004000000
+[0F8h 0248 4] Reserved2 : 00000000
+[0FCh 0252 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[100h 0256 8] Reserved3 : 0000000000000000
+
+[108h 0264 1] Subtable Type : 01 [Memory Affinity]
+[109h 0265 1] Length : 28
+
+[10Ah 0266 4] Proximity Domain : 00000000
+[10Eh 0270 2] Reserved1 : 0000
+[110h 0272 8] Base Address : 0000000000000000
+[118h 0280 8] Address Length : 0000000000000000
+[120h 0288 4] Reserved2 : 00000000
+[124h 0292 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[128h 0296 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 304 (0x130)
+
+ 0000: 53 52 41 54 30 01 00 00 01 36 42 4F 43 48 53 20 // SRAT0....6BOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 10 00 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 00 10 00 02 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0060: 00 10 01 04 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0070: 00 10 01 05 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 10 01 06 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 00A0: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 00C0: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................
+ 00D0: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(..............
+ 00F0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0100: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 0110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,194 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/SRAT.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 00000188
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 68
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[031h 0049 1] Length : 10
+
+[032h 0050 1] Proximity Domain Low(8) : 00
+[033h 0051 1] Apic ID : 00
+[034h 0052 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[038h 0056 1] Local Sapic EID : 00
+[039h 0057 3] Proximity Domain High(24) : 000000
+[03Ch 0060 4] Clock Domain : 00000000
+
+[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[041h 0065 1] Length : 10
+
+[042h 0066 1] Proximity Domain Low(8) : 01
+[043h 0067 1] Apic ID : 01
+[044h 0068 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[048h 0072 1] Local Sapic EID : 00
+[049h 0073 3] Proximity Domain High(24) : 000000
+[04Ch 0076 4] Clock Domain : 00000000
+
+[050h 0080 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[051h 0081 1] Length : 10
+
+[052h 0082 1] Proximity Domain Low(8) : 02
+[053h 0083 1] Apic ID : 02
+[054h 0084 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[058h 0088 1] Local Sapic EID : 00
+[059h 0089 3] Proximity Domain High(24) : 000000
+[05Ch 0092 4] Clock Domain : 00000000
+
+[060h 0096 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[061h 0097 1] Length : 10
+
+[062h 0098 1] Proximity Domain Low(8) : 03
+[063h 0099 1] Apic ID : 03
+[064h 0100 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[068h 0104 1] Local Sapic EID : 00
+[069h 0105 3] Proximity Domain High(24) : 000000
+[06Ch 0108 4] Clock Domain : 00000000
+
+[070h 0112 1] Subtable Type : 01 [Memory Affinity]
+[071h 0113 1] Length : 28
+
+[072h 0114 4] Proximity Domain : 00000000
+[076h 0118 2] Reserved1 : 0000
+[078h 0120 8] Base Address : 0000000000000000
+[080h 0128 8] Address Length : 00000000000A0000
+[088h 0136 4] Reserved2 : 00000000
+[08Ch 0140 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[090h 0144 8] Reserved3 : 0000000000000000
+
+[098h 0152 1] Subtable Type : 01 [Memory Affinity]
+[099h 0153 1] Length : 28
+
+[09Ah 0154 4] Proximity Domain : 00000000
+[09Eh 0158 2] Reserved1 : 0000
+[0A0h 0160 8] Base Address : 0000000000100000
+[0A8h 0168 8] Address Length : 0000000001F00000
+[0B0h 0176 4] Reserved2 : 00000000
+[0B4h 0180 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0B8h 0184 8] Reserved3 : 0000000000000000
+
+[0C0h 0192 1] Subtable Type : 01 [Memory Affinity]
+[0C1h 0193 1] Length : 28
+
+[0C2h 0194 4] Proximity Domain : 00000001
+[0C6h 0198 2] Reserved1 : 0000
+[0C8h 0200 8] Base Address : 0000000002000000
+[0D0h 0208 8] Address Length : 0000000002000000
+[0D8h 0216 4] Reserved2 : 00000000
+[0DCh 0220 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0E0h 0224 8] Reserved3 : 0000000000000000
+
+[0E8h 0232 1] Subtable Type : 01 [Memory Affinity]
+[0E9h 0233 1] Length : 28
+
+[0EAh 0234 4] Proximity Domain : 00000002
+[0EEh 0238 2] Reserved1 : 0000
+[0F0h 0240 8] Base Address : 0000000004000000
+[0F8h 0248 8] Address Length : 0000000002000000
+[100h 0256 4] Reserved2 : 00000000
+[104h 0260 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[108h 0264 8] Reserved3 : 0000000000000000
+
+[110h 0272 1] Subtable Type : 01 [Memory Affinity]
+[111h 0273 1] Length : 28
+
+[112h 0274 4] Proximity Domain : 00000003
+[116h 0278 2] Reserved1 : 0000
+[118h 0280 8] Base Address : 0000000006000000
+[120h 0288 8] Address Length : 0000000002000000
+[128h 0296 4] Reserved2 : 00000000
+[12Ch 0300 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[130h 0304 8] Reserved3 : 0000000000000000
+
+[138h 0312 1] Subtable Type : 01 [Memory Affinity]
+[139h 0313 1] Length : 28
+
+[13Ah 0314 4] Proximity Domain : 00000002
+[13Eh 0318 2] Reserved1 : 0000
+[140h 0320 8] Base Address : 0000000108000000
+[148h 0328 8] Address Length : 0000000008000000
+[150h 0336 4] Reserved2 : 00000000
+[154h 0340 4] Flags (decoded below) : 00000005
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 1
+[158h 0344 8] Reserved3 : 0000000000000000
+
+[160h 0352 1] Subtable Type : 01 [Memory Affinity]
+[161h 0353 1] Length : 28
+
+[162h 0354 4] Proximity Domain : 00000003
+[166h 0358 2] Reserved1 : 0000
+[168h 0360 8] Base Address : 0000000100000000
+[170h 0368 8] Address Length : 00000000F8000000
+[178h 0376 4] Reserved2 : 00000000
+[17Ch 0380 4] Flags (decoded below) : 00000003
+ Enabled : 1
+ Hot Pluggable : 1
+ Non-Volatile : 0
+[180h 0384 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 392 (0x188)
+
+ 0000: 53 52 41 54 88 01 00 00 01 68 42 4F 43 48 53 20 // SRAT.....hBOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 10 01 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 00 10 02 02 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0060: 00 10 03 03 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0070: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 0080: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0090: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 00A0: 00 00 10 00 00 00 00 00 00 00 F0 01 00 00 00 00 // ................
+ 00B0: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 01 28 01 00 00 00 00 00 00 00 00 02 00 00 00 00 // .(..............
+ 00D0: 00 00 00 02 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 00E0: 00 00 00 00 00 00 00 00 01 28 02 00 00 00 00 00 // .........(......
+ 00F0: 00 00 00 04 00 00 00 00 00 00 00 02 00 00 00 00 // ................
+ 0100: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0110: 01 28 03 00 00 00 00 00 00 00 00 06 00 00 00 00 // .(..............
+ 0120: 00 00 00 02 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0130: 00 00 00 00 00 00 00 00 01 28 02 00 00 00 00 00 // .........(......
+ 0140: 00 00 00 08 01 00 00 00 00 00 00 08 00 00 00 00 // ................
+ 0150: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0160: 01 28 03 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(..............
+ 0170: 00 00 00 F8 00 00 00 00 00 00 00 00 03 00 00 00 // ................
+ 0180: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
@@ -0,0 +1,108 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/SRAT.numamem, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 000000E0
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : F5
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[031h 0049 1] Length : 10
+
+[032h 0050 1] Proximity Domain Low(8) : 00
+[033h 0051 1] Apic ID : 00
+[034h 0052 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[038h 0056 1] Local Sapic EID : 00
+[039h 0057 3] Proximity Domain High(24) : 000000
+[03Ch 0060 4] Clock Domain : 00000000
+
+[040h 0064 1] Subtable Type : 01 [Memory Affinity]
+[041h 0065 1] Length : 28
+
+[042h 0066 4] Proximity Domain : 00000001
+[046h 0070 2] Reserved1 : 0000
+[048h 0072 8] Base Address : 0000000000000000
+[050h 0080 8] Address Length : 00000000000A0000
+[058h 0088 4] Reserved2 : 00000000
+[05Ch 0092 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[060h 0096 8] Reserved3 : 0000000000000000
+
+[068h 0104 1] Subtable Type : 01 [Memory Affinity]
+[069h 0105 1] Length : 28
+
+[06Ah 0106 4] Proximity Domain : 00000001
+[06Eh 0110 2] Reserved1 : 0000
+[070h 0112 8] Base Address : 0000000000100000
+[078h 0120 8] Address Length : 0000000007F00000
+[080h 0128 4] Reserved2 : 00000000
+[084h 0132 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[088h 0136 8] Reserved3 : 0000000000000000
+
+[090h 0144 1] Subtable Type : 01 [Memory Affinity]
+[091h 0145 1] Length : 28
+
+[092h 0146 4] Proximity Domain : 00000000
+[096h 0150 2] Reserved1 : 0000
+[098h 0152 8] Base Address : 0000000000000000
+[0A0h 0160 8] Address Length : 0000000000000000
+[0A8h 0168 4] Reserved2 : 00000000
+[0ACh 0172 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0B0h 0176 8] Reserved3 : 0000000000000000
+
+[0B8h 0184 1] Subtable Type : 01 [Memory Affinity]
+[0B9h 0185 1] Length : 28
+
+[0BAh 0186 4] Proximity Domain : 00000000
+[0BEh 0190 2] Reserved1 : 0000
+[0C0h 0192 8] Base Address : 0000000000000000
+[0C8h 0200 8] Address Length : 0000000000000000
+[0D0h 0208 4] Reserved2 : 00000000
+[0D4h 0212 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0D8h 0216 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 224 (0xE0)
+
+ 0000: 53 52 41 54 E0 00 00 00 01 F5 42 4F 43 48 53 20 // SRAT......BOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 01 28 01 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 01 28 01 00 00 00 00 00 // .........(......
+ 0070: 00 00 10 00 00 00 00 00 00 00 F0 07 00 00 00 00 // ................
+ 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,125 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/SRAT.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 00000108
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : A2
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[031h 0049 1] Length : 10
+
+[032h 0050 1] Proximity Domain Low(8) : 00
+[033h 0051 1] Apic ID : 00
+[034h 0052 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[038h 0056 1] Local Sapic EID : 00
+[039h 0057 3] Proximity Domain High(24) : 000000
+[03Ch 0060 4] Clock Domain : 00000000
+
+[040h 0064 1] Subtable Type : 01 [Memory Affinity]
+[041h 0065 1] Length : 28
+
+[042h 0066 4] Proximity Domain : 00000000
+[046h 0070 2] Reserved1 : 0000
+[048h 0072 8] Base Address : 0000000000000000
+[050h 0080 8] Address Length : 00000000000A0000
+[058h 0088 4] Reserved2 : 00000000
+[05Ch 0092 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[060h 0096 8] Reserved3 : 0000000000000000
+
+[068h 0104 1] Subtable Type : 01 [Memory Affinity]
+[069h 0105 1] Length : 28
+
+[06Ah 0106 4] Proximity Domain : 00000000
+[06Eh 0110 2] Reserved1 : 0000
+[070h 0112 8] Base Address : 0000000000100000
+[078h 0120 8] Address Length : 0000000003F00000
+[080h 0128 4] Reserved2 : 00000000
+[084h 0132 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[088h 0136 8] Reserved3 : 0000000000000000
+
+[090h 0144 1] Subtable Type : 01 [Memory Affinity]
+[091h 0145 1] Length : 28
+
+[092h 0146 4] Proximity Domain : 00000001
+[096h 0150 2] Reserved1 : 0000
+[098h 0152 8] Base Address : 0000000004000000
+[0A0h 0160 8] Address Length : 0000000004000000
+[0A8h 0168 4] Reserved2 : 00000000
+[0ACh 0172 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0B0h 0176 8] Reserved3 : 0000000000000000
+
+[0B8h 0184 1] Subtable Type : 01 [Memory Affinity]
+[0B9h 0185 1] Length : 28
+
+[0BAh 0186 4] Proximity Domain : 00000000
+[0BEh 0190 2] Reserved1 : 0000
+[0C0h 0192 8] Base Address : 0000000000000000
+[0C8h 0200 8] Address Length : 0000000000000000
+[0D0h 0208 4] Reserved2 : 00000000
+[0D4h 0212 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0D8h 0216 8] Reserved3 : 0000000000000000
+
+[0E0h 0224 1] Subtable Type : 01 [Memory Affinity]
+[0E1h 0225 1] Length : 28
+
+[0E2h 0226 4] Proximity Domain : 00000001
+[0E6h 0230 2] Reserved1 : 0000
+[0E8h 0232 8] Base Address : 0000000100000000
+[0F0h 0240 8] Address Length : 00000000F8000000
+[0F8h 0248 4] Reserved2 : 00000000
+[0FCh 0252 4] Flags (decoded below) : 00000003
+ Enabled : 1
+ Hot Pluggable : 1
+ Non-Volatile : 0
+[100h 0256 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 264 (0x108)
+
+ 0000: 53 52 41 54 08 01 00 00 01 A2 42 4F 43 48 53 20 // SRAT......BOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 0070: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................
+ 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(..............
+ 00A0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 01 28 01 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(..............
+ 00F0: 00 00 00 F8 00 00 00 00 00 00 00 00 03 00 00 00 // ................
+ 0100: 00 00 00 00 00 00 00 00 // ........
new file mode 100644
@@ -0,0 +1,108 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/SRAT.mmio64, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 000000E0
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 3B
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[031h 0049 1] Length : 10
+
+[032h 0050 1] Proximity Domain Low(8) : 00
+[033h 0051 1] Apic ID : 00
+[034h 0052 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[038h 0056 1] Local Sapic EID : 00
+[039h 0057 3] Proximity Domain High(24) : 000000
+[03Ch 0060 4] Clock Domain : 00000000
+
+[040h 0064 1] Subtable Type : 01 [Memory Affinity]
+[041h 0065 1] Length : 28
+
+[042h 0066 4] Proximity Domain : 00000000
+[046h 0070 2] Reserved1 : 0000
+[048h 0072 8] Base Address : 0000000000000000
+[050h 0080 8] Address Length : 00000000000A0000
+[058h 0088 4] Reserved2 : 00000000
+[05Ch 0092 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[060h 0096 8] Reserved3 : 0000000000000000
+
+[068h 0104 1] Subtable Type : 01 [Memory Affinity]
+[069h 0105 1] Length : 28
+
+[06Ah 0106 4] Proximity Domain : 00000000
+[06Eh 0110 2] Reserved1 : 0000
+[070h 0112 8] Base Address : 0000000000100000
+[078h 0120 8] Address Length : 0000000007F00000
+[080h 0128 4] Reserved2 : 00000000
+[084h 0132 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[088h 0136 8] Reserved3 : 0000000000000000
+
+[090h 0144 1] Subtable Type : 01 [Memory Affinity]
+[091h 0145 1] Length : 28
+
+[092h 0146 4] Proximity Domain : 00000000
+[096h 0150 2] Reserved1 : 0000
+[098h 0152 8] Base Address : 0000000000000000
+[0A0h 0160 8] Address Length : 0000000000000000
+[0A8h 0168 4] Reserved2 : 00000000
+[0ACh 0172 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0B0h 0176 8] Reserved3 : 0000000000000000
+
+[0B8h 0184 1] Subtable Type : 01 [Memory Affinity]
+[0B9h 0185 1] Length : 28
+
+[0BAh 0186 4] Proximity Domain : 00000000
+[0BEh 0190 2] Reserved1 : 0000
+[0C0h 0192 8] Base Address : 0000000100000000
+[0C8h 0200 8] Address Length : 00000000B8000000
+[0D0h 0208 4] Reserved2 : 00000000
+[0D4h 0212 4] Flags (decoded below) : 00000003
+ Enabled : 1
+ Hot Pluggable : 1
+ Non-Volatile : 0
+[0D8h 0216 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 224 (0xE0)
+
+ 0000: 53 52 41 54 E0 00 00 00 01 3B 42 4F 43 48 53 20 // SRAT.....;BOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 0070: 00 00 10 00 00 00 00 00 00 00 F0 07 00 00 00 00 // ................
+ 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 00C0: 00 00 00 00 01 00 00 00 00 00 00 B8 00 00 00 00 // ................
+ 00D0: 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,108 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/SRAT.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 000000E0
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : F5
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity]
+[031h 0049 1] Length : 10
+
+[032h 0050 1] Proximity Domain Low(8) : 00
+[033h 0051 1] Apic ID : 00
+[034h 0052 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[038h 0056 1] Local Sapic EID : 00
+[039h 0057 3] Proximity Domain High(24) : 000000
+[03Ch 0060 4] Clock Domain : 00000000
+
+[040h 0064 1] Subtable Type : 01 [Memory Affinity]
+[041h 0065 1] Length : 28
+
+[042h 0066 4] Proximity Domain : 00000001
+[046h 0070 2] Reserved1 : 0000
+[048h 0072 8] Base Address : 0000000000000000
+[050h 0080 8] Address Length : 00000000000A0000
+[058h 0088 4] Reserved2 : 00000000
+[05Ch 0092 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[060h 0096 8] Reserved3 : 0000000000000000
+
+[068h 0104 1] Subtable Type : 01 [Memory Affinity]
+[069h 0105 1] Length : 28
+
+[06Ah 0106 4] Proximity Domain : 00000001
+[06Eh 0110 2] Reserved1 : 0000
+[070h 0112 8] Base Address : 0000000000100000
+[078h 0120 8] Address Length : 0000000007F00000
+[080h 0128 4] Reserved2 : 00000000
+[084h 0132 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[088h 0136 8] Reserved3 : 0000000000000000
+
+[090h 0144 1] Subtable Type : 01 [Memory Affinity]
+[091h 0145 1] Length : 28
+
+[092h 0146 4] Proximity Domain : 00000000
+[096h 0150 2] Reserved1 : 0000
+[098h 0152 8] Base Address : 0000000000000000
+[0A0h 0160 8] Address Length : 0000000000000000
+[0A8h 0168 4] Reserved2 : 00000000
+[0ACh 0172 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0B0h 0176 8] Reserved3 : 0000000000000000
+
+[0B8h 0184 1] Subtable Type : 01 [Memory Affinity]
+[0B9h 0185 1] Length : 28
+
+[0BAh 0186 4] Proximity Domain : 00000000
+[0BEh 0190 2] Reserved1 : 0000
+[0C0h 0192 8] Base Address : 0000000000000000
+[0C8h 0200 8] Address Length : 0000000000000000
+[0D0h 0208 4] Reserved2 : 00000000
+[0D4h 0212 4] Flags (decoded below) : 00000000
+ Enabled : 0
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[0D8h 0216 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 224 (0xE0)
+
+ 0000: 53 52 41 54 E0 00 00 00 01 F5 42 4F 43 48 53 20 // SRAT......BOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 01 28 01 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 01 28 01 00 00 00 00 00 // .........(......
+ 0070: 00 00 10 00 00 00 00 00 00 00 F0 07 00 00 00 00 // ................
+ 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(..............
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(......
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,205 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/q35/SSDT.dimmpxm, Mon Sep 28 17:24:38 2020
+ *
+ * Original Table Header:
+ * Signature "SSDT"
+ * Length 0x000002DE (734)
+ * Revision 0x01
+ * Checksum 0x46
+ * OEM ID "BOCHS "
+ * OEM Table ID "NVDIMM"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001)
+{
+ Scope (\_SB)
+ {
+ Device (NVDR)
+ {
+ Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Hardware ID
+ Method (NCAL, 5, Serialized)
+ {
+ Local6 = MEMA /* \MEMA */
+ OperationRegion (NPIO, SystemIO, 0x0A18, 0x04)
+ OperationRegion (NRAM, SystemMemory, Local6, 0x1000)
+ Field (NPIO, DWordAcc, NoLock, Preserve)
+ {
+ NTFI, 32
+ }
+
+ Field (NRAM, DWordAcc, NoLock, Preserve)
+ {
+ HDLE, 32,
+ REVS, 32,
+ FUNC, 32,
+ FARG, 32672
+ }
+
+ Field (NRAM, DWordAcc, NoLock, Preserve)
+ {
+ RLEN, 32,
+ ODAT, 32736
+ }
+
+ If ((Arg4 == Zero))
+ {
+ Local0 = ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75cba")
+ }
+ ElseIf ((Arg4 == 0x00010000))
+ {
+ Local0 = ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62")
+ }
+ Else
+ {
+ Local0 = ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66")
+ }
+
+ If (((Local6 == Zero) | (Arg0 != Local0)))
+ {
+ If ((Arg2 == Zero))
+ {
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+
+ Return (Buffer (One)
+ {
+ 0x01 // .
+ })
+ }
+
+ HDLE = Arg4
+ REVS = Arg1
+ FUNC = Arg2
+ If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One)))
+ {
+ Local2 = Arg3 [Zero]
+ Local3 = DerefOf (Local2)
+ FARG = Local3
+ }
+
+ NTFI = Local6
+ Local1 = (RLEN - 0x04)
+ If ((Local1 < 0x08))
+ {
+ Local2 = Zero
+ Name (TBUF, Buffer (One)
+ {
+ 0x00 // .
+ })
+ Local7 = Buffer (Zero){}
+ While ((Local2 < Local1))
+ {
+ TBUF [Zero] = DerefOf (ODAT [Local2])
+ Concatenate (Local7, TBUF, Local7)
+ Local2++
+ }
+
+ Return (Local7)
+ }
+
+ Local1 = (Local1 << 0x03)
+ CreateField (ODAT, Zero, Local1, OBUF)
+ Return (OBUF) /* \_SB_.NVDR.NCAL.OBUF */
+ }
+
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ Return (NCAL (Arg0, Arg1, Arg2, Arg3, Zero))
+ }
+
+ Name (RSTA, Zero)
+ Method (RFIT, 1, Serialized)
+ {
+ Name (OFST, Zero)
+ OFST = Arg0
+ Local0 = NCAL (ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62"), One, One, Package (0x01)
+ {
+ OFST
+ }, 0x00010000)
+ CreateDWordField (Local0, Zero, STAU)
+ RSTA = STAU /* \_SB_.NVDR.RFIT.STAU */
+ If ((Zero != STAU))
+ {
+ Return (Buffer (Zero){})
+ }
+
+ Local1 = SizeOf (Local0)
+ Local1 -= 0x04
+ If ((Local1 == Zero))
+ {
+ Return (Buffer (Zero){})
+ }
+
+ CreateField (Local0, 0x20, (Local1 << 0x03), BUFF)
+ Return (BUFF) /* \_SB_.NVDR.RFIT.BUFF */
+ }
+
+ Method (_FIT, 0, Serialized) // _FIT: Firmware Interface Table
+ {
+ Local2 = Buffer (Zero){}
+ Local3 = Zero
+ While (One)
+ {
+ Local0 = RFIT (Local3)
+ Local1 = SizeOf (Local0)
+ If ((RSTA == 0x0100))
+ {
+ Local2 = Buffer (Zero){}
+ Local3 = Zero
+ }
+ Else
+ {
+ If ((Local1 == Zero))
+ {
+ Return (Local2)
+ }
+
+ Local3 += Local1
+ Concatenate (Local2, Local0, Local2)
+ }
+ }
+ }
+
+ Device (NV00)
+ {
+ Name (_ADR, One) // _ADR: Address
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ Return (NCAL (Arg0, Arg1, Arg2, Arg3, One))
+ }
+ }
+
+ Device (NV01)
+ {
+ Name (_ADR, 0x02) // _ADR: Address
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x02))
+ }
+ }
+
+ Device (NV02)
+ {
+ Name (_ADR, 0x03) // _ADR: Address
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x03))
+ }
+ }
+ }
+ }
+
+ Name (MEMA, 0x07FFF000)
+}
+
new file mode 100644
@@ -0,0 +1,38 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/TPM2.tis, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [TPM2]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "TPM2" [Trusted Platform Module hardware interface table]
+[004h 0004 4] Table Length : 0000004C
+[008h 0008 1] Revision : 04
+[009h 0009 1] Checksum : 72
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCTPM2"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 2] Platform Class : 0000
+[026h 0038 2] Reserved : 0000
+[028h 0040 8] Control Address : 0000000000000000
+[030h 0048 4] Start Method : 06 [Memory Mapped I/O]
+
+[034h 0052 12] Method Parameters : 00 00 00 00 00 00 00 00 00 00 00 00
+[040h 0064 4] Minimum Log Length : 00010000
+[044h 0068 8] Log Address : 0000000007FF0000
+
+Raw Table Data: Length 76 (0x4C)
+
+ 0000: 54 50 4D 32 4C 00 00 00 04 72 42 4F 43 48 53 20 // TPM2L....rBOCHS
+ 0010: 42 58 50 43 54 50 4D 32 01 00 00 00 42 58 50 43 // BXPCTPM2....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 00 01 00 00 00 FF 07 00 00 00 00 // ............
new file mode 100644
@@ -0,0 +1,38 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/TPM2.tis, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [TPM2]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "TPM2" [Trusted Platform Module hardware interface table]
+[004h 0004 4] Table Length : 0000004C
+[008h 0008 1] Revision : 04
+[009h 0009 1] Checksum : 72
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCTPM2"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 2] Platform Class : 0000
+[026h 0038 2] Reserved : 0000
+[028h 0040 8] Control Address : 0000000000000000
+[030h 0048 4] Start Method : 06 [Memory Mapped I/O]
+
+[034h 0052 12] Method Parameters : 00 00 00 00 00 00 00 00 00 00 00 00
+[040h 0064 4] Minimum Log Length : 00010000
+[044h 0068 8] Log Address : 0000000007FF0000
+
+Raw Table Data: Length 76 (0x4C)
+
+ 0000: 54 50 4D 32 4C 00 00 00 04 72 42 4F 43 48 53 20 // TPM2L....rBOCHS
+ 0010: 42 58 50 43 54 50 4D 32 01 00 00 00 42 58 50 43 // BXPCTPM2....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 00 01 00 00 00 FF 07 00 00 00 00 // ............
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/WAET.acpihmat, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/WAET.bridge, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/WAET.cphp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/WAET.dimmpxm, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/WAET.tis, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/WAET.ipmibt, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/WAET.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/WAET.mmio64, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/WAET.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
GIT binary patch
literal 40
mcmWG{bPds9U|?YEaPoKd2v%^42yhMuiZKGkKx`1r1jGQWX$JuS
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/q35/WAET.tis, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [WAET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table]
+[004h 0004 4] Table Length : 00000028
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 88
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCWAET"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Flags (decoded below) : 00000002
+ RTC needs no INT ack : 0
+ PM timer, one read only : 1
+
+Raw Table Data: Length 40 (0x28)
+
+ 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS
+ 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC
+ 0020: 01 00 00 00 02 00 00 00 // ........
new file mode 100644
@@ -0,0 +1,78 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/APIC.numamem, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 000000A8
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : 00000000
+[028h 0040 4] Flags (decoded below) : 00000000
+ PC-AT Compatibility : 0
+
+[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor]
+[02Dh 0045 1] Length : 18
+[02Eh 0046 2] Reserved : 0000
+[030h 0048 4] Local GIC Hardware ID : 00000000
+[034h 0052 8] Base Address : 0000000008000000
+[03Ch 0060 4] Interrupt Base : 00000000
+[040h 0064 1] Version : 02
+[041h 0065 3] Reserved : 000000
+
+[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller]
+[045h 0069 1] Length : 4C
+[046h 0070 2] Reserved : 0000
+[048h 0072 4] CPU Interface Number : 00000000
+[04Ch 0076 4] Processor UID : 00000000
+[050h 0080 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[054h 0084 4] Parking Protocol Version : 00000000
+[058h 0088 4] Performance Interrupt : 00000017
+[05Ch 0092 8] Parked Address : 0000000000000000
+[064h 0100 8] Base Address : 0000000008010000
+[06Ch 0108 8] Virtual GIC Base Address : 0000000008040000
+[074h 0116 8] Hypervisor GIC Base Address : 0000000008030000
+[07Ch 0124 4] Virtual GIC Interrupt : 00000000
+[080h 0128 8] Redistributor Base Address : 0000000000000000
+[088h 0136 8] ARM MPIDR : 0000000000000000
+/**** ACPI subtable terminates early - may be older version (dump table) */
+
+[090h 0144 1] Subtable Type : 0D [Generic MSI Frame]
+[091h 0145 1] Length : 18
+[092h 0146 2] Reserved : 0000
+[094h 0148 4] MSI Frame ID : 00000000
+[098h 0152 8] Base Address : 0000000008020000
+[0A0h 0160 4] Flags (decoded below) : 00000001
+ Select SPI : 1
+[0A4h 0164 2] SPI Count : 0040
+[0A6h 0166 2] SPI Base : 0050
+
+Raw Table Data: Length 168 (0xA8)
+
+ 0000: 41 50 49 43 A8 00 00 00 03 B3 42 4F 43 48 53 20 // APIC......BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................
+ 0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L..........
+ 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 04 08 // ................
+ 0070: 00 00 00 00 00 00 03 08 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 0D 18 00 00 00 00 00 00 00 00 02 08 00 00 00 00 // ................
+ 00A0: 01 00 00 00 40 00 50 00 // ....@.P.
new file mode 100644
@@ -0,0 +1,78 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/APIC.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 000000A8
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : 00000000
+[028h 0040 4] Flags (decoded below) : 00000000
+ PC-AT Compatibility : 0
+
+[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor]
+[02Dh 0045 1] Length : 18
+[02Eh 0046 2] Reserved : 0000
+[030h 0048 4] Local GIC Hardware ID : 00000000
+[034h 0052 8] Base Address : 0000000008000000
+[03Ch 0060 4] Interrupt Base : 00000000
+[040h 0064 1] Version : 02
+[041h 0065 3] Reserved : 000000
+
+[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller]
+[045h 0069 1] Length : 4C
+[046h 0070 2] Reserved : 0000
+[048h 0072 4] CPU Interface Number : 00000000
+[04Ch 0076 4] Processor UID : 00000000
+[050h 0080 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[054h 0084 4] Parking Protocol Version : 00000000
+[058h 0088 4] Performance Interrupt : 00000017
+[05Ch 0092 8] Parked Address : 0000000000000000
+[064h 0100 8] Base Address : 0000000008010000
+[06Ch 0108 8] Virtual GIC Base Address : 0000000008040000
+[074h 0116 8] Hypervisor GIC Base Address : 0000000008030000
+[07Ch 0124 4] Virtual GIC Interrupt : 00000000
+[080h 0128 8] Redistributor Base Address : 0000000000000000
+[088h 0136 8] ARM MPIDR : 0000000000000000
+/**** ACPI subtable terminates early - may be older version (dump table) */
+
+[090h 0144 1] Subtable Type : 0D [Generic MSI Frame]
+[091h 0145 1] Length : 18
+[092h 0146 2] Reserved : 0000
+[094h 0148 4] MSI Frame ID : 00000000
+[098h 0152 8] Base Address : 0000000008020000
+[0A0h 0160 4] Flags (decoded below) : 00000001
+ Select SPI : 1
+[0A4h 0164 2] SPI Count : 0040
+[0A6h 0166 2] SPI Base : 0050
+
+Raw Table Data: Length 168 (0xA8)
+
+ 0000: 41 50 49 43 A8 00 00 00 03 B3 42 4F 43 48 53 20 // APIC......BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................
+ 0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L..........
+ 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 04 08 // ................
+ 0070: 00 00 00 00 00 00 03 08 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 0D 18 00 00 00 00 00 00 00 00 02 08 00 00 00 00 // ................
+ 00A0: 01 00 00 00 40 00 50 00 // ....@.P.
new file mode 100644
@@ -0,0 +1,78 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/APIC.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 000000A8
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : B3
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCAPIC"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Local Apic Address : 00000000
+[028h 0040 4] Flags (decoded below) : 00000000
+ PC-AT Compatibility : 0
+
+[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor]
+[02Dh 0045 1] Length : 18
+[02Eh 0046 2] Reserved : 0000
+[030h 0048 4] Local GIC Hardware ID : 00000000
+[034h 0052 8] Base Address : 0000000008000000
+[03Ch 0060 4] Interrupt Base : 00000000
+[040h 0064 1] Version : 02
+[041h 0065 3] Reserved : 000000
+
+[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller]
+[045h 0069 1] Length : 4C
+[046h 0070 2] Reserved : 0000
+[048h 0072 4] CPU Interface Number : 00000000
+[04Ch 0076 4] Processor UID : 00000000
+[050h 0080 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+ Performance Interrupt Trigger Mode : 0
+ Virtual GIC Interrupt Trigger Mode : 0
+[054h 0084 4] Parking Protocol Version : 00000000
+[058h 0088 4] Performance Interrupt : 00000017
+[05Ch 0092 8] Parked Address : 0000000000000000
+[064h 0100 8] Base Address : 0000000008010000
+[06Ch 0108 8] Virtual GIC Base Address : 0000000008040000
+[074h 0116 8] Hypervisor GIC Base Address : 0000000008030000
+[07Ch 0124 4] Virtual GIC Interrupt : 00000000
+[080h 0128 8] Redistributor Base Address : 0000000000000000
+[088h 0136 8] ARM MPIDR : 0000000000000000
+/**** ACPI subtable terminates early - may be older version (dump table) */
+
+[090h 0144 1] Subtable Type : 0D [Generic MSI Frame]
+[091h 0145 1] Length : 18
+[092h 0146 2] Reserved : 0000
+[094h 0148 4] MSI Frame ID : 00000000
+[098h 0152 8] Base Address : 0000000008020000
+[0A0h 0160 4] Flags (decoded below) : 00000001
+ Select SPI : 1
+[0A4h 0164 2] SPI Count : 0040
+[0A6h 0166 2] SPI Base : 0050
+
+Raw Table Data: Length 168 (0xA8)
+
+ 0000: 41 50 49 43 A8 00 00 00 03 B3 42 4F 43 48 53 20 // APIC......BOCHS
+ 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................
+ 0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L..........
+ 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 04 08 // ................
+ 0070: 00 00 00 00 00 00 03 08 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 0D 18 00 00 00 00 00 00 00 00 02 08 00 00 00 00 // ................
+ 00A0: 01 00 00 00 40 00 50 00 // ....@.P.
new file mode 100644
@@ -0,0 +1,1906 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/virt/DSDT.numamem, Mon Sep 28 17:24:38 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00001450 (5200)
+ * Revision 0x02
+ * Checksum 0xFA
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\_SB)
+ {
+ Device (C000)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+
+ Device (COM0)
+ {
+ Name (_HID, "ARMH0011") // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x09000000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000021,
+ }
+ })
+ }
+
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x09020000, // Address Base
+ 0x00000018, // Address Length
+ )
+ })
+ }
+
+ Device (VR00)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000000, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000030,
+ }
+ })
+ }
+
+ Device (VR01)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000200, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000031,
+ }
+ })
+ }
+
+ Device (VR02)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000400, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000032,
+ }
+ })
+ }
+
+ Device (VR03)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000600, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000033,
+ }
+ })
+ }
+
+ Device (VR04)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000800, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000034,
+ }
+ })
+ }
+
+ Device (VR05)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000A00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000035,
+ }
+ })
+ }
+
+ Device (VR06)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000C00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000036,
+ }
+ })
+ }
+
+ Device (VR07)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000E00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000037,
+ }
+ })
+ }
+
+ Device (VR08)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x08) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001000, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000038,
+ }
+ })
+ }
+
+ Device (VR09)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x09) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001200, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000039,
+ }
+ })
+ }
+
+ Device (VR10)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0A) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001400, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003A,
+ }
+ })
+ }
+
+ Device (VR11)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0B) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001600, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003B,
+ }
+ })
+ }
+
+ Device (VR12)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0C) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001800, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003C,
+ }
+ })
+ }
+
+ Device (VR13)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0D) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001A00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003D,
+ }
+ })
+ }
+
+ Device (VR14)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0E) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001C00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003E,
+ }
+ })
+ }
+
+ Device (VR15)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0F) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001E00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003F,
+ }
+ })
+ }
+
+ Device (VR16)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002000, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000040,
+ }
+ })
+ }
+
+ Device (VR17)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x11) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002200, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000041,
+ }
+ })
+ }
+
+ Device (VR18)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x12) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002400, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000042,
+ }
+ })
+ }
+
+ Device (VR19)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x13) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002600, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000043,
+ }
+ })
+ }
+
+ Device (VR20)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002800, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000044,
+ }
+ })
+ }
+
+ Device (VR21)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002A00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000045,
+ }
+ })
+ }
+
+ Device (VR22)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x16) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002C00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000046,
+ }
+ })
+ }
+
+ Device (VR23)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x17) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002E00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000047,
+ }
+ })
+ }
+
+ Device (VR24)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x18) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003000, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000048,
+ }
+ })
+ }
+
+ Device (VR25)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x19) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003200, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000049,
+ }
+ })
+ }
+
+ Device (VR26)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1A) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003400, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004A,
+ }
+ })
+ }
+
+ Device (VR27)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1B) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003600, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004B,
+ }
+ })
+ }
+
+ Device (VR28)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1C) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003800, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004C,
+ }
+ })
+ }
+
+ Device (VR29)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1D) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003A00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004D,
+ }
+ })
+ }
+
+ Device (VR30)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1E) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003C00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004E,
+ }
+ })
+ }
+
+ Device (VR31)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1F) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003E00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004F,
+ }
+ })
+ }
+
+ Device (PCI0)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, Zero) // _SEG: PCI Segment
+ Name (_BBN, Zero) // _BBN: BIOS Bus Number
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_PRT, Package (0x80) // _PRT: PCI Routing Table
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSI2,
+ Zero
+ }
+ })
+ Device (GSI0)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000023,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000023,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSI1)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000024,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000024,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSI2)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000025,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000025,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSI3)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000026,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000026,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
+ {
+ Return (0x0000004010000000)
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x10000000, // Range Minimum
+ 0x3EFEFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x2EFF0000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ 0x3EFF0000, // Translation Offset
+ 0x00010000, // Length
+ ,, , TypeStatic, DenseTranslation)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000008000000000, // Range Minimum
+ 0x000000FFFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000008000000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ }
+
+ Name (SUPP, Zero)
+ Name (CTRL, Zero)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */
+ CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ CTRL &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != CTRL))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = CTRL /* \_SB_.PCI0.CTRL */
+ Return (Arg3)
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ Return (Arg3)
+ }
+ }
+
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
+ {
+ If ((Arg2 == Zero))
+ {
+ Return (Buffer (One)
+ {
+ 0x01 // .
+ })
+ }
+ }
+
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000004010000000, // Range Minimum
+ 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000010000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ }
+ }
+
+ Device (\_SB.GED)
+ {
+ Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
+ Name (_UID, "GED") // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000029,
+ }
+ })
+ OperationRegion (EREG, SystemMemory, 0x09080000, 0x04)
+ Field (EREG, DWordAcc, NoLock, WriteAsZeros)
+ {
+ ESEL, 32
+ }
+
+ Method (_EVT, 1, Serialized) // _EVT: Event
+ {
+ Local0 = ESEL /* \_SB_.GED_.ESEL */
+ If (((Local0 & 0x02) == 0x02))
+ {
+ Notify (PWRB, 0x80) // Status Change
+ }
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+ }
+}
+
new file mode 100644
@@ -0,0 +1,2215 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/virt/DSDT.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x000019A6 (6566)
+ * Revision 0x02
+ * Checksum 0x02
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ External (_SB_.NVDR, UnknownObj)
+
+ Scope (\_SB)
+ {
+ Device (C000)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+
+ Device (COM0)
+ {
+ Name (_HID, "ARMH0011") // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x09000000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000021,
+ }
+ })
+ }
+
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x09020000, // Address Base
+ 0x00000018, // Address Length
+ )
+ })
+ }
+
+ Device (VR00)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000000, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000030,
+ }
+ })
+ }
+
+ Device (VR01)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000200, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000031,
+ }
+ })
+ }
+
+ Device (VR02)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000400, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000032,
+ }
+ })
+ }
+
+ Device (VR03)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000600, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000033,
+ }
+ })
+ }
+
+ Device (VR04)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000800, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000034,
+ }
+ })
+ }
+
+ Device (VR05)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000A00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000035,
+ }
+ })
+ }
+
+ Device (VR06)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000C00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000036,
+ }
+ })
+ }
+
+ Device (VR07)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000E00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000037,
+ }
+ })
+ }
+
+ Device (VR08)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x08) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001000, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000038,
+ }
+ })
+ }
+
+ Device (VR09)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x09) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001200, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000039,
+ }
+ })
+ }
+
+ Device (VR10)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0A) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001400, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003A,
+ }
+ })
+ }
+
+ Device (VR11)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0B) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001600, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003B,
+ }
+ })
+ }
+
+ Device (VR12)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0C) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001800, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003C,
+ }
+ })
+ }
+
+ Device (VR13)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0D) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001A00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003D,
+ }
+ })
+ }
+
+ Device (VR14)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0E) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001C00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003E,
+ }
+ })
+ }
+
+ Device (VR15)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0F) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001E00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003F,
+ }
+ })
+ }
+
+ Device (VR16)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002000, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000040,
+ }
+ })
+ }
+
+ Device (VR17)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x11) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002200, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000041,
+ }
+ })
+ }
+
+ Device (VR18)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x12) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002400, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000042,
+ }
+ })
+ }
+
+ Device (VR19)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x13) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002600, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000043,
+ }
+ })
+ }
+
+ Device (VR20)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002800, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000044,
+ }
+ })
+ }
+
+ Device (VR21)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002A00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000045,
+ }
+ })
+ }
+
+ Device (VR22)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x16) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002C00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000046,
+ }
+ })
+ }
+
+ Device (VR23)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x17) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002E00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000047,
+ }
+ })
+ }
+
+ Device (VR24)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x18) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003000, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000048,
+ }
+ })
+ }
+
+ Device (VR25)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x19) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003200, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000049,
+ }
+ })
+ }
+
+ Device (VR26)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1A) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003400, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004A,
+ }
+ })
+ }
+
+ Device (VR27)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1B) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003600, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004B,
+ }
+ })
+ }
+
+ Device (VR28)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1C) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003800, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004C,
+ }
+ })
+ }
+
+ Device (VR29)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1D) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003A00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004D,
+ }
+ })
+ }
+
+ Device (VR30)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1E) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003C00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004E,
+ }
+ })
+ }
+
+ Device (VR31)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1F) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003E00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004F,
+ }
+ })
+ }
+
+ Device (PCI0)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, Zero) // _SEG: PCI Segment
+ Name (_BBN, Zero) // _BBN: BIOS Bus Number
+ Name (_UID, "PCI0") // _UID: Unique ID
+ Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_PRT, Package (0x80) // _PRT: PCI Routing Table
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSI2,
+ Zero
+ }
+ })
+ Device (GSI0)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000023,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000023,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSI1)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000024,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000024,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSI2)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000025,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000025,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSI3)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000026,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000026,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
+ {
+ Return (0x0000004010000000)
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x10000000, // Range Minimum
+ 0x3EFEFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x2EFF0000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ 0x3EFF0000, // Translation Offset
+ 0x00010000, // Length
+ ,, , TypeStatic, DenseTranslation)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000008000000000, // Range Minimum
+ 0x000000FFFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000008000000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ }
+
+ Name (SUPP, Zero)
+ Name (CTRL, Zero)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */
+ CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ CTRL &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != CTRL))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = CTRL /* \_SB_.PCI0.CTRL */
+ Return (Arg3)
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ Return (Arg3)
+ }
+ }
+
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
+ {
+ If ((Arg2 == Zero))
+ {
+ Return (Buffer (One)
+ {
+ 0x01 // .
+ })
+ }
+ }
+
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000004010000000, // Range Minimum
+ 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000010000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ }
+ }
+
+ Device (\_SB.GED)
+ {
+ Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
+ Name (_UID, "GED") // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000029,
+ }
+ })
+ OperationRegion (EREG, SystemMemory, 0x09080000, 0x04)
+ Field (EREG, DWordAcc, NoLock, WriteAsZeros)
+ {
+ ESEL, 32
+ }
+
+ Method (_EVT, 1, Serialized) // _EVT: Event
+ {
+ Local0 = ESEL /* \_SB_.GED_.ESEL */
+ If (((Local0 & One) == One))
+ {
+ \_SB.MHPC.MSCN ()
+ }
+
+ If (((Local0 & 0x02) == 0x02))
+ {
+ Notify (PWRB, 0x80) // Status Change
+ }
+
+ If (((Local0 & 0x04) == 0x04))
+ {
+ Notify (\_SB.NVDR, 0x80) // Status Change
+ }
+ }
+ }
+
+ Device (\_SB.MHPD)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "Memory hotplug resources") // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x09070000, // Address Base
+ 0x00000018, // Address Length
+ )
+ })
+ OperationRegion (HPMR, SystemMemory, 0x09070000, 0x18)
+ }
+
+ Device (\_SB.MHPC)
+ {
+ Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID
+ Name (_UID, "DIMM devices") // _UID: Unique ID
+ Name (MDNR, 0x03)
+ Field (\_SB.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MRBL, 32,
+ MRBH, 32,
+ MRLL, 32,
+ MRLH, 32,
+ MPX, 32
+ }
+
+ Field (\_SB.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0x14),
+ MES, 1,
+ MINS, 1,
+ MRMV, 1,
+ MEJ, 1
+ }
+
+ Field (\_SB.MHPD.HPMR, DWordAcc, NoLock, Preserve)
+ {
+ MSEL, 32,
+ MOEV, 32,
+ MOSC, 32
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Return (0x0B)
+ }
+
+ Mutex (MLCK, 0x00)
+ Method (MSCN, 0, NotSerialized)
+ {
+ If ((MDNR == Zero))
+ {
+ Return (Zero)
+ }
+
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ While ((Local0 < MDNR))
+ {
+ MSEL = Local0
+ If ((MINS == One))
+ {
+ MTFY (Local0, One)
+ MINS = One
+ }
+ ElseIf ((MRMV == One))
+ {
+ MTFY (Local0, 0x03)
+ MRMV = One
+ }
+
+ Local0 += One
+ }
+
+ Release (MLCK)
+ Return (One)
+ }
+
+ Method (MRST, 1, NotSerialized)
+ {
+ Local0 = Zero
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ If ((MES == One))
+ {
+ Local0 = 0x0F
+ }
+
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MCRS, 1, Serialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Name (MR64, ResourceTemplate ()
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000000000000000, // Range Minimum
+ 0xFFFFFFFFFFFFFFFE, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0xFFFFFFFFFFFFFFFF, // Length
+ ,, _Y00, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y00._MIN, MINL) // _MIN: Minimum Base Address
+ CreateDWordField (MR64, 0x12, MINH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y00._LEN, LENL) // _LEN: Length
+ CreateDWordField (MR64, 0x2A, LENH)
+ CreateDWordField (MR64, \_SB.MHPC.MCRS._Y00._MAX, MAXL) // _MAX: Maximum Base Address
+ CreateDWordField (MR64, 0x1A, MAXH)
+ MINH = MRBH /* \_SB_.MHPC.MRBH */
+ MINL = MRBL /* \_SB_.MHPC.MRBL */
+ LENH = MRLH /* \_SB_.MHPC.MRLH */
+ LENL = MRLL /* \_SB_.MHPC.MRLL */
+ MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */
+ MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */
+ If ((MAXL < MINL))
+ {
+ MAXH += One
+ }
+
+ If ((MAXL < One))
+ {
+ MAXH -= One
+ }
+
+ MAXL -= One
+ If ((MAXH == Zero))
+ {
+ Name (MR32, ResourceTemplate ()
+ {
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0xFFFFFFFE, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0xFFFFFFFF, // Length
+ ,, _Y01, AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y01._MIN, MIN) // _MIN: Minimum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y01._MAX, MAX) // _MAX: Maximum Base Address
+ CreateDWordField (MR32, \_SB.MHPC.MCRS._Y01._LEN, LEN) // _LEN: Length
+ MIN = MINL /* \_SB_.MHPC.MCRS.MINL */
+ MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */
+ LEN = LENL /* \_SB_.MHPC.MCRS.LENL */
+ Release (MLCK)
+ Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */
+ }
+
+ Release (MLCK)
+ Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */
+ }
+
+ Method (MPXM, 1, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ Local0 = MPX /* \_SB_.MHPC.MPX_ */
+ Release (MLCK)
+ Return (Local0)
+ }
+
+ Method (MOST, 4, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MOEV = Arg1
+ MOSC = Arg2
+ Release (MLCK)
+ }
+
+ Method (MEJ0, 2, NotSerialized)
+ {
+ Acquire (MLCK, 0xFFFF)
+ MSEL = ToInteger (Arg0)
+ MEJ = One
+ Release (MLCK)
+ }
+
+ Device (MP00)
+ {
+ Name (_UID, "0x00") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Device (MP01)
+ {
+ Name (_UID, "0x01") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Device (MP02)
+ {
+ Name (_UID, "0x02") // _UID: Unique ID
+ Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (MCRS (_UID))
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (MRST (_UID))
+ }
+
+ Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity
+ {
+ Return (MPXM (_UID))
+ }
+
+ Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication
+ {
+ MOST (_UID, Arg0, Arg1, Arg2)
+ }
+
+ Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9
+ {
+ MEJ0 (_UID, Arg0)
+ }
+ }
+
+ Method (MTFY, 2, NotSerialized)
+ {
+ If ((Arg0 == Zero))
+ {
+ Notify (MP00, Arg1)
+ }
+
+ If ((Arg0 == One))
+ {
+ Notify (MP01, Arg1)
+ }
+
+ If ((Arg0 == 0x02))
+ {
+ Notify (MP02, Arg1)
+ }
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+ }
+}
+
new file mode 100644
@@ -0,0 +1,1906 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/virt/DSDT.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x00001455 (5205)
+ * Revision 0x02
+ * Checksum 0xE1
+ * OEM ID "BOCHS "
+ * OEM Table ID "BXPCDSDT"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001)
+{
+ Scope (\_SB)
+ {
+ Device (C000)
+ {
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+
+ Device (COM0)
+ {
+ Name (_HID, "ARMH0011") // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x09000000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000021,
+ }
+ })
+ }
+
+ Device (FWCF)
+ {
+ Name (_HID, "QEMU0002") // _HID: Hardware ID
+ Name (_STA, 0x0B) // _STA: Status
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x09020000, // Address Base
+ 0x00000018, // Address Length
+ )
+ })
+ }
+
+ Device (VR00)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000000, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000030,
+ }
+ })
+ }
+
+ Device (VR01)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000200, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000031,
+ }
+ })
+ }
+
+ Device (VR02)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000400, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000032,
+ }
+ })
+ }
+
+ Device (VR03)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000600, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000033,
+ }
+ })
+ }
+
+ Device (VR04)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000800, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000034,
+ }
+ })
+ }
+
+ Device (VR05)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000A00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000035,
+ }
+ })
+ }
+
+ Device (VR06)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x06) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000C00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000036,
+ }
+ })
+ }
+
+ Device (VR07)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A000E00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000037,
+ }
+ })
+ }
+
+ Device (VR08)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x08) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001000, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000038,
+ }
+ })
+ }
+
+ Device (VR09)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x09) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001200, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000039,
+ }
+ })
+ }
+
+ Device (VR10)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0A) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001400, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003A,
+ }
+ })
+ }
+
+ Device (VR11)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0B) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001600, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003B,
+ }
+ })
+ }
+
+ Device (VR12)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0C) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001800, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003C,
+ }
+ })
+ }
+
+ Device (VR13)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0D) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001A00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003D,
+ }
+ })
+ }
+
+ Device (VR14)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0E) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001C00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003E,
+ }
+ })
+ }
+
+ Device (VR15)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x0F) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A001E00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000003F,
+ }
+ })
+ }
+
+ Device (VR16)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x10) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002000, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000040,
+ }
+ })
+ }
+
+ Device (VR17)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x11) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002200, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000041,
+ }
+ })
+ }
+
+ Device (VR18)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x12) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002400, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000042,
+ }
+ })
+ }
+
+ Device (VR19)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x13) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002600, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000043,
+ }
+ })
+ }
+
+ Device (VR20)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x14) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002800, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000044,
+ }
+ })
+ }
+
+ Device (VR21)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x15) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002A00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000045,
+ }
+ })
+ }
+
+ Device (VR22)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x16) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002C00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000046,
+ }
+ })
+ }
+
+ Device (VR23)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x17) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A002E00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000047,
+ }
+ })
+ }
+
+ Device (VR24)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x18) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003000, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000048,
+ }
+ })
+ }
+
+ Device (VR25)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x19) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003200, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000049,
+ }
+ })
+ }
+
+ Device (VR26)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1A) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003400, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004A,
+ }
+ })
+ }
+
+ Device (VR27)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1B) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003600, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004B,
+ }
+ })
+ }
+
+ Device (VR28)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1C) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003800, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004C,
+ }
+ })
+ }
+
+ Device (VR29)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1D) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003A00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004D,
+ }
+ })
+ }
+
+ Device (VR30)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1E) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003C00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004E,
+ }
+ })
+ }
+
+ Device (VR31)
+ {
+ Name (_HID, "LNRO0005") // _HID: Hardware ID
+ Name (_UID, 0x1F) // _UID: Unique ID
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadWrite,
+ 0x0A003E00, // Address Base
+ 0x00000200, // Address Length
+ )
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x0000004F,
+ }
+ })
+ }
+
+ Device (PCI0)
+ {
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID
+ Name (_SEG, Zero) // _SEG: PCI Segment
+ Name (_BBN, Zero) // _BBN: BIOS Bus Number
+ Name (_UID, "PCI0") // _UID: Unique ID
+ Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String
+ Name (_CCA, One) // _CCA: Cache Coherency Attribute
+ Name (_PRT, Package (0x80) // _PRT: PCI Routing Table
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0001FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0003FFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0004FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0005FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0006FFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0007FFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0008FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0009FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000AFFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000BFFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000CFFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000DFFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000EFFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x000FFFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0010FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0011FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0012FFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0013FFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0015FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0016FFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0017FFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0018FFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0019FFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ 0x03,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ One,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x02,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ 0x03,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ Zero,
+ GSI2,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ One,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x02,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001EFFFF,
+ 0x03,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ GSI3,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ GSI0,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ GSI1,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ GSI2,
+ Zero
+ }
+ })
+ Device (GSI0)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000023,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000023,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSI1)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000024,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000024,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSI2)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000025,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000025,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Device (GSI3)
+ {
+ Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000026,
+ }
+ })
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000026,
+ }
+ })
+ Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings
+ {
+ }
+ }
+
+ Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address
+ {
+ Return (0x0000004010000000)
+ }
+
+ Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
+ {
+ Return (ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x10000000, // Range Minimum
+ 0x3EFEFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x2EFF0000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ 0x3EFF0000, // Translation Offset
+ 0x00010000, // Length
+ ,, , TypeStatic, DenseTranslation)
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000008000000000, // Range Minimum
+ 0x000000FFFFFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000008000000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ }
+
+ Name (SUPP, Zero)
+ Name (CTRL, Zero)
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ CreateDWordField (Arg3, Zero, CDW1)
+ If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */))
+ {
+ CreateDWordField (Arg3, 0x04, CDW2)
+ CreateDWordField (Arg3, 0x08, CDW3)
+ SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */
+ CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */
+ CTRL &= 0x1F
+ If ((Arg1 != One))
+ {
+ CDW1 |= 0x08
+ }
+
+ If ((CDW3 != CTRL))
+ {
+ CDW1 |= 0x10
+ }
+
+ CDW3 = CTRL /* \_SB_.PCI0.CTRL */
+ Return (Arg3)
+ }
+ Else
+ {
+ CDW1 |= 0x04
+ Return (Arg3)
+ }
+ }
+
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */))
+ {
+ If ((Arg2 == Zero))
+ {
+ Return (Buffer (One)
+ {
+ 0x01 // .
+ })
+ }
+ }
+
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x0000000000000000, // Granularity
+ 0x0000004010000000, // Range Minimum
+ 0x000000401FFFFFFF, // Range Maximum
+ 0x0000000000000000, // Translation Offset
+ 0x0000000010000000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ }
+ }
+
+ Device (\_SB.GED)
+ {
+ Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID
+ Name (_UID, "GED") // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, )
+ {
+ 0x00000029,
+ }
+ })
+ OperationRegion (EREG, SystemMemory, 0x09080000, 0x04)
+ Field (EREG, DWordAcc, NoLock, WriteAsZeros)
+ {
+ ESEL, 32
+ }
+
+ Method (_EVT, 1, Serialized) // _EVT: Event
+ {
+ Local0 = ESEL /* \_SB_.GED_.ESEL */
+ If (((Local0 & 0x02) == 0x02))
+ {
+ Notify (PWRB, 0x80) // Status Change
+ }
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID
+ Name (_UID, Zero) // _UID: Unique ID
+ }
+ }
+}
+
new file mode 100644
@@ -0,0 +1,196 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/FACP.numamem, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 0000010C
+[008h 0008 1] Revision : 05
+[009h 0009 1] Checksum : BB
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 00
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0000
+[030h 0048 4] SMI Command Port : 00000000
+[034h 0052 1] ACPI Enable Value : 00
+[035h 0053 1] ACPI Disable Value : 00
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000000
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000000
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000000
+[050h 0080 4] GPE0 Block Address : 00000000
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 00
+[059h 0089 1] PM1 Control Block Length : 00
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 00
+[05Ch 0092 1] GPE0 Block Length : 00
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0000
+[062h 0098 2] C3 Latency : 0000
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 00
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 00100000
+ WBINVD instruction is operational (V1) : 0
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 0
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 0
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 0
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 0
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 1
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 00 [SystemMemory]
+[075h 0117 1] Bit Width : 00
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000000
+
+[080h 0128 1] Value to cause reset : 00
+[081h 0129 2] ARM Flags (decoded below) : 0003
+ PSCI Compliant : 1
+ Must use HVC for PSCI : 1
+
+[083h 0131 1] FADT Minor Revision : 01
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 00 [SystemMemory]
+[095h 0149 1] Bit Width : 00
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000000
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 00 [SystemMemory]
+[0ADh 0173 1] Bit Width : 00
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000000
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 00 [SystemMemory]
+[0D1h 0209 1] Bit Width : 00
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000000
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 00 [SystemMemory]
+[0DDh 0221 1] Bit Width : 00
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000000
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+[0F4h 0244 12] Sleep Control Register : [Generic Address Structure]
+[0F4h 0244 1] Space ID : 00 [SystemMemory]
+[0F5h 0245 1] Bit Width : 00
+[0F6h 0246 1] Bit Offset : 00
+[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0F8h 0248 8] Address : 0000000000000000
+
+[100h 0256 12] Sleep Status Register : [Generic Address Structure]
+[100h 0256 1] Space ID : 00 [SystemMemory]
+[101h 0257 1] Bit Width : 00
+[102h 0258 1] Bit Offset : 00
+[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
+[104h 0260 8] Address : 0000000000000000
+
+/**** ACPI table terminates in the middle of a data structure! (dump table) */
+
+Raw Table Data: Length 268 (0x10C)
+
+ 0000: 46 41 43 50 0C 01 00 00 05 BB 42 4F 43 48 53 20 // FACP......BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............
new file mode 100644
@@ -0,0 +1,196 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/FACP.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 0000010C
+[008h 0008 1] Revision : 05
+[009h 0009 1] Checksum : BB
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 00
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0000
+[030h 0048 4] SMI Command Port : 00000000
+[034h 0052 1] ACPI Enable Value : 00
+[035h 0053 1] ACPI Disable Value : 00
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000000
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000000
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000000
+[050h 0080 4] GPE0 Block Address : 00000000
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 00
+[059h 0089 1] PM1 Control Block Length : 00
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 00
+[05Ch 0092 1] GPE0 Block Length : 00
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0000
+[062h 0098 2] C3 Latency : 0000
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 00
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 00100000
+ WBINVD instruction is operational (V1) : 0
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 0
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 0
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 0
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 0
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 1
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 00 [SystemMemory]
+[075h 0117 1] Bit Width : 00
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000000
+
+[080h 0128 1] Value to cause reset : 00
+[081h 0129 2] ARM Flags (decoded below) : 0003
+ PSCI Compliant : 1
+ Must use HVC for PSCI : 1
+
+[083h 0131 1] FADT Minor Revision : 01
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 00 [SystemMemory]
+[095h 0149 1] Bit Width : 00
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000000
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 00 [SystemMemory]
+[0ADh 0173 1] Bit Width : 00
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000000
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 00 [SystemMemory]
+[0D1h 0209 1] Bit Width : 00
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000000
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 00 [SystemMemory]
+[0DDh 0221 1] Bit Width : 00
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000000
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+[0F4h 0244 12] Sleep Control Register : [Generic Address Structure]
+[0F4h 0244 1] Space ID : 00 [SystemMemory]
+[0F5h 0245 1] Bit Width : 00
+[0F6h 0246 1] Bit Offset : 00
+[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0F8h 0248 8] Address : 0000000000000000
+
+[100h 0256 12] Sleep Status Register : [Generic Address Structure]
+[100h 0256 1] Space ID : 00 [SystemMemory]
+[101h 0257 1] Bit Width : 00
+[102h 0258 1] Bit Offset : 00
+[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
+[104h 0260 8] Address : 0000000000000000
+
+/**** ACPI table terminates in the middle of a data structure! (dump table) */
+
+Raw Table Data: Length 268 (0x10C)
+
+ 0000: 46 41 43 50 0C 01 00 00 05 BB 42 4F 43 48 53 20 // FACP......BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............
new file mode 100644
@@ -0,0 +1,196 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/FACP.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 0000010C
+[008h 0008 1] Revision : 05
+[009h 0009 1] Checksum : BB
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCFACP"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] FACS Address : 00000000
+[028h 0040 4] DSDT Address : 00000000
+[02Ch 0044 1] Model : 00
+[02Dh 0045 1] PM Profile : 00 [Unspecified]
+[02Eh 0046 2] SCI Interrupt : 0000
+[030h 0048 4] SMI Command Port : 00000000
+[034h 0052 1] ACPI Enable Value : 00
+[035h 0053 1] ACPI Disable Value : 00
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000000
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000000
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000000
+[04Ch 0076 4] PM Timer Block Address : 00000000
+[050h 0080 4] GPE0 Block Address : 00000000
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 00
+[059h 0089 1] PM1 Control Block Length : 00
+[05Ah 0090 1] PM2 Control Block Length : 00
+[05Bh 0091 1] PM Timer Block Length : 00
+[05Ch 0092 1] GPE0 Block Length : 00
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0000
+[062h 0098 2] C3 Latency : 0000
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 00
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 00
+[06Dh 0109 2] Boot Flags (decoded below) : 0000
+ Legacy Devices Supported (V2) : 0
+ 8042 Present on ports 60/64 (V2) : 0
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 00100000
+ WBINVD instruction is operational (V1) : 0
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 0
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 0
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 0
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 0
+ Sealed Case (V3) : 0
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 0
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 1
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 00 [SystemMemory]
+[075h 0117 1] Bit Width : 00
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[078h 0120 8] Address : 0000000000000000
+
+[080h 0128 1] Value to cause reset : 00
+[081h 0129 2] ARM Flags (decoded below) : 0003
+ PSCI Compliant : 1
+ Must use HVC for PSCI : 1
+
+[083h 0131 1] FADT Minor Revision : 01
+[084h 0132 8] FACS Address : 0000000000000000
+[08Ch 0140 8] DSDT Address : 0000000000000000
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 00 [SystemMemory]
+[095h 0149 1] Bit Width : 00
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[098h 0152 8] Address : 0000000000000000
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 00 [SystemMemory]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 00 [SystemMemory]
+[0ADh 0173 1] Bit Width : 00
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0B0h 0176 8] Address : 0000000000000000
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 00 [SystemMemory]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 00 [SystemMemory]
+[0C5h 0197 1] Bit Width : 00
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C8h 0200 8] Address : 0000000000000000
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 00 [SystemMemory]
+[0D1h 0209 1] Bit Width : 00
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D4h 0212 8] Address : 0000000000000000
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 00 [SystemMemory]
+[0DDh 0221 1] Bit Width : 00
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0E0h 0224 8] Address : 0000000000000000
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 00 [SystemMemory]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+[0F4h 0244 12] Sleep Control Register : [Generic Address Structure]
+[0F4h 0244 1] Space ID : 00 [SystemMemory]
+[0F5h 0245 1] Bit Width : 00
+[0F6h 0246 1] Bit Offset : 00
+[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0F8h 0248 8] Address : 0000000000000000
+
+[100h 0256 12] Sleep Status Register : [Generic Address Structure]
+[100h 0256 1] Space ID : 00 [SystemMemory]
+[101h 0257 1] Bit Width : 00
+[102h 0258 1] Bit Offset : 00
+[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy]
+[104h 0260 8] Address : 0000000000000000
+
+/**** ACPI table terminates in the middle of a data structure! (dump table) */
+
+Raw Table Data: Length 268 (0x10C)
+
+ 0000: 46 41 43 50 0C 01 00 00 05 BB 42 4F 43 48 53 20 // FACP......BOCHS
+ 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............
new file mode 100644
@@ -0,0 +1,61 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/GTDT.numamem, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [GTDT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table]
+[004h 0004 4] Table Length : 00000060
+[008h 0008 1] Revision : 02
+[009h 0009 1] Checksum : D9
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCGTDT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Counter Block Address : 0000000000000000
+[02Ch 0044 4] Reserved : 00000000
+
+[030h 0048 4] Secure EL1 Interrupt : 0000001D
+[034h 0052 4] EL1 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 0
+
+[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E
+[03Ch 0060 4] NEL1 Flags (decoded below) : 00000004
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 1
+
+[040h 0064 4] Virtual Timer Interrupt : 0000001B
+[044h 0068 4] VT Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 0
+
+[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A
+[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 0
+[050h 0080 8] Counter Read Block Address : 0000000000000000
+
+[058h 0088 4] Platform Timer Count : 00000000
+[05Ch 0092 4] Platform Timer Offset : 00000000
+
+Raw Table Data: Length 96 (0x60)
+
+ 0000: 47 54 44 54 60 00 00 00 02 D9 42 4F 43 48 53 20 // GTDT`.....BOCHS
+ 0010: 42 58 50 43 47 54 44 54 01 00 00 00 42 58 50 43 // BXPCGTDT....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................
+ 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,61 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/GTDT.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [GTDT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table]
+[004h 0004 4] Table Length : 00000060
+[008h 0008 1] Revision : 02
+[009h 0009 1] Checksum : D9
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCGTDT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Counter Block Address : 0000000000000000
+[02Ch 0044 4] Reserved : 00000000
+
+[030h 0048 4] Secure EL1 Interrupt : 0000001D
+[034h 0052 4] EL1 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 0
+
+[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E
+[03Ch 0060 4] NEL1 Flags (decoded below) : 00000004
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 1
+
+[040h 0064 4] Virtual Timer Interrupt : 0000001B
+[044h 0068 4] VT Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 0
+
+[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A
+[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 0
+[050h 0080 8] Counter Read Block Address : 0000000000000000
+
+[058h 0088 4] Platform Timer Count : 00000000
+[05Ch 0092 4] Platform Timer Offset : 00000000
+
+Raw Table Data: Length 96 (0x60)
+
+ 0000: 47 54 44 54 60 00 00 00 02 D9 42 4F 43 48 53 20 // GTDT`.....BOCHS
+ 0010: 42 58 50 43 47 54 44 54 01 00 00 00 42 58 50 43 // BXPCGTDT....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................
+ 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,61 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/GTDT.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [GTDT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table]
+[004h 0004 4] Table Length : 00000060
+[008h 0008 1] Revision : 02
+[009h 0009 1] Checksum : D9
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCGTDT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Counter Block Address : 0000000000000000
+[02Ch 0044 4] Reserved : 00000000
+
+[030h 0048 4] Secure EL1 Interrupt : 0000001D
+[034h 0052 4] EL1 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 0
+
+[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E
+[03Ch 0060 4] NEL1 Flags (decoded below) : 00000004
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 1
+
+[040h 0064 4] Virtual Timer Interrupt : 0000001B
+[044h 0068 4] VT Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 0
+
+[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A
+[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000
+ Trigger Mode : 0
+ Polarity : 0
+ Always On : 0
+[050h 0080 8] Counter Read Block Address : 0000000000000000
+
+[058h 0088 4] Platform Timer Count : 00000000
+[05Ch 0092 4] Platform Timer Offset : 00000000
+
+Raw Table Data: Length 96 (0x60)
+
+ 0000: 47 54 44 54 60 00 00 00 02 D9 42 4F 43 48 53 20 // GTDT`.....BOCHS
+ 0010: 42 58 50 43 47 54 44 54 01 00 00 00 42 58 50 43 // BXPCGTDT....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................
+ 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................
+ 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,36 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/MCFG.numamem, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [MCFG]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table]
+[004h 0004 4] Table Length : 0000003C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 4F
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCMCFG"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Reserved : 0000000000000000
+
+[02Ch 0044 8] Base Address : 0000004010000000
+[034h 0052 2] Segment Group Number : 0000
+[036h 0054 1] Start Bus Number : 00
+[037h 0055 1] End Bus Number : FF
+[038h 0056 4] Reserved : 00000000
+
+Raw Table Data: Length 60 (0x3C)
+
+ 0000: 4D 43 46 47 3C 00 00 00 01 4F 42 4F 43 48 53 20 // MCFG<....OBOCHS
+ 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 // ................
+ 0030: 40 00 00 00 00 00 00 FF 00 00 00 00 // @...........
new file mode 100644
@@ -0,0 +1,36 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/MCFG.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [MCFG]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table]
+[004h 0004 4] Table Length : 0000003C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 4F
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCMCFG"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Reserved : 0000000000000000
+
+[02Ch 0044 8] Base Address : 0000004010000000
+[034h 0052 2] Segment Group Number : 0000
+[036h 0054 1] Start Bus Number : 00
+[037h 0055 1] End Bus Number : FF
+[038h 0056 4] Reserved : 00000000
+
+Raw Table Data: Length 60 (0x3C)
+
+ 0000: 4D 43 46 47 3C 00 00 00 01 4F 42 4F 43 48 53 20 // MCFG<....OBOCHS
+ 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 // ................
+ 0030: 40 00 00 00 00 00 00 FF 00 00 00 00 // @...........
new file mode 100644
@@ -0,0 +1,36 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/MCFG.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [MCFG]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table]
+[004h 0004 4] Table Length : 0000003C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 4F
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCMCFG"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Reserved : 0000000000000000
+
+[02Ch 0044 8] Base Address : 0000004010000000
+[034h 0052 2] Segment Group Number : 0000
+[036h 0054 1] Start Bus Number : 00
+[037h 0055 1] End Bus Number : FF
+[038h 0056 4] Reserved : 00000000
+
+Raw Table Data: Length 60 (0x3C)
+
+ 0000: 4D 43 46 47 3C 00 00 00 01 4F 42 4F 43 48 53 20 // MCFG<....OBOCHS
+ 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 // ................
+ 0030: 40 00 00 00 00 00 00 FF 00 00 00 00 // @...........
new file mode 100644
@@ -0,0 +1,103 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/NFIT.memhp, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [NFIT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table]
+[004h 0004 4] Table Length : 000000E0
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : D1
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCNFIT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Reserved : 00000000
+
+[028h 0040 2] Subtable Type : 0000 [System Physical Address Range]
+[02Ah 0042 2] Length : 0038
+
+[02Ch 0044 2] Range Index : 0004
+[02Eh 0046 2] Flags (decoded below) : 0003
+ Add/Online Operation Only : 1
+ Proximity Domain Valid : 1
+[030h 0048 4] Reserved : 00000000
+[034h 0052 4] Proximity Domain : 00000001
+[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB
+[048h 0072 8] Address Range Base : 0000000088000000
+[050h 0080 8] Address Range Length : 0000000008000000
+[058h 0088 8] Memory Map Attribute : 0000000000008008
+
+[060h 0096 2] Subtable Type : 0001 [Memory Range Map]
+[062h 0098 2] Length : 0030
+
+[064h 0100 4] Device Handle : 00000002
+[068h 0104 2] Physical Id : 0000
+[06Ah 0106 2] Region Id : 0000
+[06Ch 0108 2] Range Index : 0004
+[06Eh 0110 2] Control Region Index : 0005
+[070h 0112 8] Region Size : 0000000008000000
+[078h 0120 8] Region Offset : 0000000000000000
+[080h 0128 8] Address Region Base : 0000000000000000
+[088h 0136 2] Interleave Index : 0000
+[08Ah 0138 2] Interleave Ways : 0001
+[08Ch 0140 2] Flags : 0000
+ Save to device failed : 0
+ Restore from device failed : 0
+ Platform flush failed : 0
+ Device not armed : 0
+ Health events observed : 0
+ Health events enabled : 0
+ Mapping failed : 0
+[08Eh 0142 2] Reserved : 0000
+
+[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region]
+[092h 0146 2] Length : 0050
+
+[094h 0148 2] Region Index : 0005
+[096h 0150 2] Vendor Id : 8086
+[098h 0152 2] Device Id : 0001
+[09Ah 0154 2] Revision Id : 0001
+[09Ch 0156 2] Subsystem Vendor Id : 0000
+[09Eh 0158 2] Subsystem Device Id : 0000
+[0A0h 0160 2] Subsystem Revision Id : 0000
+[0A2h 0162 1] Valid Fields : 00
+[0A3h 0163 1] Manufacturing Location : 00
+[0A4h 0164 2] Manufacturing Date : 0000
+[0A6h 0166 2] Reserved : 0000
+[0A8h 0168 4] Serial Number : 00123457
+[0ACh 0172 2] Code : 0301
+[0AEh 0174 2] Window Count : 0000
+[0B0h 0176 8] Window Size : 0000000000000000
+[0B8h 0184 8] Command Offset : 0000000000000000
+[0C0h 0192 8] Command Size : 0000000000000000
+[0C8h 0200 8] Status Offset : 0000000000000000
+[0D0h 0208 8] Status Size : 0000000000000000
+[0D8h 0216 2] Flags : 0000
+ Windows buffered : 0
+[0DAh 0218 6] Reserved1 : 000000000000
+
+Raw Table Data: Length 224 (0xE0)
+
+ 0000: 4E 46 49 54 E0 00 00 00 01 D1 42 4F 43 48 53 20 // NFIT......BOCHS
+ 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8.....
+ 0030: 00 00 00 00 01 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@
+ 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 88 00 00 00 00 // .C.3............
+ 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................
+ 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0.............
+ 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................
+ 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P.............
+ 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4......
+ 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,103 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/NFIT.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [NFIT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table]
+[004h 0004 4] Table Length : 000000E0
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : D1
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCNFIT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Reserved : 00000000
+
+[028h 0040 2] Subtable Type : 0000 [System Physical Address Range]
+[02Ah 0042 2] Length : 0038
+
+[02Ch 0044 2] Range Index : 0004
+[02Eh 0046 2] Flags (decoded below) : 0003
+ Add/Online Operation Only : 1
+ Proximity Domain Valid : 1
+[030h 0048 4] Reserved : 00000000
+[034h 0052 4] Proximity Domain : 00000001
+[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB
+[048h 0072 8] Address Range Base : 0000000088000000
+[050h 0080 8] Address Range Length : 0000000008000000
+[058h 0088 8] Memory Map Attribute : 0000000000008008
+
+[060h 0096 2] Subtable Type : 0001 [Memory Range Map]
+[062h 0098 2] Length : 0030
+
+[064h 0100 4] Device Handle : 00000002
+[068h 0104 2] Physical Id : 0000
+[06Ah 0106 2] Region Id : 0000
+[06Ch 0108 2] Range Index : 0004
+[06Eh 0110 2] Control Region Index : 0005
+[070h 0112 8] Region Size : 0000000008000000
+[078h 0120 8] Region Offset : 0000000000000000
+[080h 0128 8] Address Region Base : 0000000000000000
+[088h 0136 2] Interleave Index : 0000
+[08Ah 0138 2] Interleave Ways : 0001
+[08Ch 0140 2] Flags : 0000
+ Save to device failed : 0
+ Restore from device failed : 0
+ Platform flush failed : 0
+ Device not armed : 0
+ Health events observed : 0
+ Health events enabled : 0
+ Mapping failed : 0
+[08Eh 0142 2] Reserved : 0000
+
+[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region]
+[092h 0146 2] Length : 0050
+
+[094h 0148 2] Region Index : 0005
+[096h 0150 2] Vendor Id : 8086
+[098h 0152 2] Device Id : 0001
+[09Ah 0154 2] Revision Id : 0001
+[09Ch 0156 2] Subsystem Vendor Id : 0000
+[09Eh 0158 2] Subsystem Device Id : 0000
+[0A0h 0160 2] Subsystem Revision Id : 0000
+[0A2h 0162 1] Valid Fields : 00
+[0A3h 0163 1] Manufacturing Location : 00
+[0A4h 0164 2] Manufacturing Date : 0000
+[0A6h 0166 2] Reserved : 0000
+[0A8h 0168 4] Serial Number : 00123457
+[0ACh 0172 2] Code : 0301
+[0AEh 0174 2] Window Count : 0000
+[0B0h 0176 8] Window Size : 0000000000000000
+[0B8h 0184 8] Command Offset : 0000000000000000
+[0C0h 0192 8] Command Size : 0000000000000000
+[0C8h 0200 8] Status Offset : 0000000000000000
+[0D0h 0208 8] Status Size : 0000000000000000
+[0D8h 0216 2] Flags : 0000
+ Windows buffered : 0
+[0DAh 0218 6] Reserved1 : 000000000000
+
+Raw Table Data: Length 224 (0xE0)
+
+ 0000: 4E 46 49 54 E0 00 00 00 01 D1 42 4F 43 48 53 20 // NFIT......BOCHS
+ 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC
+ 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8.....
+ 0030: 00 00 00 00 01 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@
+ 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 88 00 00 00 00 // .C.3............
+ 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................
+ 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0.............
+ 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................
+ 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P.............
+ 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4......
+ 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/SLIT.memhp, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [SLIT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SLIT" [System Locality Information Table]
+[004h 0004 4] Table Length : 00000030
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 2C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSLIT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Localities : 0000000000000002
+[02Ch 0044 2] Locality 0 : 0A 15
+[02Eh 0046 2] Locality 1 : 15 0A
+
+Raw Table Data: Length 48 (0x30)
+
+ 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS
+ 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC
+ 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................
new file mode 100644
@@ -0,0 +1,31 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/SLIT.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SLIT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SLIT" [System Locality Information Table]
+[004h 0004 4] Table Length : 00000030
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 2C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSLIT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 8] Localities : 0000000000000002
+[02Ch 0044 2] Locality 0 : 0A 15
+[02Eh 0046 2] Locality 1 : 15 0A
+
+Raw Table Data: Length 48 (0x30)
+
+ 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS
+ 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC
+ 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................
new file mode 100644
@@ -0,0 +1,57 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/SPCR.numamem, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [SPCR]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table]
+[004h 0004 4] Table Length : 00000050
+[008h 0008 1] Revision : 02
+[009h 0009 1] Checksum : 13
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSPCR"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 1] Interface Type : 03
+[025h 0037 3] Reserved : 000000
+
+[028h 0040 12] Serial Port Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 08
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8]
+[02Ch 0044 8] Address : 0000000009000000
+
+[034h 0052 1] Interrupt Type : 08
+[035h 0053 1] PCAT-compatible IRQ : 00
+[036h 0054 4] Interrupt : 00000021
+[03Ah 0058 1] Baud Rate : 03
+[03Bh 0059 1] Parity : 00
+[03Ch 0060 1] Stop Bits : 01
+[03Dh 0061 1] Flow Control : 02
+[03Eh 0062 1] Terminal Type : 00
+[04Ch 0076 1] Reserved : 00
+[040h 0064 2] PCI Device ID : FFFF
+[042h 0066 2] PCI Vendor ID : FFFF
+[044h 0068 1] PCI Bus : 00
+[045h 0069 1] PCI Device : 00
+[046h 0070 1] PCI Function : 00
+[047h 0071 4] PCI Flags : 00000000
+[04Bh 0075 1] PCI Segment : 00
+[04Ch 0076 4] Reserved : 00000000
+
+Raw Table Data: Length 80 (0x50)
+
+ 0000: 53 50 43 52 50 00 00 00 02 13 42 4F 43 48 53 20 // SPCRP.....BOCHS
+ 0010: 42 58 50 43 53 50 43 52 01 00 00 00 42 58 50 43 // BXPCSPCR....BXPC
+ 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................
+ 0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!.........
+ 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,57 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/SPCR.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SPCR]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table]
+[004h 0004 4] Table Length : 00000050
+[008h 0008 1] Revision : 02
+[009h 0009 1] Checksum : 13
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSPCR"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 1] Interface Type : 03
+[025h 0037 3] Reserved : 000000
+
+[028h 0040 12] Serial Port Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 08
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8]
+[02Ch 0044 8] Address : 0000000009000000
+
+[034h 0052 1] Interrupt Type : 08
+[035h 0053 1] PCAT-compatible IRQ : 00
+[036h 0054 4] Interrupt : 00000021
+[03Ah 0058 1] Baud Rate : 03
+[03Bh 0059 1] Parity : 00
+[03Ch 0060 1] Stop Bits : 01
+[03Dh 0061 1] Flow Control : 02
+[03Eh 0062 1] Terminal Type : 00
+[04Ch 0076 1] Reserved : 00
+[040h 0064 2] PCI Device ID : FFFF
+[042h 0066 2] PCI Vendor ID : FFFF
+[044h 0068 1] PCI Bus : 00
+[045h 0069 1] PCI Device : 00
+[046h 0070 1] PCI Function : 00
+[047h 0071 4] PCI Flags : 00000000
+[04Bh 0075 1] PCI Segment : 00
+[04Ch 0076 4] Reserved : 00000000
+
+Raw Table Data: Length 80 (0x50)
+
+ 0000: 53 50 43 52 50 00 00 00 02 13 42 4F 43 48 53 20 // SPCRP.....BOCHS
+ 0010: 42 58 50 43 53 50 43 52 01 00 00 00 42 58 50 43 // BXPCSPCR....BXPC
+ 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................
+ 0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!.........
+ 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,57 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/SPCR.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SPCR]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table]
+[004h 0004 4] Table Length : 00000050
+[008h 0008 1] Revision : 02
+[009h 0009 1] Checksum : 13
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSPCR"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 1] Interface Type : 03
+[025h 0037 3] Reserved : 000000
+
+[028h 0040 12] Serial Port Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 08
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8]
+[02Ch 0044 8] Address : 0000000009000000
+
+[034h 0052 1] Interrupt Type : 08
+[035h 0053 1] PCAT-compatible IRQ : 00
+[036h 0054 4] Interrupt : 00000021
+[03Ah 0058 1] Baud Rate : 03
+[03Bh 0059 1] Parity : 00
+[03Ch 0060 1] Stop Bits : 01
+[03Dh 0061 1] Flow Control : 02
+[03Eh 0062 1] Terminal Type : 00
+[04Ch 0076 1] Reserved : 00
+[040h 0064 2] PCI Device ID : FFFF
+[042h 0066 2] PCI Vendor ID : FFFF
+[044h 0068 1] PCI Bus : 00
+[045h 0069 1] PCI Device : 00
+[046h 0070 1] PCI Function : 00
+[047h 0071 4] PCI Flags : 00000000
+[04Bh 0075 1] PCI Segment : 00
+[04Ch 0076 4] Reserved : 00000000
+
+Raw Table Data: Length 80 (0x50)
+
+ 0000: 53 50 43 52 50 00 00 00 02 13 42 4F 43 48 53 20 // SPCRP.....BOCHS
+ 0010: 42 58 50 43 53 50 43 52 01 00 00 00 42 58 50 43 // BXPCSPCR....BXPC
+ 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................
+ 0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!.........
+ 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................
new file mode 100644
@@ -0,0 +1,57 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/SRAT.numamem, Mon Sep 28 17:24:38 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 0000006A
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : AB
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 03 [GICC Affinity]
+[031h 0049 1] Length : 12
+
+[032h 0050 4] Proximity Domain : 00000000
+[036h 0054 4] Acpi Processor UID : 00000000
+[03Ah 0058 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[03Eh 0062 4] Clock Domain : 00000000
+
+[042h 0066 1] Subtable Type : 01 [Memory Affinity]
+[043h 0067 1] Length : 28
+
+[044h 0068 4] Proximity Domain : 00000000
+[048h 0072 2] Reserved1 : 0000
+[04Ah 0074 8] Base Address : 0000000040000000
+[052h 0082 8] Address Length : 0000000008000000
+[05Ah 0090 4] Reserved2 : 00000000
+[05Eh 0094 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[062h 0098 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 106 (0x6A)
+
+ 0000: 53 52 41 54 6A 00 00 00 03 AB 42 4F 43 48 53 20 // SRATj.....BOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 03 12 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................
+ 0040: 00 00 01 28 00 00 00 00 00 00 00 00 00 40 00 00 // ...(.........@..
+ 0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 00 00 // ..........
new file mode 100644
@@ -0,0 +1,107 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/SRAT.memhp, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 000000E2
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : 5C
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 03 [GICC Affinity]
+[031h 0049 1] Length : 12
+
+[032h 0050 4] Proximity Domain : 00000000
+[036h 0054 4] Acpi Processor UID : 00000000
+[03Ah 0058 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[03Eh 0062 4] Clock Domain : 00000000
+
+[042h 0066 1] Subtable Type : 01 [Memory Affinity]
+[043h 0067 1] Length : 28
+
+[044h 0068 4] Proximity Domain : 00000000
+[048h 0072 2] Reserved1 : 0000
+[04Ah 0074 8] Base Address : 0000000040000000
+[052h 0082 8] Address Length : 0000000008000000
+[05Ah 0090 4] Reserved2 : 00000000
+[05Eh 0094 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[062h 0098 8] Reserved3 : 0000000000000000
+
+[06Ah 0106 1] Subtable Type : 01 [Memory Affinity]
+[06Bh 0107 1] Length : 28
+
+[06Ch 0108 4] Proximity Domain : 00000001
+[070h 0112 2] Reserved1 : 0000
+[072h 0114 8] Base Address : 0000000048000000
+[07Ah 0122 8] Address Length : 0000000008000000
+[082h 0130 4] Reserved2 : 00000000
+[086h 0134 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[08Ah 0138 8] Reserved3 : 0000000000000000
+
+[092h 0146 1] Subtable Type : 01 [Memory Affinity]
+[093h 0147 1] Length : 28
+
+[094h 0148 4] Proximity Domain : 00000001
+[098h 0152 2] Reserved1 : 0000
+[09Ah 0154 8] Base Address : 0000000088000000
+[0A2h 0162 8] Address Length : 0000000008000000
+[0AAh 0170 4] Reserved2 : 00000000
+[0AEh 0174 4] Flags (decoded below) : 00000005
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 1
+[0B2h 0178 8] Reserved3 : 0000000000000000
+
+[0BAh 0186 1] Subtable Type : 01 [Memory Affinity]
+[0BBh 0187 1] Length : 28
+
+[0BCh 0188 4] Proximity Domain : 00000001
+[0C0h 0192 2] Reserved1 : 0000
+[0C2h 0194 8] Base Address : 0000000080000000
+[0CAh 0202 8] Address Length : 00000000F0000000
+[0D2h 0210 4] Reserved2 : 00000000
+[0D6h 0214 4] Flags (decoded below) : 00000003
+ Enabled : 1
+ Hot Pluggable : 1
+ Non-Volatile : 0
+[0DAh 0218 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 226 (0xE2)
+
+ 0000: 53 52 41 54 E2 00 00 00 03 5C 42 4F 43 48 53 20 // SRAT.....\BOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 03 12 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................
+ 0040: 00 00 01 28 00 00 00 00 00 00 00 00 00 40 00 00 // ...(.........@..
+ 0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 00 00 01 28 01 00 00 00 // ...........(....
+ 0070: 00 00 00 00 00 48 00 00 00 00 00 00 00 08 00 00 // .....H..........
+ 0080: 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 // ................
+ 0090: 00 00 01 28 01 00 00 00 00 00 00 00 00 88 00 00 // ...(............
+ 00A0: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 05 00 // ................
+ 00B0: 00 00 00 00 00 00 00 00 00 00 01 28 01 00 00 00 // ...........(....
+ 00C0: 00 00 00 00 00 80 00 00 00 00 00 00 00 F0 00 00 // ................
+ 00D0: 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 // ................
+ 00E0: 00 00 // ..
new file mode 100644
@@ -0,0 +1,57 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembly of tests/data/acpi/virt/SRAT.numamem, Tue Aug 4 11:14:15 2020
+ *
+ * ACPI Data Table [SRAT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table]
+[004h 0004 4] Table Length : 0000006A
+[008h 0008 1] Revision : 03
+[009h 0009 1] Checksum : AB
+[00Ah 0010 6] Oem ID : "BOCHS "
+[010h 0016 8] Oem Table ID : "BXPCSRAT"
+[018h 0024 4] Oem Revision : 00000001
+[01Ch 0028 4] Asl Compiler ID : "BXPC"
+[020h 0032 4] Asl Compiler Revision : 00000001
+
+[024h 0036 4] Table Revision : 00000001
+[028h 0040 8] Reserved : 0000000000000000
+
+[030h 0048 1] Subtable Type : 03 [GICC Affinity]
+[031h 0049 1] Length : 12
+
+[032h 0050 4] Proximity Domain : 00000000
+[036h 0054 4] Acpi Processor UID : 00000000
+[03Ah 0058 4] Flags (decoded below) : 00000001
+ Enabled : 1
+[03Eh 0062 4] Clock Domain : 00000000
+
+[042h 0066 1] Subtable Type : 01 [Memory Affinity]
+[043h 0067 1] Length : 28
+
+[044h 0068 4] Proximity Domain : 00000000
+[048h 0072 2] Reserved1 : 0000
+[04Ah 0074 8] Base Address : 0000000040000000
+[052h 0082 8] Address Length : 0000000008000000
+[05Ah 0090 4] Reserved2 : 00000000
+[05Eh 0094 4] Flags (decoded below) : 00000001
+ Enabled : 1
+ Hot Pluggable : 0
+ Non-Volatile : 0
+[062h 0098 8] Reserved3 : 0000000000000000
+
+Raw Table Data: Length 106 (0x6A)
+
+ 0000: 53 52 41 54 6A 00 00 00 03 AB 42 4F 43 48 53 20 // SRATj.....BOCHS
+ 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC
+ 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................
+ 0030: 03 12 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................
+ 0040: 00 00 01 28 00 00 00 00 00 00 00 00 00 40 00 00 // ...(.........@..
+ 0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00 // ................
+ 0060: 00 00 00 00 00 00 00 00 00 00 // ..........
new file mode 100644
@@ -0,0 +1,205 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler version 20190509 (64-bit version)
+ * Copyright (c) 2000 - 2019 Intel Corporation
+ *
+ * Disassembling to symbolic ASL+ operators
+ *
+ * Disassembly of tests/data/acpi/virt/SSDT.memhp, Mon Sep 28 17:24:38 2020
+ *
+ * Original Table Header:
+ * Signature "SSDT"
+ * Length 0x000002E0 (736)
+ * Revision 0x01
+ * Checksum 0x3F
+ * OEM ID "BOCHS "
+ * OEM Table ID "NVDIMM"
+ * OEM Revision 0x00000001 (1)
+ * Compiler ID "BXPC"
+ * Compiler Version 0x00000001 (1)
+ */
+DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001)
+{
+ Scope (\_SB)
+ {
+ Device (NVDR)
+ {
+ Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Hardware ID
+ Method (NCAL, 5, Serialized)
+ {
+ Local6 = MEMA /* \MEMA */
+ OperationRegion (NPIO, SystemMemory, 0x09090000, 0x04)
+ OperationRegion (NRAM, SystemMemory, Local6, 0x1000)
+ Field (NPIO, DWordAcc, NoLock, Preserve)
+ {
+ NTFI, 32
+ }
+
+ Field (NRAM, DWordAcc, NoLock, Preserve)
+ {
+ HDLE, 32,
+ REVS, 32,
+ FUNC, 32,
+ FARG, 32672
+ }
+
+ Field (NRAM, DWordAcc, NoLock, Preserve)
+ {
+ RLEN, 32,
+ ODAT, 32736
+ }
+
+ If ((Arg4 == Zero))
+ {
+ Local0 = ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75cba")
+ }
+ ElseIf ((Arg4 == 0x00010000))
+ {
+ Local0 = ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62")
+ }
+ Else
+ {
+ Local0 = ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66")
+ }
+
+ If (((Local6 == Zero) | (Arg0 != Local0)))
+ {
+ If ((Arg2 == Zero))
+ {
+ Return (Buffer (One)
+ {
+ 0x00 // .
+ })
+ }
+
+ Return (Buffer (One)
+ {
+ 0x01 // .
+ })
+ }
+
+ HDLE = Arg4
+ REVS = Arg1
+ FUNC = Arg2
+ If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One)))
+ {
+ Local2 = Arg3 [Zero]
+ Local3 = DerefOf (Local2)
+ FARG = Local3
+ }
+
+ NTFI = Local6
+ Local1 = (RLEN - 0x04)
+ If ((Local1 < 0x08))
+ {
+ Local2 = Zero
+ Name (TBUF, Buffer (One)
+ {
+ 0x00 // .
+ })
+ Local7 = Buffer (Zero){}
+ While ((Local2 < Local1))
+ {
+ TBUF [Zero] = DerefOf (ODAT [Local2])
+ Concatenate (Local7, TBUF, Local7)
+ Local2++
+ }
+
+ Return (Local7)
+ }
+
+ Local1 = (Local1 << 0x03)
+ CreateField (ODAT, Zero, Local1, OBUF)
+ Return (OBUF) /* \_SB_.NVDR.NCAL.OBUF */
+ }
+
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ Return (NCAL (Arg0, Arg1, Arg2, Arg3, Zero))
+ }
+
+ Name (RSTA, Zero)
+ Method (RFIT, 1, Serialized)
+ {
+ Name (OFST, Zero)
+ OFST = Arg0
+ Local0 = NCAL (ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62"), One, One, Package (0x01)
+ {
+ OFST
+ }, 0x00010000)
+ CreateDWordField (Local0, Zero, STAU)
+ RSTA = STAU /* \_SB_.NVDR.RFIT.STAU */
+ If ((Zero != STAU))
+ {
+ Return (Buffer (Zero){})
+ }
+
+ Local1 = SizeOf (Local0)
+ Local1 -= 0x04
+ If ((Local1 == Zero))
+ {
+ Return (Buffer (Zero){})
+ }
+
+ CreateField (Local0, 0x20, (Local1 << 0x03), BUFF)
+ Return (BUFF) /* \_SB_.NVDR.RFIT.BUFF */
+ }
+
+ Method (_FIT, 0, Serialized) // _FIT: Firmware Interface Table
+ {
+ Local2 = Buffer (Zero){}
+ Local3 = Zero
+ While (One)
+ {
+ Local0 = RFIT (Local3)
+ Local1 = SizeOf (Local0)
+ If ((RSTA == 0x0100))
+ {
+ Local2 = Buffer (Zero){}
+ Local3 = Zero
+ }
+ Else
+ {
+ If ((Local1 == Zero))
+ {
+ Return (Local2)
+ }
+
+ Local3 += Local1
+ Concatenate (Local2, Local0, Local2)
+ }
+ }
+ }
+
+ Device (NV00)
+ {
+ Name (_ADR, One) // _ADR: Address
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ Return (NCAL (Arg0, Arg1, Arg2, Arg3, One))
+ }
+ }
+
+ Device (NV01)
+ {
+ Name (_ADR, 0x02) // _ADR: Address
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x02))
+ }
+ }
+
+ Device (NV02)
+ {
+ Name (_ADR, 0x03) // _ADR: Address
+ Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method
+ {
+ Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x03))
+ }
+ }
+ }
+ }
+
+ Name (MEMA, 0x43D10000)
+}
+
new file mode 100644
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C+DE+r
literal 0
HcmV?d00001
new file mode 100644
@@ -0,0 +1,1106 @@
+/*
+ * QTest
+ *
+ * Copyright IBM, Corp. 2012
+ * Copyright Red Hat, Inc. 2012
+ * Copyright SUSE LINUX Products GmbH 2013
+ *
+ * Authors:
+ * Anthony Liguori <aliguori@us.ibm.com>
+ * Paolo Bonzini <pbonzini@redhat.com>
+ * Andreas Färber <afaerber@suse.de>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+
+#include <sys/socket.h>
+#include <sys/wait.h>
+#include <sys/un.h>
+
+#include "libqtest.h"
+#include "qemu/cutils.h"
+#include "qapi/error.h"
+#include "qapi/qmp/json-parser.h"
+#include "qapi/qmp/json-streamer.h"
+#include "qapi/qmp/qdict.h"
+#include "qapi/qmp/qjson.h"
+#include "qapi/qmp/qlist.h"
+#include "qapi/qmp/qstring.h"
+
+#define MAX_IRQ 256
+#define SOCKET_TIMEOUT 50
+
+QTestState *global_qtest;
+
+struct QTestState
+{
+ int fd;
+ int qmp_fd;
+ bool irq_level[MAX_IRQ];
+ GString *rx;
+ pid_t qemu_pid; /* our child QEMU process */
+ bool big_endian;
+};
+
+static GHookList abrt_hooks;
+static struct sigaction sigact_old;
+
+#define g_assert_no_errno(ret) do { \
+ g_assert_cmpint(ret, !=, -1); \
+} while (0)
+
+static int qtest_query_target_endianness(QTestState *s);
+
+static int init_socket(const char *socket_path)
+{
+ struct sockaddr_un addr;
+ int sock;
+ int ret;
+
+ sock = socket(PF_UNIX, SOCK_STREAM, 0);
+ g_assert_no_errno(sock);
+
+ addr.sun_family = AF_UNIX;
+ snprintf(addr.sun_path, sizeof(addr.sun_path), "%s", socket_path);
+ qemu_set_cloexec(sock);
+
+ do {
+ ret = bind(sock, (struct sockaddr *)&addr, sizeof(addr));
+ } while (ret == -1 && errno == EINTR);
+ g_assert_no_errno(ret);
+ ret = listen(sock, 1);
+ g_assert_no_errno(ret);
+
+ return sock;
+}
+
+static int socket_accept(int sock)
+{
+ struct sockaddr_un addr;
+ socklen_t addrlen;
+ int ret;
+ struct timeval timeout = { .tv_sec = SOCKET_TIMEOUT,
+ .tv_usec = 0 };
+
+ setsockopt(sock, SOL_SOCKET, SO_RCVTIMEO, (void *)&timeout,
+ sizeof(timeout));
+
+ do {
+ addrlen = sizeof(addr);
+ ret = accept(sock, (struct sockaddr *)&addr, &addrlen);
+ } while (ret == -1 && errno == EINTR);
+ if (ret == -1) {
+ fprintf(stderr, "%s failed: %s\n", __func__, strerror(errno));
+ }
+ close(sock);
+
+ return ret;
+}
+
+static void kill_qemu(QTestState *s)
+{
+ int wstatus = 0;
+
+ if (s->qemu_pid != -1) {
+ kill(s->qemu_pid, SIGTERM);
+ waitpid(s->qemu_pid, &wstatus, 0);
+
+ if (WIFSIGNALED(wstatus)) {
+ assert(!WCOREDUMP(wstatus));
+ }
+ }
+}
+
+static void kill_qemu_hook_func(void *s)
+{
+ kill_qemu(s);
+}
+
+static void sigabrt_handler(int signo)
+{
+ g_hook_list_invoke(&abrt_hooks, FALSE);
+}
+
+static void setup_sigabrt_handler(void)
+{
+ struct sigaction sigact;
+
+ /* Catch SIGABRT to clean up on g_assert() failure */
+ sigact = (struct sigaction){
+ .sa_handler = sigabrt_handler,
+ .sa_flags = SA_RESETHAND,
+ };
+ sigemptyset(&sigact.sa_mask);
+ sigaction(SIGABRT, &sigact, &sigact_old);
+}
+
+static void cleanup_sigabrt_handler(void)
+{
+ sigaction(SIGABRT, &sigact_old, NULL);
+}
+
+void qtest_add_abrt_handler(GHookFunc fn, const void *data)
+{
+ GHook *hook;
+
+ /* Only install SIGABRT handler once */
+ if (!abrt_hooks.is_setup) {
+ g_hook_list_init(&abrt_hooks, sizeof(GHook));
+ }
+ setup_sigabrt_handler();
+
+ hook = g_hook_alloc(&abrt_hooks);
+ hook->func = fn;
+ hook->data = (void *)data;
+
+ g_hook_prepend(&abrt_hooks, hook);
+}
+
+static const char *qtest_qemu_binary(void)
+{
+ const char *qemu_bin;
+
+ qemu_bin = getenv("QTEST_QEMU_BINARY");
+ if (!qemu_bin) {
+ fprintf(stderr, "Environment variable QTEST_QEMU_BINARY required\n");
+ exit(1);
+ }
+
+ return qemu_bin;
+}
+
+QTestState *qtest_init_without_qmp_handshake(bool use_oob,
+ const char *extra_args)
+{
+ QTestState *s;
+ int sock, qmpsock, i;
+ gchar *socket_path;
+ gchar *qmp_socket_path;
+ gchar *command;
+ const char *qemu_binary = qtest_qemu_binary();
+
+ s = g_new(QTestState, 1);
+
+ socket_path = g_strdup_printf("/tmp/qtest-%d.sock", getpid());
+ qmp_socket_path = g_strdup_printf("/tmp/qtest-%d.qmp", getpid());
+
+ /* It's possible that if an earlier test run crashed it might
+ * have left a stale unix socket lying around. Delete any
+ * stale old socket to avoid spurious test failures with
+ * tests/libqtest.c:70:init_socket: assertion failed (ret != -1): (-1 != -1)
+ */
+ unlink(socket_path);
+ unlink(qmp_socket_path);
+
+ sock = init_socket(socket_path);
+ qmpsock = init_socket(qmp_socket_path);
+
+ qtest_add_abrt_handler(kill_qemu_hook_func, s);
+
+ s->qemu_pid = fork();
+ if (s->qemu_pid == 0) {
+ setenv("QEMU_AUDIO_DRV", "none", true);
+ command = g_strdup_printf("exec %s "
+ "-qtest unix:%s,nowait "
+ "-qtest-log %s "
+ "-chardev socket,path=%s,nowait,id=char0 "
+ "-mon chardev=char0,mode=control%s "
+ "-machine accel=qtest "
+ "-display none "
+ "%s", qemu_binary, socket_path,
+ getenv("QTEST_LOG") ? "/dev/fd/2" : "/dev/null",
+ qmp_socket_path, use_oob ? ",x-oob=on" : "",
+ extra_args ?: "");
+ execlp("/bin/sh", "sh", "-c", command, NULL);
+ exit(1);
+ }
+
+ s->fd = socket_accept(sock);
+ if (s->fd >= 0) {
+ s->qmp_fd = socket_accept(qmpsock);
+ }
+ unlink(socket_path);
+ unlink(qmp_socket_path);
+ g_free(socket_path);
+ g_free(qmp_socket_path);
+
+ g_assert(s->fd >= 0 && s->qmp_fd >= 0);
+
+ s->rx = g_string_new("");
+ for (i = 0; i < MAX_IRQ; i++) {
+ s->irq_level[i] = false;
+ }
+
+ if (getenv("QTEST_STOP")) {
+ kill(s->qemu_pid, SIGSTOP);
+ }
+
+ /* ask endianness of the target */
+
+ s->big_endian = qtest_query_target_endianness(s);
+
+ return s;
+}
+
+QTestState *qtest_init(const char *extra_args)
+{
+ QTestState *s = qtest_init_without_qmp_handshake(false, extra_args);
+
+ /* Read the QMP greeting and then do the handshake */
+ qtest_qmp_discard_response(s, "");
+ qtest_qmp_discard_response(s, "{ 'execute': 'qmp_capabilities' }");
+
+ return s;
+}
+
+QTestState *qtest_vstartf(const char *fmt, va_list ap)
+{
+ char *args = g_strdup_vprintf(fmt, ap);
+ QTestState *s;
+
+ s = qtest_start(args);
+ g_free(args);
+ global_qtest = NULL;
+ return s;
+}
+
+QTestState *qtest_startf(const char *fmt, ...)
+{
+ va_list ap;
+ QTestState *s;
+
+ va_start(ap, fmt);
+ s = qtest_vstartf(fmt, ap);
+ va_end(ap);
+ return s;
+}
+
+void qtest_quit(QTestState *s)
+{
+ g_hook_destroy_link(&abrt_hooks, g_hook_find_data(&abrt_hooks, TRUE, s));
+
+ /* Uninstall SIGABRT handler on last instance */
+ cleanup_sigabrt_handler();
+
+ kill_qemu(s);
+ close(s->fd);
+ close(s->qmp_fd);
+ g_string_free(s->rx, true);
+ g_free(s);
+}
+
+static void socket_send(int fd, const char *buf, size_t size)
+{
+ size_t offset;
+
+ offset = 0;
+ while (offset < size) {
+ ssize_t len;
+
+ len = write(fd, buf + offset, size - offset);
+ if (len == -1 && errno == EINTR) {
+ continue;
+ }
+
+ g_assert_no_errno(len);
+ g_assert_cmpint(len, >, 0);
+
+ offset += len;
+ }
+}
+
+static void socket_sendf(int fd, const char *fmt, va_list ap)
+{
+ gchar *str = g_strdup_vprintf(fmt, ap);
+ size_t size = strlen(str);
+
+ socket_send(fd, str, size);
+ g_free(str);
+}
+
+static void GCC_FMT_ATTR(2, 3) qtest_sendf(QTestState *s, const char *fmt, ...)
+{
+ va_list ap;
+
+ va_start(ap, fmt);
+ socket_sendf(s->fd, fmt, ap);
+ va_end(ap);
+}
+
+static GString *qtest_recv_line(QTestState *s)
+{
+ GString *line;
+ size_t offset;
+ char *eol;
+
+ while ((eol = strchr(s->rx->str, '\n')) == NULL) {
+ ssize_t len;
+ char buffer[1024];
+
+ len = read(s->fd, buffer, sizeof(buffer));
+ if (len == -1 && errno == EINTR) {
+ continue;
+ }
+
+ if (len == -1 || len == 0) {
+ fprintf(stderr, "Broken pipe\n");
+ exit(1);
+ }
+
+ g_string_append_len(s->rx, buffer, len);
+ }
+
+ offset = eol - s->rx->str;
+ line = g_string_new_len(s->rx->str, offset);
+ g_string_erase(s->rx, 0, offset + 1);
+
+ return line;
+}
+
+static gchar **qtest_rsp(QTestState *s, int expected_args)
+{
+ GString *line;
+ gchar **words;
+ int i;
+
+redo:
+ line = qtest_recv_line(s);
+ words = g_strsplit(line->str, " ", 0);
+ g_string_free(line, TRUE);
+
+ if (strcmp(words[0], "IRQ") == 0) {
+ long irq;
+ int ret;
+
+ g_assert(words[1] != NULL);
+ g_assert(words[2] != NULL);
+
+ ret = qemu_strtol(words[2], NULL, 0, &irq);
+ g_assert(!ret);
+ g_assert_cmpint(irq, >=, 0);
+ g_assert_cmpint(irq, <, MAX_IRQ);
+
+ if (strcmp(words[1], "raise") == 0) {
+ s->irq_level[irq] = true;
+ } else {
+ s->irq_level[irq] = false;
+ }
+
+ g_strfreev(words);
+ goto redo;
+ }
+
+ g_assert(words[0] != NULL);
+ g_assert_cmpstr(words[0], ==, "OK");
+
+ if (expected_args) {
+ for (i = 0; i < expected_args; i++) {
+ g_assert(words[i] != NULL);
+ }
+ } else {
+ g_strfreev(words);
+ }
+
+ return words;
+}
+
+static int qtest_query_target_endianness(QTestState *s)
+{
+ gchar **args;
+ int big_endian;
+
+ qtest_sendf(s, "endianness\n");
+ args = qtest_rsp(s, 1);
+ g_assert(strcmp(args[1], "big") == 0 || strcmp(args[1], "little") == 0);
+ big_endian = strcmp(args[1], "big") == 0;
+ g_strfreev(args);
+
+ return big_endian;
+}
+
+typedef struct {
+ JSONMessageParser parser;
+ QDict *response;
+} QMPResponseParser;
+
+static void qmp_response(JSONMessageParser *parser, GQueue *tokens)
+{
+ QMPResponseParser *qmp = container_of(parser, QMPResponseParser, parser);
+ QObject *obj;
+
+ obj = json_parser_parse(tokens, NULL);
+ if (!obj) {
+ fprintf(stderr, "QMP JSON response parsing failed\n");
+ exit(1);
+ }
+
+ g_assert(!qmp->response);
+ qmp->response = qobject_to(QDict, obj);
+ g_assert(qmp->response);
+}
+
+QDict *qmp_fd_receive(int fd)
+{
+ QMPResponseParser qmp;
+ bool log = getenv("QTEST_LOG") != NULL;
+
+ qmp.response = NULL;
+ json_message_parser_init(&qmp.parser, qmp_response);
+ while (!qmp.response) {
+ ssize_t len;
+ char c;
+
+ len = read(fd, &c, 1);
+ if (len == -1 && errno == EINTR) {
+ continue;
+ }
+
+ if (len == -1 || len == 0) {
+ fprintf(stderr, "Broken pipe\n");
+ exit(1);
+ }
+
+ if (log) {
+ len = write(2, &c, 1);
+ }
+ json_message_parser_feed(&qmp.parser, &c, 1);
+ }
+ json_message_parser_destroy(&qmp.parser);
+
+ return qmp.response;
+}
+
+QDict *qtest_qmp_receive(QTestState *s)
+{
+ return qmp_fd_receive(s->qmp_fd);
+}
+
+/**
+ * Allow users to send a message without waiting for the reply,
+ * in the case that they choose to discard all replies up until
+ * a particular EVENT is received.
+ */
+void qmp_fd_sendv(int fd, const char *fmt, va_list ap)
+{
+ va_list ap_copy;
+ QObject *qobj;
+
+ /* qobject_from_jsonv() silently eats leading 0xff as invalid
+ * JSON, but we want to test sending them over the wire to force
+ * resyncs */
+ if (*fmt == '\377') {
+ socket_send(fd, fmt, 1);
+ fmt++;
+ }
+
+ /* Going through qobject ensures we escape strings properly.
+ * This seemingly unnecessary copy is required in case va_list
+ * is an array type.
+ */
+ va_copy(ap_copy, ap);
+ qobj = qobject_from_jsonv(fmt, &ap_copy, &error_abort);
+ va_end(ap_copy);
+
+ /* No need to send anything for an empty QObject. */
+ if (qobj) {
+ int log = getenv("QTEST_LOG") != NULL;
+ QString *qstr = qobject_to_json(qobj);
+ const char *str;
+
+ /*
+ * BUG: QMP doesn't react to input until it sees a newline, an
+ * object, or an array. Work-around: give it a newline.
+ */
+ qstring_append_chr(qstr, '\n');
+ str = qstring_get_str(qstr);
+
+ if (log) {
+ fprintf(stderr, "%s", str);
+ }
+ /* Send QMP request */
+ socket_send(fd, str, qstring_get_length(qstr));
+
+ qobject_unref(qstr);
+ qobject_unref(qobj);
+ }
+}
+
+void qtest_async_qmpv(QTestState *s, const char *fmt, va_list ap)
+{
+ qmp_fd_sendv(s->qmp_fd, fmt, ap);
+}
+
+QDict *qmp_fdv(int fd, const char *fmt, va_list ap)
+{
+ qmp_fd_sendv(fd, fmt, ap);
+
+ return qmp_fd_receive(fd);
+}
+
+QDict *qtest_qmpv(QTestState *s, const char *fmt, va_list ap)
+{
+ qtest_async_qmpv(s, fmt, ap);
+
+ /* Receive reply */
+ return qtest_qmp_receive(s);
+}
+
+QDict *qmp_fd(int fd, const char *fmt, ...)
+{
+ va_list ap;
+ QDict *response;
+
+ va_start(ap, fmt);
+ response = qmp_fdv(fd, fmt, ap);
+ va_end(ap);
+ return response;
+}
+
+void qmp_fd_send(int fd, const char *fmt, ...)
+{
+ va_list ap;
+
+ va_start(ap, fmt);
+ qmp_fd_sendv(fd, fmt, ap);
+ va_end(ap);
+}
+
+QDict *qtest_qmp(QTestState *s, const char *fmt, ...)
+{
+ va_list ap;
+ QDict *response;
+
+ va_start(ap, fmt);
+ response = qtest_qmpv(s, fmt, ap);
+ va_end(ap);
+ return response;
+}
+
+void qtest_async_qmp(QTestState *s, const char *fmt, ...)
+{
+ va_list ap;
+
+ va_start(ap, fmt);
+ qtest_async_qmpv(s, fmt, ap);
+ va_end(ap);
+}
+
+void qtest_qmpv_discard_response(QTestState *s, const char *fmt, va_list ap)
+{
+ QDict *response = qtest_qmpv(s, fmt, ap);
+ qobject_unref(response);
+}
+
+void qtest_qmp_discard_response(QTestState *s, const char *fmt, ...)
+{
+ va_list ap;
+ QDict *response;
+
+ va_start(ap, fmt);
+ response = qtest_qmpv(s, fmt, ap);
+ va_end(ap);
+ qobject_unref(response);
+}
+
+QDict *qtest_qmp_eventwait_ref(QTestState *s, const char *event)
+{
+ QDict *response;
+
+ for (;;) {
+ response = qtest_qmp_receive(s);
+ if ((qdict_haskey(response, "event")) &&
+ (strcmp(qdict_get_str(response, "event"), event) == 0)) {
+ return response;
+ }
+ qobject_unref(response);
+ }
+}
+
+void qtest_qmp_eventwait(QTestState *s, const char *event)
+{
+ QDict *response;
+
+ response = qtest_qmp_eventwait_ref(s, event);
+ qobject_unref(response);
+}
+
+char *qtest_hmpv(QTestState *s, const char *fmt, va_list ap)
+{
+ char *cmd;
+ QDict *resp;
+ char *ret;
+
+ cmd = g_strdup_vprintf(fmt, ap);
+ resp = qtest_qmp(s, "{'execute': 'human-monitor-command',"
+ " 'arguments': {'command-line': %s}}",
+ cmd);
+ ret = g_strdup(qdict_get_try_str(resp, "return"));
+ while (ret == NULL && qdict_get_try_str(resp, "event")) {
+ /* Ignore asynchronous QMP events */
+ qobject_unref(resp);
+ resp = qtest_qmp_receive(s);
+ ret = g_strdup(qdict_get_try_str(resp, "return"));
+ }
+ g_assert(ret);
+ qobject_unref(resp);
+ g_free(cmd);
+ return ret;
+}
+
+char *qtest_hmp(QTestState *s, const char *fmt, ...)
+{
+ va_list ap;
+ char *ret;
+
+ va_start(ap, fmt);
+ ret = qtest_hmpv(s, fmt, ap);
+ va_end(ap);
+ return ret;
+}
+
+const char *qtest_get_arch(void)
+{
+ const char *qemu = qtest_qemu_binary();
+ const char *end = strrchr(qemu, '/');
+
+ return end + strlen("/qemu-system-");
+}
+
+bool qtest_get_irq(QTestState *s, int num)
+{
+ /* dummy operation in order to make sure irq is up to date */
+ qtest_inb(s, 0);
+
+ return s->irq_level[num];
+}
+
+static int64_t qtest_clock_rsp(QTestState *s)
+{
+ gchar **words;
+ int64_t clock;
+ words = qtest_rsp(s, 2);
+ clock = g_ascii_strtoll(words[1], NULL, 0);
+ g_strfreev(words);
+ return clock;
+}
+
+int64_t qtest_clock_step_next(QTestState *s)
+{
+ qtest_sendf(s, "clock_step\n");
+ return qtest_clock_rsp(s);
+}
+
+int64_t qtest_clock_step(QTestState *s, int64_t step)
+{
+ qtest_sendf(s, "clock_step %"PRIi64"\n", step);
+ return qtest_clock_rsp(s);
+}
+
+int64_t qtest_clock_set(QTestState *s, int64_t val)
+{
+ qtest_sendf(s, "clock_set %"PRIi64"\n", val);
+ return qtest_clock_rsp(s);
+}
+
+void qtest_irq_intercept_out(QTestState *s, const char *qom_path)
+{
+ qtest_sendf(s, "irq_intercept_out %s\n", qom_path);
+ qtest_rsp(s, 0);
+}
+
+void qtest_irq_intercept_in(QTestState *s, const char *qom_path)
+{
+ qtest_sendf(s, "irq_intercept_in %s\n", qom_path);
+ qtest_rsp(s, 0);
+}
+
+static void qtest_out(QTestState *s, const char *cmd, uint16_t addr, uint32_t value)
+{
+ qtest_sendf(s, "%s 0x%x 0x%x\n", cmd, addr, value);
+ qtest_rsp(s, 0);
+}
+
+void qtest_outb(QTestState *s, uint16_t addr, uint8_t value)
+{
+ qtest_out(s, "outb", addr, value);
+}
+
+void qtest_outw(QTestState *s, uint16_t addr, uint16_t value)
+{
+ qtest_out(s, "outw", addr, value);
+}
+
+void qtest_outl(QTestState *s, uint16_t addr, uint32_t value)
+{
+ qtest_out(s, "outl", addr, value);
+}
+
+static uint32_t qtest_in(QTestState *s, const char *cmd, uint16_t addr)
+{
+ gchar **args;
+ int ret;
+ unsigned long value;
+
+ qtest_sendf(s, "%s 0x%x\n", cmd, addr);
+ args = qtest_rsp(s, 2);
+ ret = qemu_strtoul(args[1], NULL, 0, &value);
+ g_assert(!ret && value <= UINT32_MAX);
+ g_strfreev(args);
+
+ return value;
+}
+
+uint8_t qtest_inb(QTestState *s, uint16_t addr)
+{
+ return qtest_in(s, "inb", addr);
+}
+
+uint16_t qtest_inw(QTestState *s, uint16_t addr)
+{
+ return qtest_in(s, "inw", addr);
+}
+
+uint32_t qtest_inl(QTestState *s, uint16_t addr)
+{
+ return qtest_in(s, "inl", addr);
+}
+
+static void qtest_write(QTestState *s, const char *cmd, uint64_t addr,
+ uint64_t value)
+{
+ qtest_sendf(s, "%s 0x%" PRIx64 " 0x%" PRIx64 "\n", cmd, addr, value);
+ qtest_rsp(s, 0);
+}
+
+void qtest_writeb(QTestState *s, uint64_t addr, uint8_t value)
+{
+ qtest_write(s, "writeb", addr, value);
+}
+
+void qtest_writew(QTestState *s, uint64_t addr, uint16_t value)
+{
+ qtest_write(s, "writew", addr, value);
+}
+
+void qtest_writel(QTestState *s, uint64_t addr, uint32_t value)
+{
+ qtest_write(s, "writel", addr, value);
+}
+
+void qtest_writeq(QTestState *s, uint64_t addr, uint64_t value)
+{
+ qtest_write(s, "writeq", addr, value);
+}
+
+static uint64_t qtest_read(QTestState *s, const char *cmd, uint64_t addr)
+{
+ gchar **args;
+ int ret;
+ uint64_t value;
+
+ qtest_sendf(s, "%s 0x%" PRIx64 "\n", cmd, addr);
+ args = qtest_rsp(s, 2);
+ ret = qemu_strtou64(args[1], NULL, 0, &value);
+ g_assert(!ret);
+ g_strfreev(args);
+
+ return value;
+}
+
+uint8_t qtest_readb(QTestState *s, uint64_t addr)
+{
+ return qtest_read(s, "readb", addr);
+}
+
+uint16_t qtest_readw(QTestState *s, uint64_t addr)
+{
+ return qtest_read(s, "readw", addr);
+}
+
+uint32_t qtest_readl(QTestState *s, uint64_t addr)
+{
+ return qtest_read(s, "readl", addr);
+}
+
+uint64_t qtest_readq(QTestState *s, uint64_t addr)
+{
+ return qtest_read(s, "readq", addr);
+}
+
+static int hex2nib(char ch)
+{
+ if (ch >= '0' && ch <= '9') {
+ return ch - '0';
+ } else if (ch >= 'a' && ch <= 'f') {
+ return 10 + (ch - 'a');
+ } else if (ch >= 'A' && ch <= 'F') {
+ return 10 + (ch - 'a');
+ } else {
+ return -1;
+ }
+}
+
+void qtest_memread(QTestState *s, uint64_t addr, void *data, size_t size)
+{
+ uint8_t *ptr = data;
+ gchar **args;
+ size_t i;
+
+ if (!size) {
+ return;
+ }
+
+ qtest_sendf(s, "read 0x%" PRIx64 " 0x%zx\n", addr, size);
+ args = qtest_rsp(s, 2);
+
+ for (i = 0; i < size; i++) {
+ ptr[i] = hex2nib(args[1][2 + (i * 2)]) << 4;
+ ptr[i] |= hex2nib(args[1][2 + (i * 2) + 1]);
+ }
+
+ g_strfreev(args);
+}
+
+uint64_t qtest_rtas_call(QTestState *s, const char *name,
+ uint32_t nargs, uint64_t args,
+ uint32_t nret, uint64_t ret)
+{
+ qtest_sendf(s, "rtas %s %u 0x%"PRIx64" %u 0x%"PRIx64"\n",
+ name, nargs, args, nret, ret);
+ qtest_rsp(s, 0);
+ return 0;
+}
+
+void qtest_add_func(const char *str, void (*fn)(void))
+{
+ gchar *path = g_strdup_printf("/%s/%s", qtest_get_arch(), str);
+ g_test_add_func(path, fn);
+ g_free(path);
+}
+
+void qtest_add_data_func_full(const char *str, void *data,
+ void (*fn)(const void *),
+ GDestroyNotify data_free_func)
+{
+ gchar *path = g_strdup_printf("/%s/%s", qtest_get_arch(), str);
+ g_test_add_data_func_full(path, data, fn, data_free_func);
+ g_free(path);
+}
+
+void qtest_add_data_func(const char *str, const void *data,
+ void (*fn)(const void *))
+{
+ gchar *path = g_strdup_printf("/%s/%s", qtest_get_arch(), str);
+ g_test_add_data_func(path, data, fn);
+ g_free(path);
+}
+
+void qtest_bufwrite(QTestState *s, uint64_t addr, const void *data, size_t size)
+{
+ gchar *bdata;
+
+ bdata = g_base64_encode(data, size);
+ qtest_sendf(s, "b64write 0x%" PRIx64 " 0x%zx ", addr, size);
+ socket_send(s->fd, bdata, strlen(bdata));
+ socket_send(s->fd, "\n", 1);
+ qtest_rsp(s, 0);
+ g_free(bdata);
+}
+
+void qtest_bufread(QTestState *s, uint64_t addr, void *data, size_t size)
+{
+ gchar **args;
+ size_t len;
+
+ qtest_sendf(s, "b64read 0x%" PRIx64 " 0x%zx\n", addr, size);
+ args = qtest_rsp(s, 2);
+
+ g_base64_decode_inplace(args[1], &len);
+ if (size != len) {
+ fprintf(stderr, "bufread: asked for %zu bytes but decoded %zu\n",
+ size, len);
+ len = MIN(len, size);
+ }
+
+ memcpy(data, args[1], len);
+ g_strfreev(args);
+}
+
+void qtest_memwrite(QTestState *s, uint64_t addr, const void *data, size_t size)
+{
+ const uint8_t *ptr = data;
+ size_t i;
+ char *enc;
+
+ if (!size) {
+ return;
+ }
+
+ enc = g_malloc(2 * size + 1);
+
+ for (i = 0; i < size; i++) {
+ sprintf(&enc[i * 2], "%02x", ptr[i]);
+ }
+
+ qtest_sendf(s, "write 0x%" PRIx64 " 0x%zx 0x%s\n", addr, size, enc);
+ qtest_rsp(s, 0);
+ g_free(enc);
+}
+
+void qtest_memset(QTestState *s, uint64_t addr, uint8_t pattern, size_t size)
+{
+ qtest_sendf(s, "memset 0x%" PRIx64 " 0x%zx 0x%02x\n", addr, size, pattern);
+ qtest_rsp(s, 0);
+}
+
+QDict *qmp(const char *fmt, ...)
+{
+ va_list ap;
+ QDict *response;
+
+ va_start(ap, fmt);
+ response = qtest_qmpv(global_qtest, fmt, ap);
+ va_end(ap);
+ return response;
+}
+
+void qmp_async(const char *fmt, ...)
+{
+ va_list ap;
+
+ va_start(ap, fmt);
+ qtest_async_qmpv(global_qtest, fmt, ap);
+ va_end(ap);
+}
+
+void qmp_discard_response(const char *fmt, ...)
+{
+ va_list ap;
+
+ va_start(ap, fmt);
+ qtest_qmpv_discard_response(global_qtest, fmt, ap);
+ va_end(ap);
+}
+char *hmp(const char *fmt, ...)
+{
+ va_list ap;
+ char *ret;
+
+ va_start(ap, fmt);
+ ret = qtest_hmpv(global_qtest, fmt, ap);
+ va_end(ap);
+ return ret;
+}
+
+bool qtest_big_endian(QTestState *s)
+{
+ return s->big_endian;
+}
+
+void qtest_cb_for_every_machine(void (*cb)(const char *machine))
+{
+ QDict *response, *minfo;
+ QList *list;
+ const QListEntry *p;
+ QObject *qobj;
+ QString *qstr;
+ const char *mname;
+
+ qtest_start("-machine none");
+ response = qmp("{ 'execute': 'query-machines' }");
+ g_assert(response);
+ list = qdict_get_qlist(response, "return");
+ g_assert(list);
+
+ for (p = qlist_first(list); p; p = qlist_next(p)) {
+ minfo = qobject_to(QDict, qlist_entry_obj(p));
+ g_assert(minfo);
+ qobj = qdict_get(minfo, "name");
+ g_assert(qobj);
+ qstr = qobject_to(QString, qobj);
+ g_assert(qstr);
+ mname = qstring_get_str(qstr);
+ cb(mname);
+ }
+
+ qtest_end();
+ qobject_unref(response);
+}
+
+/*
+ * Generic hot-plugging test via the device_add QMP command.
+ */
+void qtest_qmp_device_add(const char *driver, const char *id, const char *fmt,
+ ...)
+{
+ QDict *response;
+ char *cmd, *opts = NULL;
+ va_list va;
+
+ if (fmt) {
+ va_start(va, fmt);
+ opts = g_strdup_vprintf(fmt, va);
+ va_end(va);
+ }
+
+ cmd = g_strdup_printf("{'execute': 'device_add',"
+ " 'arguments': { 'driver': '%s', 'id': '%s'%s%s }}",
+ driver, id, opts ? ", " : "", opts ? opts : "");
+ g_free(opts);
+
+ response = qmp(cmd);
+ g_free(cmd);
+ g_assert(response);
+ g_assert(!qdict_haskey(response, "event")); /* We don't expect any events */
+ g_assert(!qdict_haskey(response, "error"));
+ qobject_unref(response);
+}
+
+/*
+ * Generic hot-unplugging test via the device_del QMP command.
+ * Device deletion will get one response and one event. For example:
+ *
+ * {'execute': 'device_del','arguments': { 'id': 'scsi-hd'}}
+ *
+ * will get this one:
+ *
+ * {"timestamp": {"seconds": 1505289667, "microseconds": 569862},
+ * "event": "DEVICE_DELETED", "data": {"device": "scsi-hd",
+ * "path": "/machine/peripheral/scsi-hd"}}
+ *
+ * and this one:
+ *
+ * {"return": {}}
+ *
+ * But the order of arrival may vary - so we've got to detect both.
+ */
+void qtest_qmp_device_del(const char *id)
+{
+ QDict *response1, *response2, *event = NULL;
+ char *cmd;
+
+ cmd = g_strdup_printf("{'execute': 'device_del',"
+ " 'arguments': { 'id': '%s' }}", id);
+ response1 = qmp(cmd);
+ g_free(cmd);
+ g_assert(response1);
+ g_assert(!qdict_haskey(response1, "error"));
+
+ response2 = qmp("");
+ g_assert(response2);
+ g_assert(!qdict_haskey(response2, "error"));
+
+ if (qdict_haskey(response1, "event")) {
+ event = response1;
+ } else if (qdict_haskey(response2, "event")) {
+ event = response2;
+ }
+ g_assert(event);
+ g_assert_cmpstr(qdict_get_str(event, "event"), ==, "DEVICE_DELETED");
+
+ qobject_unref(response1);
+ qobject_unref(response2);
+}
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HcmV?d00001
new file mode 100644
@@ -0,0 +1,18 @@
+/* List of comma-separated changed AML files to ignore */
+"tests/data/acpi/pc/DSDT",
+"tests/data/acpi/pc/DSDT.acpihmat",
+"tests/data/acpi/pc/DSDT.bridge",
+"tests/data/acpi/pc/DSDT.cphp",
+"tests/data/acpi/pc/DSDT.dimmpxm",
+"tests/data/acpi/pc/DSDT.ipmikcs",
+"tests/data/acpi/pc/DSDT.memhp",
+"tests/data/acpi/pc/DSDT.numamem",
+"tests/data/acpi/q35/DSDT",
+"tests/data/acpi/q35/DSDT.acpihmat",
+"tests/data/acpi/q35/DSDT.bridge",
+"tests/data/acpi/q35/DSDT.cphp",
+"tests/data/acpi/q35/DSDT.dimmpxm",
+"tests/data/acpi/q35/DSDT.ipmibt",
+"tests/data/acpi/q35/DSDT.memhp",
+"tests/data/acpi/q35/DSDT.mmio64",
+"tests/data/acpi/q35/DSDT.numamem",
new file mode 100644
@@ -0,0 +1,9 @@
+--- tests/qtest/bios-tables-test-allowed-diff.h
++++ tests/qtest/bios-tables-test-allowed-diff.h
+@@ -1,6 +1 @@
+ /* List of comma-separated changed AML files to ignore */
+-"tests/data/acpi/pc/SSDT.dimmpxm",
+-"tests/data/acpi/q35/SSDT.dimmpxm",
+-"tests/data/acpi/virt/DSDT.memhp",
+-"tests/data/acpi/virt/SSDT.memhp",
+-"tests/data/acpi/virt/NFIT.memhp",
new file mode 100644
@@ -0,0 +1,1200 @@
+/*
+ * Boot order test cases.
+ *
+ * Copyright (c) 2013 Red Hat Inc.
+ *
+ * Authors:
+ * Michael S. Tsirkin <mst@redhat.com>,
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+/*
+ * How to add or update the tests:
+ * Contributor:
+ * 1. add empty files for new tables, if any, under tests/data/acpi
+ * 2. list any changed files in tests/qtest/bios-tables-test-allowed-diff.h
+ * 3. commit the above *before* making changes that affect the tables
+ *
+ * Contributor or ACPI Maintainer (steps 4-7 need to be redone to resolve conflicts
+ * in binary commit created in step 6):
+ *
+ * After 1-3 above tests will pass but ignore differences with the expected files.
+ * You will also notice that tests/qtest/bios-tables-test-allowed-diff.h lists
+ * a bunch of files. This is your hint that you need to do the below:
+ * 4. Run
+ * make check V=1
+ * this will produce a bunch of warnings about differences
+ * beween actual and expected ACPI tables. If you have IASL installed,
+ * they will also be disassembled so you can look at the disassembled
+ * output. If not - disassemble them yourself in any way you like.
+ * Look at the differences - make sure they make sense and match what the
+ * changes you are merging are supposed to do.
+ * Save the changes, preferably in form of ASL diff for the commit log in
+ * step 6.
+ *
+ * 5. From build directory, run:
+ * $(SRC_PATH)/tests/data/acpi/rebuild-expected-aml.sh
+ * 6. Now commit any changes to the expected binary, include diff from step 4
+ * in commit log.
+ * 7. Before sending patches to the list (Contributor)
+ * or before doing a pull request (Maintainer), make sure
+ * tests/qtest/bios-tables-test-allowed-diff.h is empty - this will ensure
+ * following changes to ACPI tables will be noticed.
+ *
+ * The resulting patchset/pull request then looks like this:
+ * - patch 1: list changed files in tests/qtest/bios-tables-test-allowed-diff.h.
+ * - patches 2 - n: real changes, may contain multiple patches.
+ * - patch n + 1: update golden master binaries and empty
+ * tests/qtest/bios-tables-test-allowed-diff.h
+ */
+
+#include "qemu/osdep.h"
+#include <glib/gstdio.h>
+#include "qemu-common.h"
+#include "hw/firmware/smbios.h"
+#include "qemu/bitmap.h"
+#include "acpi-utils.h"
+#include "boot-sector.h"
+#include "tpm-emu.h"
+#include "hw/acpi/tpm.h"
+
+
+#define MACHINE_PC "pc"
+#define MACHINE_Q35 "q35"
+
+#define ACPI_REBUILD_EXPECTED_AML "TEST_ACPI_REBUILD_AML"
+
+typedef struct {
+ bool tcg_only;
+ const char *machine;
+ const char *variant;
+ const char *uefi_fl1;
+ const char *uefi_fl2;
+ const char *cd;
+ const uint64_t ram_start;
+ const uint64_t scan_len;
+ uint64_t rsdp_addr;
+ uint8_t rsdp_table[36 /* ACPI 2.0+ RSDP size */];
+ GArray *tables;
+ uint32_t smbios_ep_addr;
+ struct smbios_21_entry_point smbios_ep_table;
+ uint16_t smbios_cpu_max_speed;
+ uint16_t smbios_cpu_curr_speed;
+ uint8_t *required_struct_types;
+ int required_struct_types_len;
+ QTestState *qts;
+} test_data;
+
+static char disk[] = "tests/acpi-test-disk-XXXXXX";
+static const char *data_dir = "tests/data/acpi";
+#ifdef CONFIG_IASL
+static const char *iasl = CONFIG_IASL;
+#else
+static const char *iasl;
+#endif
+
+static bool compare_signature(const AcpiSdtTable *sdt, const char *signature)
+{
+ return !memcmp(sdt->aml, signature, 4);
+}
+
+static void cleanup_table_descriptor(AcpiSdtTable *table)
+{
+ g_free(table->aml);
+ if (table->aml_file &&
+ !table->tmp_files_retain &&
+ g_strstr_len(table->aml_file, -1, "aml-")) {
+ unlink(table->aml_file);
+ }
+ g_free(table->aml_file);
+ g_free(table->asl);
+ if (table->asl_file &&
+ !table->tmp_files_retain) {
+ unlink(table->asl_file);
+ }
+ g_free(table->asl_file);
+}
+
+static void free_test_data(test_data *data)
+{
+ int i;
+
+ for (i = 0; i < data->tables->len; ++i) {
+ cleanup_table_descriptor(&g_array_index(data->tables, AcpiSdtTable, i));
+ }
+
+ g_array_free(data->tables, true);
+}
+
+static void test_acpi_rsdp_table(test_data *data)
+{
+ uint8_t *rsdp_table = data->rsdp_table;
+
+ acpi_fetch_rsdp_table(data->qts, data->rsdp_addr, rsdp_table);
+
+ switch (rsdp_table[15 /* Revision offset */]) {
+ case 0: /* ACPI 1.0 RSDP */
+ /* With rev 1, checksum is only for the first 20 bytes */
+ g_assert(!acpi_calc_checksum(rsdp_table, 20));
+ break;
+ case 2: /* ACPI 2.0+ RSDP */
+ /* With revision 2, we have 2 checksums */
+ g_assert(!acpi_calc_checksum(rsdp_table, 20));
+ g_assert(!acpi_calc_checksum(rsdp_table, 36));
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void test_acpi_rxsdt_table(test_data *data)
+{
+ const char *sig = "RSDT";
+ AcpiSdtTable rsdt = {};
+ int entry_size = 4;
+ int addr_off = 16 /* RsdtAddress */;
+ uint8_t *ent;
+
+ if (data->rsdp_table[15 /* Revision offset */] != 0) {
+ addr_off = 24 /* XsdtAddress */;
+ entry_size = 8;
+ sig = "XSDT";
+ }
+ /* read [RX]SDT table */
+ acpi_fetch_table(data->qts, &rsdt.aml, &rsdt.aml_len,
+ &data->rsdp_table[addr_off], entry_size, sig, true);
+
+ /* Load all tables and add to test list directly RSDT referenced tables */
+ ACPI_FOREACH_RSDT_ENTRY(rsdt.aml, rsdt.aml_len, ent, entry_size) {
+ AcpiSdtTable ssdt_table = {};
+
+ acpi_fetch_table(data->qts, &ssdt_table.aml, &ssdt_table.aml_len, ent,
+ entry_size, NULL, true);
+ /* Add table to ASL test tables list */
+ g_array_append_val(data->tables, ssdt_table);
+ }
+ cleanup_table_descriptor(&rsdt);
+}
+
+static void test_acpi_fadt_table(test_data *data)
+{
+ /* FADT table is 1st */
+ AcpiSdtTable table = g_array_index(data->tables, typeof(table), 0);
+ uint8_t *fadt_aml = table.aml;
+ uint32_t fadt_len = table.aml_len;
+ uint32_t val;
+ int dsdt_offset = 40 /* DSDT */;
+ int dsdt_entry_size = 4;
+
+ g_assert(compare_signature(&table, "FACP"));
+
+ /* Since DSDT/FACS isn't in RSDT, add them to ASL test list manually */
+ memcpy(&val, fadt_aml + 112 /* Flags */, 4);
+ val = le32_to_cpu(val);
+ if (!(val & 1UL << 20 /* HW_REDUCED_ACPI */)) {
+ acpi_fetch_table(data->qts, &table.aml, &table.aml_len,
+ fadt_aml + 36 /* FIRMWARE_CTRL */, 4, "FACS", false);
+ g_array_append_val(data->tables, table);
+ }
+
+ memcpy(&val, fadt_aml + dsdt_offset, 4);
+ val = le32_to_cpu(val);
+ if (!val) {
+ dsdt_offset = 140 /* X_DSDT */;
+ dsdt_entry_size = 8;
+ }
+ acpi_fetch_table(data->qts, &table.aml, &table.aml_len,
+ fadt_aml + dsdt_offset, dsdt_entry_size, "DSDT", true);
+ g_array_append_val(data->tables, table);
+
+ memset(fadt_aml + 36, 0, 4); /* sanitize FIRMWARE_CTRL ptr */
+ memset(fadt_aml + 40, 0, 4); /* sanitize DSDT ptr */
+ if (fadt_aml[8 /* FADT Major Version */] >= 3) {
+ memset(fadt_aml + 132, 0, 8); /* sanitize X_FIRMWARE_CTRL ptr */
+ memset(fadt_aml + 140, 0, 8); /* sanitize X_DSDT ptr */
+ }
+
+ /* update checksum */
+ fadt_aml[9 /* Checksum */] = 0;
+ fadt_aml[9 /* Checksum */] -= acpi_calc_checksum(fadt_aml, fadt_len);
+}
+
+static void dump_aml_files(test_data *data, bool rebuild)
+{
+ AcpiSdtTable *sdt;
+ GError *error = NULL;
+ gchar *aml_file = NULL;
+ gint fd;
+ ssize_t ret;
+ int i;
+
+ for (i = 0; i < data->tables->len; ++i) {
+ const char *ext = data->variant ? data->variant : "";
+ sdt = &g_array_index(data->tables, AcpiSdtTable, i);
+ g_assert(sdt->aml);
+
+ if (rebuild) {
+ aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine,
+ sdt->aml, ext);
+ fd = g_open(aml_file, O_WRONLY|O_TRUNC|O_CREAT,
+ S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH);
+ if (fd < 0) {
+ perror(aml_file);
+ }
+ g_assert(fd >= 0);
+ } else {
+ fd = g_file_open_tmp("aml-XXXXXX", &sdt->aml_file, &error);
+ g_assert_no_error(error);
+ }
+
+ ret = qemu_write_full(fd, sdt->aml, sdt->aml_len);
+ g_assert(ret == sdt->aml_len);
+
+ close(fd);
+
+ g_free(aml_file);
+ }
+}
+
+static bool load_asl(GArray *sdts, AcpiSdtTable *sdt)
+{
+ AcpiSdtTable *temp;
+ GError *error = NULL;
+ GString *command_line = g_string_new(iasl);
+ gint fd;
+ gchar *out, *out_err;
+ gboolean ret;
+ int i;
+
+ fd = g_file_open_tmp("asl-XXXXXX.dsl", &sdt->asl_file, &error);
+ g_assert_no_error(error);
+ close(fd);
+
+ /* build command line */
+ g_string_append_printf(command_line, " -p %s ", sdt->asl_file);
+ if (compare_signature(sdt, "DSDT") ||
+ compare_signature(sdt, "SSDT")) {
+ for (i = 0; i < sdts->len; ++i) {
+ temp = &g_array_index(sdts, AcpiSdtTable, i);
+ if (compare_signature(temp, "DSDT") ||
+ compare_signature(temp, "SSDT")) {
+ g_string_append_printf(command_line, "-e %s ", temp->aml_file);
+ }
+ }
+ }
+ g_string_append_printf(command_line, "-d %s", sdt->aml_file);
+
+ /* pass 'out' and 'out_err' in order to be redirected */
+ ret = g_spawn_command_line_sync(command_line->str, &out, &out_err, NULL, &error);
+ g_assert_no_error(error);
+ if (ret) {
+ ret = g_file_get_contents(sdt->asl_file, &sdt->asl,
+ &sdt->asl_len, &error);
+ g_assert(ret);
+ g_assert_no_error(error);
+ ret = (sdt->asl_len > 0);
+ }
+
+ g_free(out);
+ g_free(out_err);
+ g_string_free(command_line, true);
+
+ return !ret;
+}
+
+#define COMMENT_END "*/"
+#define DEF_BLOCK "DefinitionBlock ("
+#define BLOCK_NAME_END ","
+
+static GString *normalize_asl(gchar *asl_code)
+{
+ GString *asl = g_string_new(asl_code);
+ gchar *comment, *block_name;
+
+ /* strip comments (different generation days) */
+ comment = g_strstr_len(asl->str, asl->len, COMMENT_END);
+ if (comment) {
+ comment += strlen(COMMENT_END);
+ while (*comment == '\n') {
+ comment++;
+ }
+ asl = g_string_erase(asl, 0, comment - asl->str);
+ }
+
+ /* strip def block name (it has file path in it) */
+ if (g_str_has_prefix(asl->str, DEF_BLOCK)) {
+ block_name = g_strstr_len(asl->str, asl->len, BLOCK_NAME_END);
+ g_assert(block_name);
+ asl = g_string_erase(asl, 0,
+ block_name + sizeof(BLOCK_NAME_END) - asl->str);
+ }
+
+ return asl;
+}
+
+static GArray *load_expected_aml(test_data *data)
+{
+ int i;
+ AcpiSdtTable *sdt;
+ GError *error = NULL;
+ gboolean ret;
+ gsize aml_len;
+
+ GArray *exp_tables = g_array_new(false, true, sizeof(AcpiSdtTable));
+ if (getenv("V")) {
+ fputc('\n', stderr);
+ }
+ for (i = 0; i < data->tables->len; ++i) {
+ AcpiSdtTable exp_sdt;
+ gchar *aml_file = NULL;
+ const char *ext = data->variant ? data->variant : "";
+
+ sdt = &g_array_index(data->tables, AcpiSdtTable, i);
+
+ memset(&exp_sdt, 0, sizeof(exp_sdt));
+
+try_again:
+ aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine,
+ sdt->aml, ext);
+ if (getenv("V")) {
+ fprintf(stderr, "Looking for expected file '%s'\n", aml_file);
+ }
+ if (g_file_test(aml_file, G_FILE_TEST_EXISTS)) {
+ exp_sdt.aml_file = aml_file;
+ } else if (*ext != '\0') {
+ /* try fallback to generic (extension less) expected file */
+ ext = "";
+ g_free(aml_file);
+ goto try_again;
+ }
+ g_assert(exp_sdt.aml_file);
+ if (getenv("V")) {
+ fprintf(stderr, "Using expected file '%s'\n", aml_file);
+ }
+ ret = g_file_get_contents(aml_file, (gchar **)&exp_sdt.aml,
+ &aml_len, &error);
+ exp_sdt.aml_len = aml_len;
+ g_assert(ret);
+ g_assert_no_error(error);
+ g_assert(exp_sdt.aml);
+ if (!exp_sdt.aml_len) {
+ fprintf(stderr, "Warning! zero length expected file '%s'\n",
+ aml_file);
+ }
+
+ g_array_append_val(exp_tables, exp_sdt);
+ }
+
+ return exp_tables;
+}
+
+static bool test_acpi_find_diff_allowed(AcpiSdtTable *sdt)
+{
+ const gchar *allowed_diff_file[] = {
+#include "bios-tables-test-allowed-diff.h"
+ NULL
+ };
+ const gchar **f;
+
+ for (f = allowed_diff_file; *f; ++f) {
+ if (!g_strcmp0(sdt->aml_file, *f)) {
+ return true;
+ }
+ }
+ return false;
+}
+
+/* test the list of tables in @data->tables against reference tables */
+static void test_acpi_asl(test_data *data)
+{
+ int i;
+ AcpiSdtTable *sdt, *exp_sdt;
+ test_data exp_data;
+ gboolean exp_err, err, all_tables_match = true;
+
+ memset(&exp_data, 0, sizeof(exp_data));
+ exp_data.tables = load_expected_aml(data);
+ dump_aml_files(data, false);
+ for (i = 0; i < data->tables->len; ++i) {
+ GString *asl, *exp_asl;
+
+ sdt = &g_array_index(data->tables, AcpiSdtTable, i);
+ exp_sdt = &g_array_index(exp_data.tables, AcpiSdtTable, i);
+
+ if (sdt->aml_len == exp_sdt->aml_len &&
+ !memcmp(sdt->aml, exp_sdt->aml, sdt->aml_len)) {
+ /* Identical table binaries: no need to disassemble. */
+ continue;
+ }
+
+ fprintf(stderr,
+ "acpi-test: Warning! %.4s binary file mismatch. "
+ "Actual [aml:%s], Expected [aml:%s].\n"
+ "See source file tests/qtest/bios-tables-test.c "
+ "for instructions on how to update expected files.\n",
+ exp_sdt->aml, sdt->aml_file, exp_sdt->aml_file);
+
+ all_tables_match = all_tables_match &&
+ test_acpi_find_diff_allowed(exp_sdt);
+
+ /*
+ * don't try to decompile if IASL isn't present, in this case user
+ * will just 'get binary file mismatch' warnings and test failure
+ */
+ if (!iasl) {
+ continue;
+ }
+
+ err = load_asl(data->tables, sdt);
+ asl = normalize_asl(sdt->asl);
+
+ exp_err = load_asl(exp_data.tables, exp_sdt);
+ exp_asl = normalize_asl(exp_sdt->asl);
+
+ /* TODO: check for warnings */
+ g_assert(!err || exp_err);
+
+ if (g_strcmp0(asl->str, exp_asl->str)) {
+ sdt->tmp_files_retain = true;
+ if (exp_err) {
+ fprintf(stderr,
+ "Warning! iasl couldn't parse the expected aml\n");
+ } else {
+ exp_sdt->tmp_files_retain = true;
+ fprintf(stderr,
+ "acpi-test: Warning! %.4s mismatch. "
+ "Actual [asl:%s, aml:%s], Expected [asl:%s, aml:%s].\n",
+ exp_sdt->aml, sdt->asl_file, sdt->aml_file,
+ exp_sdt->asl_file, exp_sdt->aml_file);
+ fflush(stderr);
+ if (getenv("V")) {
+ const char *diff_env = getenv("DIFF");
+ const char *diff_cmd = diff_env ? diff_env : "diff -U 16";
+ char *diff = g_strdup_printf("%s %s %s", diff_cmd,
+ exp_sdt->asl_file, sdt->asl_file);
+ int out = dup(STDOUT_FILENO);
+ int ret G_GNUC_UNUSED;
+
+ dup2(STDERR_FILENO, STDOUT_FILENO);
+ ret = system(diff) ;
+ dup2(out, STDOUT_FILENO);
+ close(out);
+ g_free(diff);
+ }
+ }
+ }
+ g_string_free(asl, true);
+ g_string_free(exp_asl, true);
+ }
+ if (!iasl && !all_tables_match) {
+ fprintf(stderr, "to see ASL diff between mismatched files install IASL,"
+ " rebuild QEMU from scratch and re-run tests with V=1"
+ " environment variable set");
+ }
+ g_assert(all_tables_match);
+
+ free_test_data(&exp_data);
+}
+
+static bool smbios_ep_table_ok(test_data *data)
+{
+ struct smbios_21_entry_point *ep_table = &data->smbios_ep_table;
+ uint32_t addr = data->smbios_ep_addr;
+
+ qtest_memread(data->qts, addr, ep_table, sizeof(*ep_table));
+ if (memcmp(ep_table->anchor_string, "_SM_", 4)) {
+ return false;
+ }
+ if (memcmp(ep_table->intermediate_anchor_string, "_DMI_", 5)) {
+ return false;
+ }
+ if (ep_table->structure_table_length == 0) {
+ return false;
+ }
+ if (ep_table->number_of_structures == 0) {
+ return false;
+ }
+ if (acpi_calc_checksum((uint8_t *)ep_table, sizeof *ep_table) ||
+ acpi_calc_checksum((uint8_t *)ep_table + 0x10,
+ sizeof *ep_table - 0x10)) {
+ return false;
+ }
+ return true;
+}
+
+static void test_smbios_entry_point(test_data *data)
+{
+ uint32_t off;
+
+ /* find smbios entry point structure */
+ for (off = 0xf0000; off < 0x100000; off += 0x10) {
+ uint8_t sig[] = "_SM_";
+ int i;
+
+ for (i = 0; i < sizeof sig - 1; ++i) {
+ sig[i] = qtest_readb(data->qts, off + i);
+ }
+
+ if (!memcmp(sig, "_SM_", sizeof sig)) {
+ /* signature match, but is this a valid entry point? */
+ data->smbios_ep_addr = off;
+ if (smbios_ep_table_ok(data)) {
+ break;
+ }
+ }
+ }
+
+ g_assert_cmphex(off, <, 0x100000);
+}
+
+static inline bool smbios_single_instance(uint8_t type)
+{
+ switch (type) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 16:
+ case 32:
+ case 127:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool smbios_cpu_test(test_data *data, uint32_t addr)
+{
+ uint16_t expect_speed[2];
+ uint16_t real;
+ int offset[2];
+ int i;
+
+ /* Check CPU speed for backward compatibility */
+ offset[0] = offsetof(struct smbios_type_4, max_speed);
+ offset[1] = offsetof(struct smbios_type_4, current_speed);
+ expect_speed[0] = data->smbios_cpu_max_speed ? : 2000;
+ expect_speed[1] = data->smbios_cpu_curr_speed ? : 2000;
+
+ for (i = 0; i < 2; i++) {
+ real = qtest_readw(data->qts, addr + offset[i]);
+ if (real != expect_speed[i]) {
+ fprintf(stderr, "Unexpected SMBIOS CPU speed: real %u expect %u\n",
+ real, expect_speed[i]);
+ return false;
+ }
+ }
+
+ return true;
+}
+
+static void test_smbios_structs(test_data *data)
+{
+ DECLARE_BITMAP(struct_bitmap, SMBIOS_MAX_TYPE+1) = { 0 };
+ struct smbios_21_entry_point *ep_table = &data->smbios_ep_table;
+ uint32_t addr = le32_to_cpu(ep_table->structure_table_address);
+ int i, len, max_len = 0;
+ uint8_t type, prv, crt;
+
+ /* walk the smbios tables */
+ for (i = 0; i < le16_to_cpu(ep_table->number_of_structures); i++) {
+
+ /* grab type and formatted area length from struct header */
+ type = qtest_readb(data->qts, addr);
+ g_assert_cmpuint(type, <=, SMBIOS_MAX_TYPE);
+ len = qtest_readb(data->qts, addr + 1);
+
+ /* single-instance structs must not have been encountered before */
+ if (smbios_single_instance(type)) {
+ g_assert(!test_bit(type, struct_bitmap));
+ }
+ set_bit(type, struct_bitmap);
+
+ if (type == 4) {
+ g_assert(smbios_cpu_test(data, addr));
+ }
+
+ /* seek to end of unformatted string area of this struct ("\0\0") */
+ prv = crt = 1;
+ while (prv || crt) {
+ prv = crt;
+ crt = qtest_readb(data->qts, addr + len);
+ len++;
+ }
+
+ /* keep track of max. struct size */
+ if (max_len < len) {
+ max_len = len;
+ g_assert_cmpuint(max_len, <=, ep_table->max_structure_size);
+ }
+
+ /* start of next structure */
+ addr += len;
+ }
+
+ /* total table length and max struct size must match entry point values */
+ g_assert_cmpuint(le16_to_cpu(ep_table->structure_table_length), ==,
+ addr - le32_to_cpu(ep_table->structure_table_address));
+ g_assert_cmpuint(le16_to_cpu(ep_table->max_structure_size), ==, max_len);
+
+ /* required struct types must all be present */
+ for (i = 0; i < data->required_struct_types_len; i++) {
+ g_assert(test_bit(data->required_struct_types[i], struct_bitmap));
+ }
+}
+
+static void test_acpi_one(const char *params, test_data *data)
+{
+ char *args;
+ bool use_uefi = data->uefi_fl1 && data->uefi_fl2;
+
+ if (use_uefi) {
+ /*
+ * TODO: convert '-drive if=pflash' to new syntax (see e33763be7cd3)
+ * when arm/virt boad starts to support it.
+ */
+ args = g_strdup_printf("-machine %s %s -accel tcg -nodefaults -nographic "
+ "-drive if=pflash,format=raw,file=%s,readonly "
+ "-drive if=pflash,format=raw,file=%s,snapshot=on -cdrom %s %s",
+ data->machine, data->tcg_only ? "" : "-accel kvm",
+ data->uefi_fl1, data->uefi_fl2, data->cd, params ? params : "");
+
+ } else {
+ /* Disable kernel irqchip to be able to override apic irq0. */
+ args = g_strdup_printf("-machine %s,kernel-irqchip=off %s -accel tcg "
+ "-net none -display none %s "
+ "-drive id=hd0,if=none,file=%s,format=raw "
+ "-device ide-hd,drive=hd0 ",
+ data->machine, data->tcg_only ? "" : "-accel kvm",
+ params ? params : "", disk);
+ }
+
+ data->qts = qtest_init(args);
+
+ if (use_uefi) {
+ g_assert(data->scan_len);
+ data->rsdp_addr = acpi_find_rsdp_address_uefi(data->qts,
+ data->ram_start, data->scan_len);
+ } else {
+ boot_sector_test(data->qts);
+ data->rsdp_addr = acpi_find_rsdp_address(data->qts);
+ g_assert_cmphex(data->rsdp_addr, <, 0x100000);
+ }
+
+ data->tables = g_array_new(false, true, sizeof(AcpiSdtTable));
+ test_acpi_rsdp_table(data);
+ test_acpi_rxsdt_table(data);
+ test_acpi_fadt_table(data);
+
+ if (getenv(ACPI_REBUILD_EXPECTED_AML)) {
+ dump_aml_files(data, true);
+ } else {
+ test_acpi_asl(data);
+ }
+
+ /*
+ * TODO: make SMBIOS tests work with UEFI firmware,
+ * Bug on uefi-test-tools to provide entry point:
+ * https://bugs.launchpad.net/qemu/+bug/1821884
+ */
+ if (!use_uefi) {
+ test_smbios_entry_point(data);
+ test_smbios_structs(data);
+ }
+
+ qtest_quit(data->qts);
+ g_free(args);
+}
+
+static uint8_t base_required_struct_types[] = {
+ 0, 1, 3, 4, 16, 17, 19, 32, 127
+};
+
+static void test_acpi_piix4_tcg(void)
+{
+ test_data data;
+
+ /* Supplying -machine accel argument overrides the default (qtest).
+ * This is to make guest actually run.
+ */
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
+ test_acpi_one(NULL, &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_piix4_tcg_bridge(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+ data.variant = ".bridge";
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
+ test_acpi_one("-device pci-bridge,chassis_nr=1", &data);
+ free_test_data(&data);
+}
+
+<<<<<<< HEAD
+static void test_acpi_piix4_bridge_hotplug(void)
+=======
+static void test_acpi_piix4_root_hotplug(void)
+>>>>>>> tests/acpi: add a new unit test to test hotplug off/on feature on the root pci bus
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+<<<<<<< HEAD
+ data.variant = ".hpbridge";
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
+ test_acpi_one("-global PIIX4_PM.acpi-pci-hotplug-with-bridge-support=off "
+ "-device pci-bridge,chassis_nr=1", &data);
+=======
+ data.variant = ".roothp";
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
+ test_acpi_one("-global PIIX4_PM.acpi-root-pci-hotplug=off", &data);
+>>>>>>> tests/acpi: add a new unit test to test hotplug off/on feature on the root pci bus
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
+ test_acpi_one(NULL, &data);
+ free_test_data(&data);
+
+ data.smbios_cpu_max_speed = 3000;
+ data.smbios_cpu_curr_speed = 2600;
+ test_acpi_one("-smbios type=4,max-speed=3000,current-speed=2600", &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_bridge(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.variant = ".bridge";
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
+ test_acpi_one("-device pci-bridge,chassis_nr=1",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_mmio64(void)
+{
+ test_data data = {
+ .machine = MACHINE_Q35,
+ .variant = ".mmio64",
+ .required_struct_types = base_required_struct_types,
+ .required_struct_types_len = ARRAY_SIZE(base_required_struct_types)
+ };
+
+ test_acpi_one("-m 128M,slots=1,maxmem=2G "
+ "-object memory-backend-ram,id=ram0,size=128M "
+ "-numa node,memdev=ram0 "
+ "-device pci-testdev,membar=2G",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_piix4_tcg_cphp(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+ data.variant = ".cphp";
+ test_acpi_one("-smp 2,cores=3,sockets=2,maxcpus=6"
+ " -object memory-backend-ram,id=ram0,size=64M"
+ " -object memory-backend-ram,id=ram1,size=64M"
+ " -numa node,memdev=ram0 -numa node,memdev=ram1"
+ " -numa dist,src=0,dst=1,val=21",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_cphp(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.variant = ".cphp";
+ test_acpi_one(" -smp 2,cores=3,sockets=2,maxcpus=6"
+ " -object memory-backend-ram,id=ram0,size=64M"
+ " -object memory-backend-ram,id=ram1,size=64M"
+ " -numa node,memdev=ram0 -numa node,memdev=ram1"
+ " -numa dist,src=0,dst=1,val=21",
+ &data);
+ free_test_data(&data);
+}
+
+static uint8_t ipmi_required_struct_types[] = {
+ 0, 1, 3, 4, 16, 17, 19, 32, 38, 127
+};
+
+static void test_acpi_q35_tcg_ipmi(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.variant = ".ipmibt";
+ data.required_struct_types = ipmi_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types);
+ test_acpi_one("-device ipmi-bmc-sim,id=bmc0"
+ " -device isa-ipmi-bt,bmc=bmc0",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_piix4_tcg_ipmi(void)
+{
+ test_data data;
+
+ /* Supplying -machine accel argument overrides the default (qtest).
+ * This is to make guest actually run.
+ */
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+ data.variant = ".ipmikcs";
+ data.required_struct_types = ipmi_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types);
+ test_acpi_one("-device ipmi-bmc-sim,id=bmc0"
+ " -device isa-ipmi-kcs,irq=0,bmc=bmc0",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_memhp(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.variant = ".memhp";
+ test_acpi_one(" -m 128,slots=3,maxmem=1G"
+ " -object memory-backend-ram,id=ram0,size=64M"
+ " -object memory-backend-ram,id=ram1,size=64M"
+ " -numa node,memdev=ram0 -numa node,memdev=ram1"
+ " -numa dist,src=0,dst=1,val=21",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_piix4_tcg_memhp(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+ data.variant = ".memhp";
+ test_acpi_one(" -m 128,slots=3,maxmem=1G"
+ " -object memory-backend-ram,id=ram0,size=64M"
+ " -object memory-backend-ram,id=ram1,size=64M"
+ " -numa node,memdev=ram0 -numa node,memdev=ram1"
+ " -numa dist,src=0,dst=1,val=21",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_numamem(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.variant = ".numamem";
+ test_acpi_one(" -object memory-backend-ram,id=ram0,size=128M"
+ " -numa node -numa node,memdev=ram0", &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_piix4_tcg_numamem(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+ data.variant = ".numamem";
+ test_acpi_one(" -object memory-backend-ram,id=ram0,size=128M"
+ " -numa node -numa node,memdev=ram0", &data);
+ free_test_data(&data);
+}
+
+uint64_t tpm_tis_base_addr;
+
+static void test_acpi_tcg_tpm(const char *machine, const char *tpm_if,
+ uint64_t base)
+{
+#ifdef CONFIG_TPM
+ gchar *tmp_dir_name = g_strdup_printf("qemu-test_acpi_%s_tcg_%s.XXXXXX",
+ machine, tpm_if);
+ char *tmp_path = g_dir_make_tmp(tmp_dir_name, NULL);
+ TestState test;
+ test_data data;
+ GThread *thread;
+ char *args, *variant = g_strdup_printf(".%s", tpm_if);
+
+ tpm_tis_base_addr = base;
+
+ module_call_init(MODULE_INIT_QOM);
+
+ test.addr = g_new0(SocketAddress, 1);
+ test.addr->type = SOCKET_ADDRESS_TYPE_UNIX;
+ test.addr->u.q_unix.path = g_build_filename(tmp_path, "sock", NULL);
+ g_mutex_init(&test.data_mutex);
+ g_cond_init(&test.data_cond);
+ test.data_cond_signal = false;
+
+ thread = g_thread_new(NULL, tpm_emu_ctrl_thread, &test);
+ tpm_emu_test_wait_cond(&test);
+
+ memset(&data, 0, sizeof(data));
+ data.machine = machine;
+ data.variant = variant;
+
+ args = g_strdup_printf(
+ " -chardev socket,id=chr,path=%s"
+ " -tpmdev emulator,id=dev,chardev=chr"
+ " -device tpm-%s,tpmdev=dev",
+ test.addr->u.q_unix.path, tpm_if);
+
+ test_acpi_one(args, &data);
+
+ g_thread_join(thread);
+ g_unlink(test.addr->u.q_unix.path);
+ qapi_free_SocketAddress(test.addr);
+ g_rmdir(tmp_path);
+ g_free(variant);
+ g_free(tmp_path);
+ g_free(tmp_dir_name);
+ g_free(args);
+ free_test_data(&data);
+#else
+ g_test_skip("TPM disabled");
+#endif
+}
+
+static void test_acpi_q35_tcg_tpm_tis(void)
+{
+ test_acpi_tcg_tpm("q35", "tis", 0xFED40000);
+}
+
+static void test_acpi_tcg_dimm_pxm(const char *machine)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = machine;
+ data.variant = ".dimmpxm";
+ test_acpi_one(" -machine nvdimm=on,nvdimm-persistence=cpu"
+ " -smp 4,sockets=4"
+ " -m 128M,slots=3,maxmem=1G"
+ " -object memory-backend-ram,id=ram0,size=32M"
+ " -object memory-backend-ram,id=ram1,size=32M"
+ " -object memory-backend-ram,id=ram2,size=32M"
+ " -object memory-backend-ram,id=ram3,size=32M"
+ " -numa node,memdev=ram0,nodeid=0"
+ " -numa node,memdev=ram1,nodeid=1"
+ " -numa node,memdev=ram2,nodeid=2"
+ " -numa node,memdev=ram3,nodeid=3"
+ " -numa cpu,node-id=0,socket-id=0"
+ " -numa cpu,node-id=1,socket-id=1"
+ " -numa cpu,node-id=2,socket-id=2"
+ " -numa cpu,node-id=3,socket-id=3"
+ " -object memory-backend-ram,id=ram4,size=128M"
+ " -object memory-backend-ram,id=nvm0,size=128M"
+ " -device pc-dimm,id=dimm0,memdev=ram4,node=1"
+ " -device nvdimm,id=dimm1,memdev=nvm0,node=2",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_dimm_pxm(void)
+{
+ test_acpi_tcg_dimm_pxm(MACHINE_Q35);
+}
+
+static void test_acpi_piix4_tcg_dimm_pxm(void)
+{
+ test_acpi_tcg_dimm_pxm(MACHINE_PC);
+}
+
+static void test_acpi_virt_tcg_memhp(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
+ .ram_start = 0x40000000ULL,
+ .scan_len = 256ULL * 1024 * 1024,
+ };
+
+ data.variant = ".memhp";
+ test_acpi_one(" -machine nvdimm=on"
+ " -cpu cortex-a57"
+ " -m 256M,slots=3,maxmem=1G"
+ " -object memory-backend-ram,id=ram0,size=128M"
+ " -object memory-backend-ram,id=ram1,size=128M"
+ " -numa node,memdev=ram0 -numa node,memdev=ram1"
+ " -numa dist,src=0,dst=1,val=21"
+ " -object memory-backend-ram,id=ram2,size=128M"
+ " -object memory-backend-ram,id=nvm0,size=128M"
+ " -device pc-dimm,id=dimm0,memdev=ram2,node=0"
+ " -device nvdimm,id=dimm1,memdev=nvm0,node=1",
+ &data);
+
+ free_test_data(&data);
+
+}
+
+static void test_acpi_virt_tcg_numamem(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
+ .ram_start = 0x40000000ULL,
+ .scan_len = 128ULL * 1024 * 1024,
+ };
+
+ data.variant = ".numamem";
+ test_acpi_one(" -cpu cortex-a57"
+ " -object memory-backend-ram,id=ram0,size=128M"
+ " -numa node,memdev=ram0",
+ &data);
+
+ free_test_data(&data);
+
+}
+
+static void test_acpi_tcg_acpi_hmat(const char *machine)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = machine;
+ data.variant = ".acpihmat";
+ test_acpi_one(" -machine hmat=on"
+ " -smp 2,sockets=2"
+ " -m 128M,slots=2,maxmem=1G"
+ " -object memory-backend-ram,size=64M,id=m0"
+ " -object memory-backend-ram,size=64M,id=m1"
+ " -numa node,nodeid=0,memdev=m0"
+ " -numa node,nodeid=1,memdev=m1,initiator=0"
+ " -numa cpu,node-id=0,socket-id=0"
+ " -numa cpu,node-id=0,socket-id=1"
+ " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+ "data-type=access-latency,latency=1"
+ " -numa hmat-lb,initiator=0,target=0,hierarchy=memory,"
+ "data-type=access-bandwidth,bandwidth=65534M"
+ " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+ "data-type=access-latency,latency=65534"
+ " -numa hmat-lb,initiator=0,target=1,hierarchy=memory,"
+ "data-type=access-bandwidth,bandwidth=32767M"
+ " -numa hmat-cache,node-id=0,size=10K,level=1,"
+ "associativity=direct,policy=write-back,line=8"
+ " -numa hmat-cache,node-id=1,size=10K,level=1,"
+ "associativity=direct,policy=write-back,line=8",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_q35_tcg_acpi_hmat(void)
+{
+ test_acpi_tcg_acpi_hmat(MACHINE_Q35);
+}
+
+static void test_acpi_piix4_tcg_acpi_hmat(void)
+{
+ test_acpi_tcg_acpi_hmat(MACHINE_PC);
+}
+
+static void test_acpi_virt_tcg(void)
+{
+ test_data data = {
+ .machine = "virt",
+ .tcg_only = true,
+ .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd",
+ .uefi_fl2 = "pc-bios/edk2-arm-vars.fd",
+ .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2",
+ .ram_start = 0x40000000ULL,
+ .scan_len = 128ULL * 1024 * 1024,
+ };
+
+ test_acpi_one("-cpu cortex-a57", &data);
+ free_test_data(&data);
+
+ data.smbios_cpu_max_speed = 2900;
+ data.smbios_cpu_curr_speed = 2700;
+ test_acpi_one("-cpu cortex-a57 "
+ "-smbios type=4,max-speed=2900,current-speed=2700", &data);
+ free_test_data(&data);
+}
+
+int main(int argc, char *argv[])
+{
+ const char *arch = qtest_get_arch();
+ int ret;
+
+ g_test_init(&argc, &argv, NULL);
+
+ if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
+ ret = boot_sector_init(disk);
+ if (ret) {
+ return ret;
+ }
+
+ qtest_add_func("acpi/q35/tpm-tis", test_acpi_q35_tcg_tpm_tis);
+ qtest_add_func("acpi/piix4", test_acpi_piix4_tcg);
+ qtest_add_func("acpi/piix4/bridge", test_acpi_piix4_tcg_bridge);
+<<<<<<< HEAD
+ qtest_add_func("acpi/piix4/brhotplug", test_acpi_piix4_bridge_hotplug);
+=======
+ qtest_add_func("acpi/piix4/hotplug", test_acpi_piix4_root_hotplug);
+>>>>>>> tests/acpi: add a new unit test to test hotplug off/on feature on the root pci bus
+ qtest_add_func("acpi/q35", test_acpi_q35_tcg);
+ qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge);
+ qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64);
+ qtest_add_func("acpi/piix4/ipmi", test_acpi_piix4_tcg_ipmi);
+ qtest_add_func("acpi/q35/ipmi", test_acpi_q35_tcg_ipmi);
+ qtest_add_func("acpi/piix4/cpuhp", test_acpi_piix4_tcg_cphp);
+ qtest_add_func("acpi/q35/cpuhp", test_acpi_q35_tcg_cphp);
+ qtest_add_func("acpi/piix4/memhp", test_acpi_piix4_tcg_memhp);
+ qtest_add_func("acpi/q35/memhp", test_acpi_q35_tcg_memhp);
+ qtest_add_func("acpi/piix4/numamem", test_acpi_piix4_tcg_numamem);
+ qtest_add_func("acpi/q35/numamem", test_acpi_q35_tcg_numamem);
+ qtest_add_func("acpi/piix4/dimmpxm", test_acpi_piix4_tcg_dimm_pxm);
+ qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm);
+ qtest_add_func("acpi/piix4/acpihmat", test_acpi_piix4_tcg_acpi_hmat);
+ qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_tcg_acpi_hmat);
+ } else if (strcmp(arch, "aarch64") == 0) {
+ qtest_add_func("acpi/virt", test_acpi_virt_tcg);
+ qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem);
+ qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp);
+ }
+ ret = g_test_run();
+ boot_sector_cleanup(disk);
+ return ret;
+}
new file mode 100644
@@ -0,0 +1,22 @@
+--- tests/qtest/bios-tables-test.c
++++ tests/qtest/bios-tables-test.c
+@@ -927,12 +927,17 @@ static void test_acpi_virt_tcg_memhp(void)
+ };
+ 20
+ data.variant =3D ".memhp";
+- test_acpi_one(" -cpu cortex-a57"
++ test_acpi_one(" -machine nvdimm=3Don"
++ " -cpu cortex-a57"
+ " -m 256M,slots=3D3,maxmem=3D1G"
+ " -object memory-backend-ram,id=3Dram0,size=3D128M"
+ " -object memory-backend-ram,id=3Dram1,size=3D128M"
+ " -numa node,memdev=3Dram0 -numa node,memdev=3Dram1"
+- " -numa dist,src=3D0,dst=3D1,val=3D21",
++ " -numa dist,src=3D0,dst=3D1,val=3D21"
++ " -object memory-backend-ram,id=3Dram2,size=3D128M"
++ " -object memory-backend-ram,id=3Dnvm0,size=3D128M"
++ " -device pc-dimm,id=3Ddimm0,memdev=3Dram2,node=3D0"
++ " -device nvdimm,id=3Ddimm1,memdev=3Dnvm0,node=3D1",
+ &data);
+ 20
+ free_test_data(&data);
new file mode 100755
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HcmV?d00001
new file mode 100644
@@ -0,0 +1,1432 @@
+/*
+ * Vhost User Bridge
+ *
+ * Copyright (c) 2015 Red Hat, Inc.
+ *
+ * Authors:
+ * Victor Kaplansky <victork@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
+ */
+
+/*
+ * TODO:
+ * - main should get parameters from the command line.
+ * - implement all request handlers. Still not implemented:
+ * vubr_get_queue_num_exec()
+ * vubr_send_rarp_exec()
+ * - test for broken requests and virtqueue.
+ * - implement features defined by Virtio 1.0 spec.
+ * - support mergeable buffers and indirect descriptors.
+ * - implement clean shutdown.
+ * - implement non-blocking writes to UDP backend.
+ * - implement polling strategy.
+ * - implement clean starting/stopping of vq processing
+ * - implement clean starting/stopping of used and buffers
+ * dirty page logging.
+ */
+
+#define _FILE_OFFSET_BITS 64
+
+#include "qemu/osdep.h"
+#include <sys/socket.h>
+#include <sys/un.h>
+#include <sys/unistd.h>
+#include <sys/mman.h>
+#include <sys/eventfd.h>
+#include <arpa/inet.h>
+#include <netdb.h>
+#include <qemu/osdep.h>
+
+#include <linux/vhost.h>
+
+#include "qemu/atomic.h"
+#include "standard-headers/linux/virtio_net.h"
+#include "standard-headers/linux/virtio_ring.h"
+
+#define VHOST_USER_BRIDGE_DEBUG 1
+
+#define DPRINT(...) \
+ do { \
+ if (VHOST_USER_BRIDGE_DEBUG) { \
+ printf(__VA_ARGS__); \
+ } \
+ } while (0)
+
+typedef void (*CallbackFunc)(int sock, void *ctx);
+
+typedef struct Event {
+ void *ctx;
+ CallbackFunc callback;
+} Event;
+
+typedef struct Dispatcher {
+ int max_sock;
+ fd_set fdset;
+ Event events[FD_SETSIZE];
+} Dispatcher;
+
+static void
+vubr_die(const char *s)
+{
+ perror(s);
+ exit(1);
+}
+
+static int
+dispatcher_init(Dispatcher *dispr)
+{
+ FD_ZERO(&dispr->fdset);
+ dispr->max_sock = -1;
+ return 0;
+}
+
+static int
+dispatcher_add(Dispatcher *dispr, int sock, void *ctx, CallbackFunc cb)
+{
+ if (sock >= FD_SETSIZE) {
+ fprintf(stderr,
+ "Error: Failed to add new event. sock %d should be less than %d\n",
+ sock, FD_SETSIZE);
+ return -1;
+ }
+
+ dispr->events[sock].ctx = ctx;
+ dispr->events[sock].callback = cb;
+
+ FD_SET(sock, &dispr->fdset);
+ if (sock > dispr->max_sock) {
+ dispr->max_sock = sock;
+ }
+ DPRINT("Added sock %d for watching. max_sock: %d\n",
+ sock, dispr->max_sock);
+ return 0;
+}
+
+/* dispatcher_remove() is not currently in use but may be useful
+ * in the future. */
+static int
+dispatcher_remove(Dispatcher *dispr, int sock)
+{
+ if (sock >= FD_SETSIZE) {
+ fprintf(stderr,
+ "Error: Failed to remove event. sock %d should be less than %d\n",
+ sock, FD_SETSIZE);
+ return -1;
+ }
+
+ FD_CLR(sock, &dispr->fdset);
+ DPRINT("Sock %d removed from dispatcher watch.\n", sock);
+ return 0;
+}
+
+/* timeout in us */
+static int
+dispatcher_wait(Dispatcher *dispr, uint32_t timeout)
+{
+ struct timeval tv;
+ tv.tv_sec = timeout / 1000000;
+ tv.tv_usec = timeout % 1000000;
+
+ fd_set fdset = dispr->fdset;
+
+ /* wait until some of sockets become readable. */
+ int rc = select(dispr->max_sock + 1, &fdset, 0, 0, &tv);
+
+ if (rc == -1) {
+ vubr_die("select");
+ }
+
+ /* Timeout */
+ if (rc == 0) {
+ return 0;
+ }
+
+ /* Now call callback for every ready socket. */
+
+ int sock;
+ for (sock = 0; sock < dispr->max_sock + 1; sock++) {
+ /* The callback on a socket can remove other sockets from the
+ * dispatcher, thus we have to check that the socket is
+ * still not removed from dispatcher's list
+ */
+ if (FD_ISSET(sock, &fdset) && FD_ISSET(sock, &dispr->fdset)) {
+ Event *e = &dispr->events[sock];
+ e->callback(sock, e->ctx);
+ }
+ }
+
+ return 0;
+}
+
+typedef struct VubrVirtq {
+ int call_fd;
+ int kick_fd;
+ uint32_t size;
+ uint16_t last_avail_index;
+ uint16_t last_used_index;
+ struct vring_desc *desc;
+ struct vring_avail *avail;
+ struct vring_used *used;
+ uint64_t log_guest_addr;
+ int enable;
+} VubrVirtq;
+
+/* Based on qemu/hw/virtio/vhost-user.c */
+
+#define VHOST_MEMORY_MAX_NREGIONS 8
+#define VHOST_USER_F_PROTOCOL_FEATURES 30
+/* v1.0 compliant. */
+#define VIRTIO_F_VERSION_1 32
+
+#define VHOST_LOG_PAGE 4096
+
+enum VhostUserProtocolFeature {
+ VHOST_USER_PROTOCOL_F_MQ = 0,
+ VHOST_USER_PROTOCOL_F_LOG_SHMFD = 1,
+ VHOST_USER_PROTOCOL_F_RARP = 2,
+
+ VHOST_USER_PROTOCOL_F_MAX
+};
+
+#define VHOST_USER_PROTOCOL_FEATURE_MASK ((1 << VHOST_USER_PROTOCOL_F_MAX) - 1)
+
+typedef enum VhostUserRequest {
+ VHOST_USER_NONE = 0,
+ VHOST_USER_GET_FEATURES = 1,
+ VHOST_USER_SET_FEATURES = 2,
+ VHOST_USER_SET_OWNER = 3,
+ VHOST_USER_RESET_OWNER = 4,
+ VHOST_USER_SET_MEM_TABLE = 5,
+ VHOST_USER_SET_LOG_BASE = 6,
+ VHOST_USER_SET_LOG_FD = 7,
+ VHOST_USER_SET_VRING_NUM = 8,
+ VHOST_USER_SET_VRING_ADDR = 9,
+ VHOST_USER_SET_VRING_BASE = 10,
+ VHOST_USER_GET_VRING_BASE = 11,
+ VHOST_USER_SET_VRING_KICK = 12,
+ VHOST_USER_SET_VRING_CALL = 13,
+ VHOST_USER_SET_VRING_ERR = 14,
+ VHOST_USER_GET_PROTOCOL_FEATURES = 15,
+ VHOST_USER_SET_PROTOCOL_FEATURES = 16,
+ VHOST_USER_GET_QUEUE_NUM = 17,
+ VHOST_USER_SET_VRING_ENABLE = 18,
+ VHOST_USER_SEND_RARP = 19,
+ VHOST_USER_MAX
+} VhostUserRequest;
+
+typedef struct VhostUserMemoryRegion {
+ uint64_t guest_phys_addr;
+ uint64_t memory_size;
+ uint64_t userspace_addr;
+ uint64_t mmap_offset;
+} VhostUserMemoryRegion;
+
+typedef struct VhostUserMemory {
+ uint32_t nregions;
+ uint32_t padding;
+ VhostUserMemoryRegion regions[VHOST_MEMORY_MAX_NREGIONS];
+} VhostUserMemory;
+
+typedef struct VhostUserLog {
+ uint64_t mmap_size;
+ uint64_t mmap_offset;
+} VhostUserLog;
+
+typedef struct VhostUserMsg {
+ VhostUserRequest request;
+
+#define VHOST_USER_VERSION_MASK (0x3)
+#define VHOST_USER_REPLY_MASK (0x1<<2)
+ uint32_t flags;
+ uint32_t size; /* the following payload size */
+ union {
+#define VHOST_USER_VRING_IDX_MASK (0xff)
+#define VHOST_USER_VRING_NOFD_MASK (0x1<<8)
+ uint64_t u64;
+ struct vhost_vring_state state;
+ struct vhost_vring_addr addr;
+ VhostUserMemory memory;
+ VhostUserLog log;
+ } payload;
+ int fds[VHOST_MEMORY_MAX_NREGIONS];
+ int fd_num;
+} QEMU_PACKED VhostUserMsg;
+
+#define VHOST_USER_HDR_SIZE offsetof(VhostUserMsg, payload.u64)
+
+/* The version of the protocol we support */
+#define VHOST_USER_VERSION (0x1)
+
+#define MAX_NR_VIRTQUEUE (8)
+
+typedef struct VubrDevRegion {
+ /* Guest Physical address. */
+ uint64_t gpa;
+ /* Memory region size. */
+ uint64_t size;
+ /* QEMU virtual address (userspace). */
+ uint64_t qva;
+ /* Starting offset in our mmaped space. */
+ uint64_t mmap_offset;
+ /* Start address of mmaped space. */
+ uint64_t mmap_addr;
+} VubrDevRegion;
+
+typedef struct VubrDev {
+ int sock;
+ Dispatcher dispatcher;
+ uint32_t nregions;
+ VubrDevRegion regions[VHOST_MEMORY_MAX_NREGIONS];
+ VubrVirtq vq[MAX_NR_VIRTQUEUE];
+ int log_call_fd;
+ uint64_t log_size;
+ uint8_t *log_table;
+ int backend_udp_sock;
+ struct sockaddr_in backend_udp_dest;
+ int ready;
+ uint64_t features;
+ int hdrlen;
+} VubrDev;
+
+static const char *vubr_request_str[] = {
+ [VHOST_USER_NONE] = "VHOST_USER_NONE",
+ [VHOST_USER_GET_FEATURES] = "VHOST_USER_GET_FEATURES",
+ [VHOST_USER_SET_FEATURES] = "VHOST_USER_SET_FEATURES",
+ [VHOST_USER_SET_OWNER] = "VHOST_USER_SET_OWNER",
+ [VHOST_USER_RESET_OWNER] = "VHOST_USER_RESET_OWNER",
+ [VHOST_USER_SET_MEM_TABLE] = "VHOST_USER_SET_MEM_TABLE",
+ [VHOST_USER_SET_LOG_BASE] = "VHOST_USER_SET_LOG_BASE",
+ [VHOST_USER_SET_LOG_FD] = "VHOST_USER_SET_LOG_FD",
+ [VHOST_USER_SET_VRING_NUM] = "VHOST_USER_SET_VRING_NUM",
+ [VHOST_USER_SET_VRING_ADDR] = "VHOST_USER_SET_VRING_ADDR",
+ [VHOST_USER_SET_VRING_BASE] = "VHOST_USER_SET_VRING_BASE",
+ [VHOST_USER_GET_VRING_BASE] = "VHOST_USER_GET_VRING_BASE",
+ [VHOST_USER_SET_VRING_KICK] = "VHOST_USER_SET_VRING_KICK",
+ [VHOST_USER_SET_VRING_CALL] = "VHOST_USER_SET_VRING_CALL",
+ [VHOST_USER_SET_VRING_ERR] = "VHOST_USER_SET_VRING_ERR",
+ [VHOST_USER_GET_PROTOCOL_FEATURES] = "VHOST_USER_GET_PROTOCOL_FEATURES",
+ [VHOST_USER_SET_PROTOCOL_FEATURES] = "VHOST_USER_SET_PROTOCOL_FEATURES",
+ [VHOST_USER_GET_QUEUE_NUM] = "VHOST_USER_GET_QUEUE_NUM",
+ [VHOST_USER_SET_VRING_ENABLE] = "VHOST_USER_SET_VRING_ENABLE",
+ [VHOST_USER_SEND_RARP] = "VHOST_USER_SEND_RARP",
+ [VHOST_USER_MAX] = "VHOST_USER_MAX",
+};
+
+static void
+print_buffer(uint8_t *buf, size_t len)
+{
+ int i;
+ printf("Raw buffer:\n");
+ for (i = 0; i < len; i++) {
+ if (i % 16 == 0) {
+ printf("\n");
+ }
+ if (i % 4 == 0) {
+ printf(" ");
+ }
+ printf("%02x ", buf[i]);
+ }
+ printf("\n............................................................\n");
+}
+
+/* Translate guest physical address to our virtual address. */
+static uint64_t
+gpa_to_va(VubrDev *dev, uint64_t guest_addr)
+{
+ int i;
+
+ /* Find matching memory region. */
+ for (i = 0; i < dev->nregions; i++) {
+ VubrDevRegion *r = &dev->regions[i];
+
+ if ((guest_addr >= r->gpa) && (guest_addr < (r->gpa + r->size))) {
+ return guest_addr - r->gpa + r->mmap_addr + r->mmap_offset;
+ }
+ }
+
+ assert(!"address not found in regions");
+ return 0;
+}
+
+/* Translate qemu virtual address to our virtual address. */
+static uint64_t
+qva_to_va(VubrDev *dev, uint64_t qemu_addr)
+{
+ int i;
+
+ /* Find matching memory region. */
+ for (i = 0; i < dev->nregions; i++) {
+ VubrDevRegion *r = &dev->regions[i];
+
+ if ((qemu_addr >= r->qva) && (qemu_addr < (r->qva + r->size))) {
+ return qemu_addr - r->qva + r->mmap_addr + r->mmap_offset;
+ }
+ }
+
+ assert(!"address not found in regions");
+ return 0;
+}
+
+static void
+vubr_message_read(int conn_fd, VhostUserMsg *vmsg)
+{
+ char control[CMSG_SPACE(VHOST_MEMORY_MAX_NREGIONS * sizeof(int))] = { };
+ struct iovec iov = {
+ .iov_base = (char *)vmsg,
+ .iov_len = VHOST_USER_HDR_SIZE,
+ };
+ struct msghdr msg = {
+ .msg_iov = &iov,
+ .msg_iovlen = 1,
+ .msg_control = control,
+ .msg_controllen = sizeof(control),
+ };
+ size_t fd_size;
+ struct cmsghdr *cmsg;
+ int rc;
+
+ rc = recvmsg(conn_fd, &msg, 0);
+
+ if (rc == 0) {
+ vubr_die("recvmsg");
+ fprintf(stderr, "Peer disconnected.\n");
+ exit(1);
+ }
+ if (rc < 0) {
+ vubr_die("recvmsg");
+ }
+
+ vmsg->fd_num = 0;
+ for (cmsg = CMSG_FIRSTHDR(&msg);
+ cmsg != NULL;
+ cmsg = CMSG_NXTHDR(&msg, cmsg))
+ {
+ if (cmsg->cmsg_level == SOL_SOCKET && cmsg->cmsg_type == SCM_RIGHTS) {
+ fd_size = cmsg->cmsg_len - CMSG_LEN(0);
+ vmsg->fd_num = fd_size / sizeof(int);
+ memcpy(vmsg->fds, CMSG_DATA(cmsg), fd_size);
+ break;
+ }
+ }
+
+ if (vmsg->size > sizeof(vmsg->payload)) {
+ fprintf(stderr,
+ "Error: too big message request: %d, size: vmsg->size: %u, "
+ "while sizeof(vmsg->payload) = %zu\n",
+ vmsg->request, vmsg->size, sizeof(vmsg->payload));
+ exit(1);
+ }
+
+ if (vmsg->size) {
+ rc = read(conn_fd, &vmsg->payload, vmsg->size);
+ if (rc == 0) {
+ vubr_die("recvmsg");
+ fprintf(stderr, "Peer disconnected.\n");
+ exit(1);
+ }
+ if (rc < 0) {
+ vubr_die("recvmsg");
+ }
+
+ assert(rc == vmsg->size);
+ }
+}
+
+static void
+vubr_message_write(int conn_fd, VhostUserMsg *vmsg)
+{
+ int rc;
+
+ do {
+ rc = write(conn_fd, vmsg, VHOST_USER_HDR_SIZE + vmsg->size);
+ } while (rc < 0 && errno == EINTR);
+
+ if (rc < 0) {
+ vubr_die("write");
+ }
+}
+
+static void
+vubr_backend_udp_sendbuf(VubrDev *dev, uint8_t *buf, size_t len)
+{
+ int slen = sizeof(struct sockaddr_in);
+
+ if (sendto(dev->backend_udp_sock, buf, len, 0,
+ (struct sockaddr *) &dev->backend_udp_dest, slen) == -1) {
+ vubr_die("sendto()");
+ }
+}
+
+static int
+vubr_backend_udp_recvbuf(VubrDev *dev, uint8_t *buf, size_t buflen)
+{
+ int slen = sizeof(struct sockaddr_in);
+ int rc;
+
+ rc = recvfrom(dev->backend_udp_sock, buf, buflen, 0,
+ (struct sockaddr *) &dev->backend_udp_dest,
+ (socklen_t *)&slen);
+ if (rc == -1) {
+ vubr_die("recvfrom()");
+ }
+
+ return rc;
+}
+
+static void
+vubr_consume_raw_packet(VubrDev *dev, uint8_t *buf, uint32_t len)
+{
+ int hdrlen = dev->hdrlen;
+ DPRINT(" hdrlen = %d\n", dev->hdrlen);
+
+ if (VHOST_USER_BRIDGE_DEBUG) {
+ print_buffer(buf, len);
+ }
+ vubr_backend_udp_sendbuf(dev, buf + hdrlen, len - hdrlen);
+}
+
+/* Kick the log_call_fd if required. */
+static void
+vubr_log_kick(VubrDev *dev)
+{
+ if (dev->log_call_fd != -1) {
+ DPRINT("Kicking the QEMU's log...\n");
+ eventfd_write(dev->log_call_fd, 1);
+ }
+}
+
+/* Kick the guest if necessary. */
+static void
+vubr_virtqueue_kick(VubrVirtq *vq)
+{
+ if (!(vq->avail->flags & VRING_AVAIL_F_NO_INTERRUPT)) {
+ DPRINT("Kicking the guest...\n");
+ eventfd_write(vq->call_fd, 1);
+ }
+}
+
+static void
+vubr_log_page(uint8_t *log_table, uint64_t page)
+{
+ DPRINT("Logged dirty guest page: %"PRId64"\n", page);
+ atomic_or(&log_table[page / 8], 1 << (page % 8));
+}
+
+static void
+vubr_log_write(VubrDev *dev, uint64_t address, uint64_t length)
+{
+ uint64_t page;
+
+ if (!(dev->features & (1ULL << VHOST_F_LOG_ALL)) ||
+ !dev->log_table || !length) {
+ return;
+ }
+
+ assert(dev->log_size > ((address + length - 1) / VHOST_LOG_PAGE / 8));
+
+ page = address / VHOST_LOG_PAGE;
+ while (page * VHOST_LOG_PAGE < address + length) {
+ vubr_log_page(dev->log_table, page);
+ page += VHOST_LOG_PAGE;
+ }
+ vubr_log_kick(dev);
+}
+
+static void
+vubr_post_buffer(VubrDev *dev, VubrVirtq *vq, uint8_t *buf, int32_t len)
+{
+ struct vring_desc *desc = vq->desc;
+ struct vring_avail *avail = vq->avail;
+ struct vring_used *used = vq->used;
+ uint64_t log_guest_addr = vq->log_guest_addr;
+ int32_t remaining_len = len;
+
+ unsigned int size = vq->size;
+
+ uint16_t avail_index = atomic_mb_read(&avail->idx);
+
+ /* We check the available descriptors before posting the
+ * buffer, so here we assume that enough available
+ * descriptors. */
+ assert(vq->last_avail_index != avail_index);
+ uint16_t a_index = vq->last_avail_index % size;
+ uint16_t u_index = vq->last_used_index % size;
+ uint16_t d_index = avail->ring[a_index];
+
+ int i = d_index;
+ uint32_t written_len = 0;
+
+ do {
+ DPRINT("Post packet to guest on vq:\n");
+ DPRINT(" size = %d\n", vq->size);
+ DPRINT(" last_avail_index = %d\n", vq->last_avail_index);
+ DPRINT(" last_used_index = %d\n", vq->last_used_index);
+ DPRINT(" a_index = %d\n", a_index);
+ DPRINT(" u_index = %d\n", u_index);
+ DPRINT(" d_index = %d\n", d_index);
+ DPRINT(" desc[%d].addr = 0x%016"PRIx64"\n", i, desc[i].addr);
+ DPRINT(" desc[%d].len = %d\n", i, desc[i].len);
+ DPRINT(" desc[%d].flags = %d\n", i, desc[i].flags);
+ DPRINT(" avail->idx = %d\n", avail_index);
+ DPRINT(" used->idx = %d\n", used->idx);
+
+ if (!(desc[i].flags & VRING_DESC_F_WRITE)) {
+ /* FIXME: we should find writable descriptor. */
+ fprintf(stderr, "Error: descriptor is not writable. Exiting.\n");
+ exit(1);
+ }
+
+ void *chunk_start = (void *)(uintptr_t)gpa_to_va(dev, desc[i].addr);
+ uint32_t chunk_len = desc[i].len;
+ uint32_t chunk_write_len = MIN(remaining_len, chunk_len);
+
+ memcpy(chunk_start, buf + written_len, chunk_write_len);
+ vubr_log_write(dev, desc[i].addr, chunk_write_len);
+ remaining_len -= chunk_write_len;
+ written_len += chunk_write_len;
+
+ if ((remaining_len == 0) || !(desc[i].flags & VRING_DESC_F_NEXT)) {
+ break;
+ }
+
+ i = desc[i].next;
+ } while (1);
+
+ if (remaining_len > 0) {
+ fprintf(stderr,
+ "Too long packet for RX, remaining_len = %d, Dropping...\n",
+ remaining_len);
+ return;
+ }
+
+ /* Add descriptor to the used ring. */
+ used->ring[u_index].id = d_index;
+ used->ring[u_index].len = len;
+ vubr_log_write(dev,
+ log_guest_addr + offsetof(struct vring_used, ring[u_index]),
+ sizeof(used->ring[u_index]));
+
+ vq->last_avail_index++;
+ vq->last_used_index++;
+
+ atomic_mb_set(&used->idx, vq->last_used_index);
+ vubr_log_write(dev,
+ log_guest_addr + offsetof(struct vring_used, idx),
+ sizeof(used->idx));
+
+ /* Kick the guest if necessary. */
+ vubr_virtqueue_kick(vq);
+}
+
+static int
+vubr_process_desc(VubrDev *dev, VubrVirtq *vq)
+{
+ struct vring_desc *desc = vq->desc;
+ struct vring_avail *avail = vq->avail;
+ struct vring_used *used = vq->used;
+ uint64_t log_guest_addr = vq->log_guest_addr;
+
+ unsigned int size = vq->size;
+
+ uint16_t a_index = vq->last_avail_index % size;
+ uint16_t u_index = vq->last_used_index % size;
+ uint16_t d_index = avail->ring[a_index];
+
+ uint32_t i, len = 0;
+ size_t buf_size = 4096;
+ uint8_t buf[4096];
+
+ DPRINT("Chunks: ");
+ i = d_index;
+ do {
+ void *chunk_start = (void *)(uintptr_t)gpa_to_va(dev, desc[i].addr);
+ uint32_t chunk_len = desc[i].len;
+
+ assert(!(desc[i].flags & VRING_DESC_F_WRITE));
+
+ if (len + chunk_len < buf_size) {
+ memcpy(buf + len, chunk_start, chunk_len);
+ DPRINT("%d ", chunk_len);
+ } else {
+ fprintf(stderr, "Error: too long packet. Dropping...\n");
+ break;
+ }
+
+ len += chunk_len;
+
+ if (!(desc[i].flags & VRING_DESC_F_NEXT)) {
+ break;
+ }
+
+ i = desc[i].next;
+ } while (1);
+ DPRINT("\n");
+
+ if (!len) {
+ return -1;
+ }
+
+ /* Add descriptor to the used ring. */
+ used->ring[u_index].id = d_index;
+ used->ring[u_index].len = len;
+ vubr_log_write(dev,
+ log_guest_addr + offsetof(struct vring_used, ring[u_index]),
+ sizeof(used->ring[u_index]));
+
+ vubr_consume_raw_packet(dev, buf, len);
+
+ return 0;
+}
+
+static void
+vubr_process_avail(VubrDev *dev, VubrVirtq *vq)
+{
+ struct vring_avail *avail = vq->avail;
+ struct vring_used *used = vq->used;
+ uint64_t log_guest_addr = vq->log_guest_addr;
+
+ while (vq->last_avail_index != atomic_mb_read(&avail->idx)) {
+ vubr_process_desc(dev, vq);
+ vq->last_avail_index++;
+ vq->last_used_index++;
+ }
+
+ atomic_mb_set(&used->idx, vq->last_used_index);
+ vubr_log_write(dev,
+ log_guest_addr + offsetof(struct vring_used, idx),
+ sizeof(used->idx));
+}
+
+static void
+vubr_backend_recv_cb(int sock, void *ctx)
+{
+ VubrDev *dev = (VubrDev *) ctx;
+ VubrVirtq *rx_vq = &dev->vq[0];
+ uint8_t buf[4096];
+ struct virtio_net_hdr_v1 *hdr = (struct virtio_net_hdr_v1 *)buf;
+ int hdrlen = dev->hdrlen;
+ int buflen = sizeof(buf);
+ int len;
+
+ if (!dev->ready) {
+ return;
+ }
+
+ DPRINT("\n\n *** IN UDP RECEIVE CALLBACK ***\n\n");
+ DPRINT(" hdrlen = %d\n", hdrlen);
+
+ uint16_t avail_index = atomic_mb_read(&rx_vq->avail->idx);
+
+ /* If there is no available descriptors, just do nothing.
+ * The buffer will be handled by next arrived UDP packet,
+ * or next kick on receive virtq. */
+ if (rx_vq->last_avail_index == avail_index) {
+ DPRINT("Got UDP packet, but no available descriptors on RX virtq.\n");
+ return;
+ }
+
+ memset(buf, 0, hdrlen);
+ /* TODO: support mergeable buffers. */
+ if (hdrlen == 12)
+ hdr->num_buffers = 1;
+ len = vubr_backend_udp_recvbuf(dev, buf + hdrlen, buflen - hdrlen);
+
+ vubr_post_buffer(dev, rx_vq, buf, len + hdrlen);
+}
+
+static void
+vubr_kick_cb(int sock, void *ctx)
+{
+ VubrDev *dev = (VubrDev *) ctx;
+ eventfd_t kick_data;
+ ssize_t rc;
+
+ rc = eventfd_read(sock, &kick_data);
+ if (rc == -1) {
+ vubr_die("eventfd_read()");
+ } else {
+ DPRINT("Got kick_data: %016"PRIx64"\n", kick_data);
+ vubr_process_avail(dev, &dev->vq[1]);
+ }
+}
+
+static int
+vubr_none_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ DPRINT("Function %s() not implemented yet.\n", __func__);
+ return 0;
+}
+
+static int
+vubr_get_features_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ vmsg->payload.u64 =
+ ((1ULL << VIRTIO_NET_F_MRG_RXBUF) |
+ (1ULL << VHOST_F_LOG_ALL) |
+ (1ULL << VIRTIO_NET_F_GUEST_ANNOUNCE) |
+ (1ULL << VHOST_USER_F_PROTOCOL_FEATURES));
+
+ vmsg->size = sizeof(vmsg->payload.u64);
+
+ DPRINT("Sending back to guest u64: 0x%016"PRIx64"\n", vmsg->payload.u64);
+
+ /* Reply */
+ return 1;
+}
+
+static int
+vubr_set_features_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ DPRINT("u64: 0x%016"PRIx64"\n", vmsg->payload.u64);
+
+ dev->features = vmsg->payload.u64;
+ if ((dev->features & (1ULL << VIRTIO_F_VERSION_1)) ||
+ (dev->features & (1ULL << VIRTIO_NET_F_MRG_RXBUF))) {
+ dev->hdrlen = 12;
+ } else {
+ dev->hdrlen = 10;
+ }
+
+ return 0;
+}
+
+static int
+vubr_set_owner_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ return 0;
+}
+
+static void
+vubr_close_log(VubrDev *dev)
+{
+ if (dev->log_table) {
+ if (munmap(dev->log_table, dev->log_size) != 0) {
+ vubr_die("munmap()");
+ }
+
+ dev->log_table = 0;
+ }
+ if (dev->log_call_fd != -1) {
+ close(dev->log_call_fd);
+ dev->log_call_fd = -1;
+ }
+}
+
+static int
+vubr_reset_device_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ vubr_close_log(dev);
+ dev->ready = 0;
+ dev->features = 0;
+ return 0;
+}
+
+static int
+vubr_set_mem_table_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ int i;
+ VhostUserMemory *memory = &vmsg->payload.memory;
+ dev->nregions = memory->nregions;
+
+ DPRINT("Nregions: %d\n", memory->nregions);
+ for (i = 0; i < dev->nregions; i++) {
+ void *mmap_addr;
+ VhostUserMemoryRegion *msg_region = &memory->regions[i];
+ VubrDevRegion *dev_region = &dev->regions[i];
+
+ DPRINT("Region %d\n", i);
+ DPRINT(" guest_phys_addr: 0x%016"PRIx64"\n",
+ msg_region->guest_phys_addr);
+ DPRINT(" memory_size: 0x%016"PRIx64"\n",
+ msg_region->memory_size);
+ DPRINT(" userspace_addr 0x%016"PRIx64"\n",
+ msg_region->userspace_addr);
+ DPRINT(" mmap_offset 0x%016"PRIx64"\n",
+ msg_region->mmap_offset);
+
+ dev_region->gpa = msg_region->guest_phys_addr;
+ dev_region->size = msg_region->memory_size;
+ dev_region->qva = msg_region->userspace_addr;
+ dev_region->mmap_offset = msg_region->mmap_offset;
+
+ /* We don't use offset argument of mmap() since the
+ * mapped address has to be page aligned, and we use huge
+ * pages. */
+ mmap_addr = mmap(0, dev_region->size + dev_region->mmap_offset,
+ PROT_READ | PROT_WRITE, MAP_SHARED,
+ vmsg->fds[i], 0);
+
+ if (mmap_addr == MAP_FAILED) {
+ vubr_die("mmap");
+ }
+ dev_region->mmap_addr = (uint64_t)(uintptr_t)mmap_addr;
+ DPRINT(" mmap_addr: 0x%016"PRIx64"\n", dev_region->mmap_addr);
+
+ close(vmsg->fds[i]);
+ }
+
+ return 0;
+}
+
+static int
+vubr_set_log_base_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ int fd;
+ uint64_t log_mmap_size, log_mmap_offset;
+ void *rc;
+
+ assert(vmsg->fd_num == 1);
+ fd = vmsg->fds[0];
+
+ assert(vmsg->size == sizeof(vmsg->payload.log));
+ log_mmap_offset = vmsg->payload.log.mmap_offset;
+ log_mmap_size = vmsg->payload.log.mmap_size;
+ DPRINT("Log mmap_offset: %"PRId64"\n", log_mmap_offset);
+ DPRINT("Log mmap_size: %"PRId64"\n", log_mmap_size);
+
+ rc = mmap(0, log_mmap_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd,
+ log_mmap_offset);
+ if (rc == MAP_FAILED) {
+ vubr_die("mmap");
+ }
+ dev->log_table = rc;
+ dev->log_size = log_mmap_size;
+
+ vmsg->size = sizeof(vmsg->payload.u64);
+ /* Reply */
+ return 1;
+}
+
+static int
+vubr_set_log_fd_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ assert(vmsg->fd_num == 1);
+ dev->log_call_fd = vmsg->fds[0];
+ DPRINT("Got log_call_fd: %d\n", vmsg->fds[0]);
+ return 0;
+}
+
+static int
+vubr_set_vring_num_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ unsigned int index = vmsg->payload.state.index;
+ unsigned int num = vmsg->payload.state.num;
+
+ DPRINT("State.index: %d\n", index);
+ DPRINT("State.num: %d\n", num);
+ dev->vq[index].size = num;
+ return 0;
+}
+
+static int
+vubr_set_vring_addr_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ struct vhost_vring_addr *vra = &vmsg->payload.addr;
+ unsigned int index = vra->index;
+ VubrVirtq *vq = &dev->vq[index];
+
+ DPRINT("vhost_vring_addr:\n");
+ DPRINT(" index: %d\n", vra->index);
+ DPRINT(" flags: %d\n", vra->flags);
+ DPRINT(" desc_user_addr: 0x%016llx\n", vra->desc_user_addr);
+ DPRINT(" used_user_addr: 0x%016llx\n", vra->used_user_addr);
+ DPRINT(" avail_user_addr: 0x%016llx\n", vra->avail_user_addr);
+ DPRINT(" log_guest_addr: 0x%016llx\n", vra->log_guest_addr);
+
+ vq->desc = (struct vring_desc *)(uintptr_t)qva_to_va(dev, vra->desc_user_addr);
+ vq->used = (struct vring_used *)(uintptr_t)qva_to_va(dev, vra->used_user_addr);
+ vq->avail = (struct vring_avail *)(uintptr_t)qva_to_va(dev, vra->avail_user_addr);
+ vq->log_guest_addr = vra->log_guest_addr;
+
+ DPRINT("Setting virtq addresses:\n");
+ DPRINT(" vring_desc at %p\n", vq->desc);
+ DPRINT(" vring_used at %p\n", vq->used);
+ DPRINT(" vring_avail at %p\n", vq->avail);
+
+ vq->last_used_index = vq->used->idx;
+ return 0;
+}
+
+static int
+vubr_set_vring_base_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ unsigned int index = vmsg->payload.state.index;
+ unsigned int num = vmsg->payload.state.num;
+
+ DPRINT("State.index: %d\n", index);
+ DPRINT("State.num: %d\n", num);
+ dev->vq[index].last_avail_index = num;
+
+ return 0;
+}
+
+static int
+vubr_get_vring_base_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ unsigned int index = vmsg->payload.state.index;
+
+ DPRINT("State.index: %d\n", index);
+ vmsg->payload.state.num = dev->vq[index].last_avail_index;
+ vmsg->size = sizeof(vmsg->payload.state);
+ /* FIXME: this is a work-around for a bug in QEMU enabling
+ * too early vrings. When protocol features are enabled,
+ * we have to respect * VHOST_USER_SET_VRING_ENABLE request. */
+ dev->ready = 0;
+
+ if (dev->vq[index].call_fd != -1) {
+ close(dev->vq[index].call_fd);
+ dispatcher_remove(&dev->dispatcher, dev->vq[index].call_fd);
+ dev->vq[index].call_fd = -1;
+ }
+ if (dev->vq[index].kick_fd != -1) {
+ close(dev->vq[index].kick_fd);
+ dispatcher_remove(&dev->dispatcher, dev->vq[index].kick_fd);
+ dev->vq[index].kick_fd = -1;
+ }
+
+ /* Reply */
+ return 1;
+}
+
+static int
+vubr_set_vring_kick_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ uint64_t u64_arg = vmsg->payload.u64;
+ int index = u64_arg & VHOST_USER_VRING_IDX_MASK;
+
+ DPRINT("u64: 0x%016"PRIx64"\n", vmsg->payload.u64);
+
+ assert((u64_arg & VHOST_USER_VRING_NOFD_MASK) == 0);
+ assert(vmsg->fd_num == 1);
+
+ if (dev->vq[index].kick_fd != -1) {
+ close(dev->vq[index].kick_fd);
+ dispatcher_remove(&dev->dispatcher, dev->vq[index].kick_fd);
+ }
+ dev->vq[index].kick_fd = vmsg->fds[0];
+ DPRINT("Got kick_fd: %d for vq: %d\n", vmsg->fds[0], index);
+
+ if (index % 2 == 1) {
+ /* TX queue. */
+ dispatcher_add(&dev->dispatcher, dev->vq[index].kick_fd,
+ dev, vubr_kick_cb);
+
+ DPRINT("Waiting for kicks on fd: %d for vq: %d\n",
+ dev->vq[index].kick_fd, index);
+ }
+ /* We temporarily use this hack to determine that both TX and RX
+ * queues are set up and ready for processing.
+ * FIXME: we need to rely in VHOST_USER_SET_VRING_ENABLE and
+ * actual kicks. */
+ if (dev->vq[0].kick_fd != -1 &&
+ dev->vq[1].kick_fd != -1) {
+ dev->ready = 1;
+ DPRINT("vhost-user-bridge is ready for processing queues.\n");
+ }
+ return 0;
+
+}
+
+static int
+vubr_set_vring_call_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ uint64_t u64_arg = vmsg->payload.u64;
+ int index = u64_arg & VHOST_USER_VRING_IDX_MASK;
+
+ DPRINT("u64: 0x%016"PRIx64"\n", vmsg->payload.u64);
+ assert((u64_arg & VHOST_USER_VRING_NOFD_MASK) == 0);
+ assert(vmsg->fd_num == 1);
+
+ if (dev->vq[index].call_fd != -1) {
+ close(dev->vq[index].call_fd);
+ dispatcher_remove(&dev->dispatcher, dev->vq[index].call_fd);
+ }
+ dev->vq[index].call_fd = vmsg->fds[0];
+ DPRINT("Got call_fd: %d for vq: %d\n", vmsg->fds[0], index);
+
+ return 0;
+}
+
+static int
+vubr_set_vring_err_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ DPRINT("u64: 0x%016"PRIx64"\n", vmsg->payload.u64);
+ return 0;
+}
+
+static int
+vubr_get_protocol_features_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ vmsg->payload.u64 = 1ULL << VHOST_USER_PROTOCOL_F_LOG_SHMFD;
+ DPRINT("u64: 0x%016"PRIx64"\n", vmsg->payload.u64);
+ vmsg->size = sizeof(vmsg->payload.u64);
+
+ /* Reply */
+ return 1;
+}
+
+static int
+vubr_set_protocol_features_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ /* FIXME: unimplented */
+ DPRINT("u64: 0x%016"PRIx64"\n", vmsg->payload.u64);
+ return 0;
+}
+
+static int
+vubr_get_queue_num_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ DPRINT("Function %s() not implemented yet.\n", __func__);
+ return 0;
+}
+
+static int
+vubr_set_vring_enable_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ unsigned int index = vmsg->payload.state.index;
+ unsigned int enable = vmsg->payload.state.num;
+
+ DPRINT("State.index: %d\n", index);
+ DPRINT("State.enable: %d\n", enable);
+ dev->vq[index].enable = enable;
+ return 0;
+}
+
+static int
+vubr_send_rarp_exec(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ DPRINT("Function %s() not implemented yet.\n", __func__);
+ return 0;
+}
+
+static int
+vubr_execute_request(VubrDev *dev, VhostUserMsg *vmsg)
+{
+ /* Print out generic part of the request. */
+ DPRINT(
+ "================== Vhost user message from QEMU ==================\n");
+ DPRINT("Request: %s (%d)\n", vubr_request_str[vmsg->request],
+ vmsg->request);
+ DPRINT("Flags: 0x%x\n", vmsg->flags);
+ DPRINT("Size: %d\n", vmsg->size);
+
+ if (vmsg->fd_num) {
+ int i;
+ DPRINT("Fds:");
+ for (i = 0; i < vmsg->fd_num; i++) {
+ DPRINT(" %d", vmsg->fds[i]);
+ }
+ DPRINT("\n");
+ }
+
+ switch (vmsg->request) {
+ case VHOST_USER_NONE:
+ return vubr_none_exec(dev, vmsg);
+ case VHOST_USER_GET_FEATURES:
+ return vubr_get_features_exec(dev, vmsg);
+ case VHOST_USER_SET_FEATURES:
+ return vubr_set_features_exec(dev, vmsg);
+ case VHOST_USER_SET_OWNER:
+ return vubr_set_owner_exec(dev, vmsg);
+ case VHOST_USER_RESET_OWNER:
+ return vubr_reset_device_exec(dev, vmsg);
+ case VHOST_USER_SET_MEM_TABLE:
+ return vubr_set_mem_table_exec(dev, vmsg);
+ case VHOST_USER_SET_LOG_BASE:
+ return vubr_set_log_base_exec(dev, vmsg);
+ case VHOST_USER_SET_LOG_FD:
+ return vubr_set_log_fd_exec(dev, vmsg);
+ case VHOST_USER_SET_VRING_NUM:
+ return vubr_set_vring_num_exec(dev, vmsg);
+ case VHOST_USER_SET_VRING_ADDR:
+ return vubr_set_vring_addr_exec(dev, vmsg);
+ case VHOST_USER_SET_VRING_BASE:
+ return vubr_set_vring_base_exec(dev, vmsg);
+ case VHOST_USER_GET_VRING_BASE:
+ return vubr_get_vring_base_exec(dev, vmsg);
+ case VHOST_USER_SET_VRING_KICK:
+ return vubr_set_vring_kick_exec(dev, vmsg);
+ case VHOST_USER_SET_VRING_CALL:
+ return vubr_set_vring_call_exec(dev, vmsg);
+ case VHOST_USER_SET_VRING_ERR:
+ return vubr_set_vring_err_exec(dev, vmsg);
+ case VHOST_USER_GET_PROTOCOL_FEATURES:
+ return vubr_get_protocol_features_exec(dev, vmsg);
+ case VHOST_USER_SET_PROTOCOL_FEATURES:
+ return vubr_set_protocol_features_exec(dev, vmsg);
+ case VHOST_USER_GET_QUEUE_NUM:
+ return vubr_get_queue_num_exec(dev, vmsg);
+ case VHOST_USER_SET_VRING_ENABLE:
+ return vubr_set_vring_enable_exec(dev, vmsg);
+ case VHOST_USER_SEND_RARP:
+ return vubr_send_rarp_exec(dev, vmsg);
+
+ case VHOST_USER_MAX:
+ assert(vmsg->request != VHOST_USER_MAX);
+ }
+ return 0;
+}
+
+static void
+vubr_receive_cb(int sock, void *ctx)
+{
+ VubrDev *dev = (VubrDev *) ctx;
+ VhostUserMsg vmsg;
+ int reply_requested;
+
+ vubr_message_read(sock, &vmsg);
+ reply_requested = vubr_execute_request(dev, &vmsg);
+ if (reply_requested) {
+ /* Set the version in the flags when sending the reply */
+ vmsg.flags &= ~VHOST_USER_VERSION_MASK;
+ vmsg.flags |= VHOST_USER_VERSION;
+ vmsg.flags |= VHOST_USER_REPLY_MASK;
+ vubr_message_write(sock, &vmsg);
+ }
+}
+
+static void
+vubr_accept_cb(int sock, void *ctx)
+{
+ VubrDev *dev = (VubrDev *)ctx;
+ int conn_fd;
+ struct sockaddr_un un;
+ socklen_t len = sizeof(un);
+
+ conn_fd = accept(sock, (struct sockaddr *) &un, &len);
+ if (conn_fd == -1) {
+ vubr_die("accept()");
+ }
+ DPRINT("Got connection from remote peer on sock %d\n", conn_fd);
+ dispatcher_add(&dev->dispatcher, conn_fd, ctx, vubr_receive_cb);
+}
+
+static VubrDev *
+vubr_new(const char *path, bool client)
+{
+ VubrDev *dev = (VubrDev *) calloc(1, sizeof(VubrDev));
+ dev->nregions = 0;
+ int i;
+ struct sockaddr_un un;
+ CallbackFunc cb;
+ size_t len;
+
+ for (i = 0; i < MAX_NR_VIRTQUEUE; i++) {
+ dev->vq[i] = (VubrVirtq) {
+ .call_fd = -1, .kick_fd = -1,
+ .size = 0,
+ .last_avail_index = 0, .last_used_index = 0,
+ .desc = 0, .avail = 0, .used = 0,
+ .enable = 0,
+ };
+ }
+
+ /* Init log */
+ dev->log_call_fd = -1;
+ dev->log_size = 0;
+ dev->log_table = 0;
+ dev->ready = 0;
+ dev->features = 0;
+
+ /* Get a UNIX socket. */
+ dev->sock = socket(AF_UNIX, SOCK_STREAM, 0);
+ if (dev->sock == -1) {
+ vubr_die("socket");
+ }
+
+ un.sun_family = AF_UNIX;
+ strcpy(un.sun_path, path);
+ len = sizeof(un.sun_family) + strlen(path);
+
+ if (!client) {
+ unlink(path);
+
+ if (bind(dev->sock, (struct sockaddr *) &un, len) == -1) {
+ vubr_die("bind");
+ }
+
+ if (listen(dev->sock, 1) == -1) {
+ vubr_die("listen");
+ }
+ cb = vubr_accept_cb;
+ } else {
+ if (connect(dev->sock, (struct sockaddr *)&un, len) == -1) {
+ vubr_die("connect");
+ }
+ cb = vubr_receive_cb;
+ }
+
+ dispatcher_init(&dev->dispatcher);
+ dispatcher_add(&dev->dispatcher, dev->sock, (void *)dev, cb);
+
+ DPRINT("Waiting for connections on UNIX socket %s ...\n", path);
+ return dev;
+}
+
+static void
+vubr_set_host(struct sockaddr_in *saddr, const char *host)
+{
+ if (isdigit(host[0])) {
+ if (!inet_aton(host, &saddr->sin_addr)) {
+ fprintf(stderr, "inet_aton() failed.\n");
+ exit(1);
+ }
+ } else {
+ struct hostent *he = gethostbyname(host);
+
+ if (!he) {
+ fprintf(stderr, "gethostbyname() failed.\n");
+ exit(1);
+ }
+ saddr->sin_addr = *(struct in_addr *)he->h_addr;
+ }
+}
+
+static void
+vubr_backend_udp_setup(VubrDev *dev,
+ const char *local_host,
+ const char *local_port,
+ const char *remote_host,
+ const char *remote_port)
+{
+ int sock;
+ const char *r;
+
+ int lport, rport;
+
+ lport = strtol(local_port, (char **)&r, 0);
+ if (r == local_port) {
+ fprintf(stderr, "lport parsing failed.\n");
+ exit(1);
+ }
+
+ rport = strtol(remote_port, (char **)&r, 0);
+ if (r == remote_port) {
+ fprintf(stderr, "rport parsing failed.\n");
+ exit(1);
+ }
+
+ struct sockaddr_in si_local = {
+ .sin_family = AF_INET,
+ .sin_port = htons(lport),
+ };
+
+ vubr_set_host(&si_local, local_host);
+
+ /* setup destination for sends */
+ dev->backend_udp_dest = (struct sockaddr_in) {
+ .sin_family = AF_INET,
+ .sin_port = htons(rport),
+ };
+ vubr_set_host(&dev->backend_udp_dest, remote_host);
+
+ sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);
+ if (sock == -1) {
+ vubr_die("socket");
+ }
+
+ if (bind(sock, (struct sockaddr *)&si_local, sizeof(si_local)) == -1) {
+ vubr_die("bind");
+ }
+
+ dev->backend_udp_sock = sock;
+ dispatcher_add(&dev->dispatcher, sock, dev, vubr_backend_recv_cb);
+ DPRINT("Waiting for data from udp backend on %s:%d...\n",
+ local_host, lport);
+}
+
+static void
+vubr_run(VubrDev *dev)
+{
+ while (1) {
+ /* timeout 200ms */
+ dispatcher_wait(&dev->dispatcher, 200000);
+ /* Here one can try polling strategy. */
+ }
+}
+
+static int
+vubr_parse_host_port(const char **host, const char **port, const char *buf)
+{
+ char *p = strchr(buf, ':');
+
+ if (!p) {
+ return -1;
+ }
+ *p = '\0';
+ *host = strdup(buf);
+ *port = strdup(p + 1);
+ return 0;
+}
+
+#define DEFAULT_UD_SOCKET "/tmp/vubr.sock"
+#define DEFAULT_LHOST "127.0.0.1"
+#define DEFAULT_LPORT "4444"
+#define DEFAULT_RHOST "127.0.0.1"
+#define DEFAULT_RPORT "5555"
+
+static const char *ud_socket_path = DEFAULT_UD_SOCKET;
+static const char *lhost = DEFAULT_LHOST;
+static const char *lport = DEFAULT_LPORT;
+static const char *rhost = DEFAULT_RHOST;
+static const char *rport = DEFAULT_RPORT;
+
+int
+main(int argc, char *argv[])
+{
+ VubrDev *dev;
+ int opt;
+ bool client = false;
+
+ while ((opt = getopt(argc, argv, "l:r:u:c")) != -1) {
+
+ switch (opt) {
+ case 'l':
+ if (vubr_parse_host_port(&lhost, &lport, optarg) < 0) {
+ goto out;
+ }
+ break;
+ case 'r':
+ if (vubr_parse_host_port(&rhost, &rport, optarg) < 0) {
+ goto out;
+ }
+ break;
+ case 'u':
+ ud_socket_path = strdup(optarg);
+ break;
+ case 'c':
+ client = true;
+ break;
+ default:
+ goto out;
+ }
+ }
+
+ DPRINT("ud socket: %s (%s)\n", ud_socket_path,
+ client ? "client" : "server");
+ DPRINT("local: %s:%s\n", lhost, lport);
+ DPRINT("remote: %s:%s\n", rhost, rport);
+
+ dev = vubr_new(ud_socket_path, client);
+ if (!dev) {
+ return 1;
+ }
+
+ vubr_backend_udp_setup(dev, lhost, lport, rhost, rport);
+ vubr_run(dev);
+ return 0;
+
+out:
+ fprintf(stderr, "Usage: %s ", argv[0]);
+ fprintf(stderr, "[-u ud_socket_path] [-l lhost:lport] [-r rhost:rport]\n");
+ fprintf(stderr, "\t-u path to unix doman socket. default: %s\n",
+ DEFAULT_UD_SOCKET);
+ fprintf(stderr, "\t-l local host and port. default: %s:%s\n",
+ DEFAULT_LHOST, DEFAULT_LPORT);
+ fprintf(stderr, "\t-r remote host and port. default: %s:%s\n",
+ DEFAULT_RHOST, DEFAULT_RPORT);
+
+ return 1;
+}
new file mode 100644
@@ -0,0 +1,364 @@
+/*
+ * QTest testcase for the vhost-user
+ *
+ * Copyright (c) 2014 Virtual Open Systems Sarl.
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#include <glib.h>
+
+#include "libqtest.h"
+#include "qemu/option.h"
+#include "sysemu/char.h"
+#include "sysemu/sysemu.h"
+
+#include <linux/vhost.h>
+#include <sys/mman.h>
+#include <sys/vfs.h>
+#include <qemu/sockets.h>
+
+/* GLIB version compatibility flags */
+#if !GLIB_CHECK_VERSION(2, 26, 0)
+#define G_TIME_SPAN_SECOND (G_GINT64_CONSTANT(1000000))
+#endif
+
+#if GLIB_CHECK_VERSION(2, 28, 0)
+#define HAVE_MONOTONIC_TIME
+#endif
+
+#define QEMU_CMD_ACCEL " -machine accel=tcg"
+#define QEMU_CMD_MEM " -m 512 -object memory-backend-file,id=mem,size=512M,"\
+ "mem-path=%s,share=on -numa node,memdev=mem"
+#define QEMU_CMD_CHR " -chardev socket,id=chr0,path=%s"
+#define QEMU_CMD_NETDEV " -netdev vhost-user,id=net0,chardev=chr0,vhostforce"
+#define QEMU_CMD_NET " -device virtio-net-pci,netdev=net0 "
+#define QEMU_CMD_ROM " -option-rom ../pc-bios/pxe-virtio.rom"
+
+#define QEMU_CMD QEMU_CMD_ACCEL QEMU_CMD_MEM QEMU_CMD_CHR \
+ QEMU_CMD_NETDEV QEMU_CMD_NET QEMU_CMD_ROM
+
+#define HUGETLBFS_MAGIC 0x958458f6
+
+/*********** FROM hw/virtio/vhost-user.c *************************************/
+
+#define VHOST_MEMORY_MAX_NREGIONS 8
+
+#define VHOST_USER_F_PROTOCOL_FEATURES 30
+
+typedef enum VhostUserRequest {
+ VHOST_USER_NONE = 0,
+ VHOST_USER_GET_FEATURES = 1,
+ VHOST_USER_SET_FEATURES = 2,
+ VHOST_USER_SET_OWNER = 3,
+ VHOST_USER_RESET_DEVICE = 4,
+ VHOST_USER_SET_MEM_TABLE = 5,
+ VHOST_USER_SET_LOG_BASE = 6,
+ VHOST_USER_SET_LOG_FD = 7,
+ VHOST_USER_SET_VRING_NUM = 8,
+ VHOST_USER_SET_VRING_ADDR = 9,
+ VHOST_USER_SET_VRING_BASE = 10,
+ VHOST_USER_GET_VRING_BASE = 11,
+ VHOST_USER_SET_VRING_KICK = 12,
+ VHOST_USER_SET_VRING_CALL = 13,
+ VHOST_USER_SET_VRING_ERR = 14,
+ VHOST_USER_GET_PROTOCOL_FEATURES = 15,
+ VHOST_USER_SET_PROTOCOL_FEATURES = 16,
+ VHOST_USER_MAX
+} VhostUserRequest;
+
+typedef struct VhostUserMemoryRegion {
+ uint64_t guest_phys_addr;
+ uint64_t memory_size;
+ uint64_t userspace_addr;
+ uint64_t mmap_offset;
+} VhostUserMemoryRegion;
+
+typedef struct VhostUserMemory {
+ uint32_t nregions;
+ uint32_t padding;
+ VhostUserMemoryRegion regions[VHOST_MEMORY_MAX_NREGIONS];
+} VhostUserMemory;
+
+typedef struct VhostUserMsg {
+ VhostUserRequest request;
+
+#define VHOST_USER_VERSION_MASK (0x3)
+#define VHOST_USER_REPLY_MASK (0x1<<2)
+ uint32_t flags;
+ uint32_t size; /* the following payload size */
+ union {
+ uint64_t u64;
+ struct vhost_vring_state state;
+ struct vhost_vring_addr addr;
+ VhostUserMemory memory;
+ };
+} QEMU_PACKED VhostUserMsg;
+
+static VhostUserMsg m __attribute__ ((unused));
+#define VHOST_USER_HDR_SIZE (sizeof(m.request) \
+ + sizeof(m.flags) \
+ + sizeof(m.size))
+
+#define VHOST_USER_PAYLOAD_SIZE (sizeof(m) - VHOST_USER_HDR_SIZE)
+
+/* The version of the protocol we support */
+#define VHOST_USER_VERSION (0x1)
+/*****************************************************************************/
+
+int fds_num = 0, fds[VHOST_MEMORY_MAX_NREGIONS];
+static VhostUserMemory memory;
+static CompatGMutex data_mutex;
+static CompatGCond data_cond;
+
+#if !GLIB_CHECK_VERSION(2, 32, 0)
+static gboolean g_cond_wait_until(CompatGCond cond, CompatGMutex mutex,
+ gint64 end_time)
+{
+ gboolean ret = FALSE;
+ end_time -= g_get_monotonic_time();
+ GTimeVal time = { end_time / G_TIME_SPAN_SECOND,
+ end_time % G_TIME_SPAN_SECOND };
+ ret = g_cond_timed_wait(cond, mutex, &time);
+ return ret;
+}
+#endif
+
+static void wait_for_fds(void)
+{
+ gint64 end_time;
+
+ g_mutex_lock(&data_mutex);
+ end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND;
+ while (!fds_num) {
+ if (!g_cond_wait_until(&data_cond, &data_mutex, end_time)) {
+ /* timeout has passed */
+ g_assert(fds_num);
+ break;
+ }
+ }
+
+ /* check for sanity */
+ g_assert_cmpint(fds_num, >, 0);
+ g_assert_cmpint(fds_num, ==, memory.nregions);
+
+ g_mutex_unlock(&data_mutex);
+}
+
+static void read_guest_mem(void)
+{
+ uint32_t *guest_mem;
+ int i, j;
+ size_t size;
+
+ wait_for_fds();
+
+ /* iterate all regions */
+ for (i = 0; i < fds_num; i++) {
+
+ /* We'll check only the region statring at 0x0*/
+ if (memory.regions[i].guest_phys_addr != 0x0) {
+ continue;
+ }
+
+ g_assert_cmpint(memory.regions[i].memory_size, >, 1024);
+
+ size = memory.regions[i].memory_size + memory.regions[i].mmap_offset;
+
+ guest_mem = mmap(0, size, PROT_READ | PROT_WRITE,
+ MAP_SHARED, fds[i], 0);
+
+ g_assert(guest_mem != MAP_FAILED);
+ guest_mem += (memory.regions[i].mmap_offset / sizeof(*guest_mem));
+
+ for (j = 0; j < 256; j++) {
+ uint32_t a = readl(memory.regions[i].guest_phys_addr + j*4);
+ uint32_t b = guest_mem[j];
+
+ g_assert_cmpint(a, ==, b);
+ }
+
+ munmap(guest_mem, memory.regions[i].memory_size);
+ }
+
+ g_mutex_unlock(&data_mutex);
+}
+
+static void *thread_function(void *data)
+{
+ GMainLoop *loop;
+ loop = g_main_loop_new(NULL, FALSE);
+ g_main_loop_run(loop);
+ return NULL;
+}
+
+static int chr_can_read(void *opaque)
+{
+ return VHOST_USER_HDR_SIZE;
+}
+
+static void chr_read(void *opaque, const uint8_t *buf, int size)
+{
+ CharDriverState *chr = opaque;
+ VhostUserMsg msg;
+ uint8_t *p = (uint8_t *) &msg;
+ int fd;
+
+ if (size != VHOST_USER_HDR_SIZE) {
+ g_test_message("Wrong message size received %d\n", size);
+ return;
+ }
+
+ g_mutex_lock(&data_mutex);
+ memcpy(p, buf, VHOST_USER_HDR_SIZE);
+
+ if (msg.size) {
+ p += VHOST_USER_HDR_SIZE;
+ qemu_chr_fe_read_all(chr, p, msg.size);
+ }
+
+ switch (msg.request) {
+ case VHOST_USER_GET_FEATURES:
+ /* send back features to qemu */
+ msg.flags |= VHOST_USER_REPLY_MASK;
+ msg.size = sizeof(m.u64);
+ msg.u64 = 0x1ULL << VHOST_USER_F_PROTOCOL_FEATURES;
+ p = (uint8_t *) &msg;
+ qemu_chr_fe_write_all(chr, p, VHOST_USER_HDR_SIZE + msg.size);
+ break;
+
+ case VHOST_USER_SET_FEATURES:
+ g_assert_cmpint(msg.u64 & (0x1ULL << VHOST_USER_F_PROTOCOL_FEATURES),
+ !=, 0ULL);
+ break;
+
+ case VHOST_USER_GET_PROTOCOL_FEATURES:
+ /* send back features to qemu */
+ msg.flags |= VHOST_USER_REPLY_MASK;
+ msg.size = sizeof(m.u64);
+ msg.u64 = 0;
+ p = (uint8_t *) &msg;
+ qemu_chr_fe_write_all(chr, p, VHOST_USER_HDR_SIZE + msg.size);
+ break;
+
+ case VHOST_USER_GET_VRING_BASE:
+ /* send back vring base to qemu */
+ msg.flags |= VHOST_USER_REPLY_MASK;
+ msg.size = sizeof(m.state);
+ msg.state.num = 0;
+ p = (uint8_t *) &msg;
+ qemu_chr_fe_write_all(chr, p, VHOST_USER_HDR_SIZE + msg.size);
+ break;
+
+ case VHOST_USER_SET_MEM_TABLE:
+ /* received the mem table */
+ memcpy(&memory, &msg.memory, sizeof(msg.memory));
+ fds_num = qemu_chr_fe_get_msgfds(chr, fds, sizeof(fds) / sizeof(int));
+
+ /* signal the test that it can continue */
+ g_cond_signal(&data_cond);
+ break;
+
+ case VHOST_USER_SET_VRING_KICK:
+ case VHOST_USER_SET_VRING_CALL:
+ /* consume the fd */
+ qemu_chr_fe_get_msgfds(chr, &fd, 1);
+ /*
+ * This is a non-blocking eventfd.
+ * The receive function forces it to be blocking,
+ * so revert it back to non-blocking.
+ */
+ qemu_set_nonblock(fd);
+ break;
+ default:
+ break;
+ }
+ g_mutex_unlock(&data_mutex);
+}
+
+static const char *init_hugepagefs(void)
+{
+ const char *path;
+ struct statfs fs;
+ int ret;
+
+ path = getenv("QTEST_HUGETLBFS_PATH");
+ if (!path) {
+ path = "/hugetlbfs";
+ }
+
+ if (access(path, R_OK | W_OK | X_OK)) {
+ g_test_message("access on path (%s): %s\n", path, strerror(errno));
+ return NULL;
+ }
+
+ do {
+ ret = statfs(path, &fs);
+ } while (ret != 0 && errno == EINTR);
+
+ if (ret != 0) {
+ g_test_message("statfs on path (%s): %s\n", path, strerror(errno));
+ return NULL;
+ }
+
+ if (fs.f_type != HUGETLBFS_MAGIC) {
+ g_test_message("Warning: path not on HugeTLBFS: %s\n", path);
+ return NULL;
+ }
+
+ return path;
+}
+
+int main(int argc, char **argv)
+{
+ QTestState *s = NULL;
+ CharDriverState *chr = NULL;
+ const char *hugefs = 0;
+ char *socket_path = 0;
+ char *qemu_cmd = 0;
+ char *chr_path = 0;
+ int ret;
+
+ g_test_init(&argc, &argv, NULL);
+
+ module_call_init(MODULE_INIT_QOM);
+
+ hugefs = init_hugepagefs();
+ if (!hugefs) {
+ return 0;
+ }
+
+ socket_path = g_strdup_printf("/tmp/vhost-%d.sock", getpid());
+
+ /* create char dev and add read handlers */
+ qemu_add_opts(&qemu_chardev_opts);
+ chr_path = g_strdup_printf("unix:%s,server,nowait", socket_path);
+ chr = qemu_chr_new("chr0", chr_path, NULL);
+ g_free(chr_path);
+ qemu_chr_add_handlers(chr, chr_can_read, chr_read, NULL, chr);
+
+ /* run the main loop thread so the chardev may operate */
+ g_mutex_init(&data_mutex);
+ g_cond_init(&data_cond);
+ g_thread_new(NULL, thread_function, NULL);
+
+ qemu_cmd = g_strdup_printf(QEMU_CMD, hugefs, socket_path);
+ s = qtest_start(qemu_cmd);
+ g_free(qemu_cmd);
+
+ qtest_add_func("/vhost-user/read-guest-mem", read_guest_mem);
+
+ ret = g_test_run();
+
+ if (s) {
+ qtest_quit(s);
+ }
+
+ /* cleanup */
+ unlink(socket_path);
+ g_free(socket_path);
+
+ return ret;
+}