From patchwork Thu Oct 15 15:21:36 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Baturo X-Patchwork-Id: 11839521 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0681C1744 for ; Thu, 15 Oct 2020 15:29:41 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8AE6A2222E for ; Thu, 15 Oct 2020 15:29:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="H16nCnw3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8AE6A2222E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:57842 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kT5CF-0007cz-Du for patchwork-qemu-devel@patchwork.kernel.org; Thu, 15 Oct 2020 11:29:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49884) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kT54j-0007MM-O5; Thu, 15 Oct 2020 11:21:53 -0400 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]:37429) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kT54h-00060P-DT; Thu, 15 Oct 2020 11:21:53 -0400 Received: by mail-ej1-x635.google.com with SMTP id e22so4201709ejr.4; Thu, 15 Oct 2020 08:21:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7/KR91T30kiKJC5sYnwuR/Z2IuXIJJJNYUfsVv1KJ5w=; b=H16nCnw3S5fDHMIZNQr2/3KXYFGlOlE0HqCFJdUN43JsXufT1Z/20SXPAm/kel+2YZ dECZxTJirsZgYQgvaSrKGre+WNMdeeufCXuRHbhBn+JL7xlMuewSJUxVlWp85H1Dxci3 8uENAOIU5qOyCJpGw1d/+rLU2HLKYyEBpjq/NdhBGwF9k0azA8YXjtmH6Xp/RzUoqqxV 6pzqk3XYi0rU9WXtvPYBDUkQbdGd3BfGvs+k9oGHz3FhiDXQ0kIZcDMeH30JnWm1/DkG D6sm2pe+2ePXQue4KJc37ruNn5TGROC50VvmPrGvhCZ3cteA0xYTqRsP6vGSXcOXLcNb qv1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7/KR91T30kiKJC5sYnwuR/Z2IuXIJJJNYUfsVv1KJ5w=; b=j7LTydtJ38s14Yku3rQgOrl4XRnFt7ECPcf8kLjc2H4APLjJa5OG9qE20qWNLL9IkZ Fx7tyr+Po72CbZsQo5IrgvOe5P6cFvMqCtM/PR7gNBIks5eIKzQjdoUHFiKsNDIC7f3A WvaVYtA8HfyvEbiI3pPuCvwkIchyHPzdpWKgTZLMAmiN7TMxKxH/ippN7cpeuBFUkuAZ v4hXyz9as594JxZ1mkU0nBSp6OS0D6pB4xhw35xR0sZuLMrn79etsnBtwV9/4yi4P7EQ 9ti0YnZbl0Llk5HQ8smVeeaTJP0dkfj6iXWNyUAAdPy/shDr6Xw0h22AOES285b4e/dG Owwg== X-Gm-Message-State: AOAM533c5bqMulCP9cLAOhlOPL9VEEgu/pTN5QxOs10F8oH2irGg1wT/ IEhAacdqrQTtuDUC+b2v+qjyr15cdQOpJafB X-Google-Smtp-Source: ABdhPJwAKYtp1iXOwvzzs3hIfZSFe2t9kd6OvtK75youAhqGaQjA0AHpSLnZQDV3BZ+W7J1AbCaUbg== X-Received: by 2002:a17:907:43c6:: with SMTP id i6mr4914243ejs.207.1602775309477; Thu, 15 Oct 2020 08:21:49 -0700 (PDT) Received: from neptune.lab ([46.39.229.194]) by smtp.googlemail.com with ESMTPSA id i5sm1819539ejv.54.2020.10.15.08.21.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Oct 2020 08:21:48 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v2 2/5] [RISCV_PM] Support CSRs required for RISC-V PM extension except for ones in hypervisor mode Date: Thu, 15 Oct 2020 18:21:36 +0300 Message-Id: <20201015152139.28903-2-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201015152139.28903-1-space.monkey.delivers@gmail.com> References: <20201015152139.28903-1-space.monkey.delivers@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x635.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com, kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 11 ++ target/riscv/cpu_bits.h | 66 ++++++++++ target/riscv/csr.c | 277 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 355 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fe6bab4a52..d63031eb08 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -440,6 +440,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (cpu->cfg.ext_j) { target_misa |= RVJ; + env->mmte |= PM_EXT_INITIAL; } if (cpu->cfg.ext_v) { target_misa |= RVV; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eca611a367..21e47b8283 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -226,6 +226,17 @@ struct CPURISCVState { /* True if in debugger mode. */ bool debugger; + + /* CSRs for PM + * TODO: move these csr to appropriate groups + */ + target_ulong mmte; + target_ulong mpmmask; + target_ulong mpmbase; + target_ulong spmmask; + target_ulong spmbase; + target_ulong upmmask; + target_ulong upmbase; #endif float_status fp_status; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bd36062877..84c93c77ae 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -354,6 +354,21 @@ #define CSR_MHPMCOUNTER30H 0xb9e #define CSR_MHPMCOUNTER31H 0xb9f +/* Custom user register */ +#define CSR_UMTE 0x8c0 +#define CSR_UPMMASK 0x8c1 +#define CSR_UPMBASE 0x8c2 + +/* Custom machine register */ +#define CSR_MMTE 0x7c0 +#define CSR_MPMMASK 0x7c1 +#define CSR_MPMBASE 0x7c2 + +/* Custom supervisor register */ +#define CSR_SMTE 0x9c0 +#define CSR_SPMMASK 0x9c1 +#define CSR_SPMBASE 0x9c2 + /* Legacy Machine Protection and Translation (priv v1.9.1) */ #define CSR_MBASE 0x380 #define CSR_MBOUND 0x381 @@ -604,4 +619,55 @@ #define MIE_UTIE (1 << IRQ_U_TIMER) #define MIE_SSIE (1 << IRQ_S_SOFT) #define MIE_USIE (1 << IRQ_U_SOFT) + +/* general mte CSR bits*/ +#define PM_ENABLE 0x00000001ULL +#define PM_CURRENT 0x00000002ULL +#define PM_XS_MASK 0x00000003ULL + +/* PM XS bits values */ +#define PM_EXT_DISABLE 0x00000000ULL +#define PM_EXT_INITIAL 0x00000001ULL +#define PM_EXT_CLEAN 0x00000002ULL +#define PM_EXT_DIRTY 0x00000003ULL + +/* offsets for every pair of control bits per each priv level */ +#define XS_OFFSET 0ULL +#define U_OFFSET 2ULL +#define S_OFFSET 4ULL +#define M_OFFSET 6ULL + +#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET) +#define U_PM_ENABLE (PM_ENABLE << U_OFFSET) +#define U_PM_CURRENT (PM_CURRENT << U_OFFSET) +#define S_PM_ENABLE (PM_ENABLE << S_OFFSET) +#define S_PM_CURRENT (PM_CURRENT << S_OFFSET) +#define M_PM_ENABLE (PM_ENABLE << M_OFFSET) + +/* mmte CSR bits */ +#define MMTE_PM_XS_BITS PM_XS_BITS +#define MMTE_U_PM_ENABLE U_PM_ENABLE +#define MMTE_U_PM_CURRENT U_PM_CURRENT +#define MMTE_S_PM_ENABLE S_PM_ENABLE +#define MMTE_S_PM_CURRENT S_PM_CURRENT +#define MMTE_M_PM_ENABLE M_PM_ENABLE +#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | \ + MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | \ + MMTE_M_PM_ENABLE | MMTE_PM_XS_BITS) + +/* smte CSR bits */ +#define SMTE_PM_XS_BITS PM_XS_BITS +#define SMTE_U_PM_ENABLE U_PM_ENABLE +#define SMTE_U_PM_CURRENT U_PM_CURRENT +#define SMTE_S_PM_ENABLE S_PM_ENABLE +#define SMTE_S_PM_CURRENT S_PM_CURRENT +#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | \ + SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | \ + SMTE_PM_XS_BITS) + +/* umte CSR bits */ +#define UMTE_U_PM_ENABLE U_PM_ENABLE +#define UMTE_U_PM_CURRENT U_PM_CURRENT +#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT) + #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index aaef6c6f20..f48f4c4070 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -140,6 +140,11 @@ static int any(CPURISCVState *env, int csrno) return 0; } +static int umode(CPURISCVState *env, int csrno) +{ + return -!riscv_has_ext(env, RVU); +} + static int smode(CPURISCVState *env, int csrno) { return -!riscv_has_ext(env, RVS); @@ -1250,6 +1255,263 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val) return 0; } +/* Functions to access Pointer Masking feature registers + * We have to check if current priv lvl could modify + * csr in given mode + */ +static int check_pm_current_disabled(CPURISCVState *env, int csrno) +{ + /* m-mode is always allowed to modify registers, so allow */ + if (env->priv == PRV_M) { + return 0; + } + int csr_priv = get_field(csrno, 0xC00); + /* If priv lvls differ that means we're accessing csr from higher priv lvl, so allow */ + if (env->priv != csr_priv) { + return 0; + } + int cur_bit_pos = (env->priv == PRV_U) ? U_PM_CURRENT : + (env->priv == PRV_S) ? S_PM_CURRENT : -1; + assert(cur_bit_pos != -1); + int pm_current = get_field(env->mmte, cur_bit_pos); + /* We're in same priv lvl, so we allow to modify csr only if pm_current==1 */ + return !pm_current; +} + +static int read_mmte(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + *val = 0; + return 0; + } +#endif + *val = env->mmte & MMTE_MASK; + return 0; +} + +static int write_mmte(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + target_ulong wpri_val = val & MMTE_MASK; + assert(val == wpri_val); + env->mmte = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_smte(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + *val = 0; + return 0; + } +#endif + *val = env->mmte & SMTE_MASK; + return 0; +} + +static int write_smte(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + target_ulong wpri_val = val & SMTE_MASK; + assert(val == wpri_val); + if (check_pm_current_disabled(env, csrno)) + return 0; + target_ulong new_val = val | (env->mmte & ~SMTE_MASK); + write_mmte(env, csrno, new_val); + return 0; +} + +static int read_umte(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + *val = 0; + return 0; + } +#endif + *val = env->mmte & UMTE_MASK; + return 0; +} + +static int write_umte(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + target_ulong wpri_val = val & UMTE_MASK; + assert(val == wpri_val); + if (check_pm_current_disabled(env, csrno)) + return 0; + target_ulong new_val = val | (env->mmte & ~UMTE_MASK); + write_mmte(env, csrno, new_val); + return 0; +} + +static int read_mpmmask(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + *val = env->mpmmask; + return 0; +} + +static int write_mpmmask(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + env->mpmmask = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_spmmask(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + *val = env->spmmask; + return 0; +} + +static int write_spmmask(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + if (check_pm_current_disabled(env, csrno)) + return 0; + env->spmmask = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_upmmask(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + *val = env->upmmask; + return 0; +} + +static int write_upmmask(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + if (check_pm_current_disabled(env, csrno)) + return 0; + env->upmmask = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_mpmbase(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + *val = env->mpmbase; + return 0; +} + +static int write_mpmbase(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + env->mpmbase = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_spmbase(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + *val = env->spmbase; + return 0; +} + +static int write_spmbase(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + if (check_pm_current_disabled(env, csrno)) + return 0; + env->spmbase = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} + +static int read_upmbase(CPURISCVState *env, int csrno, target_ulong *val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + *val = env->upmbase; + return 0; +} + +static int write_upmbase(CPURISCVState *env, int csrno, target_ulong val) +{ +#if !defined(CONFIG_USER_ONLY) + if (!riscv_has_ext(env, RVJ)) { + return -RISCV_EXCP_ILLEGAL_INST; + } +#endif + if (check_pm_current_disabled(env, csrno)) + return 0; + env->upmbase = val; + env->mstatus |= MSTATUS_XS | MSTATUS_SD; + env->mmte |= PM_EXT_DIRTY; + return 0; +} #endif /* @@ -1471,6 +1733,21 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr }, + /* User Pointer Masking */ + [CSR_UMTE] = { umode, read_umte, write_umte }, + [CSR_UPMMASK] = { umode, read_upmmask, write_upmmask }, + [CSR_UPMBASE] = { umode, read_upmbase, write_upmbase }, + + /* Machine Pointer Masking */ + [CSR_MMTE] = { any, read_mmte, write_mmte }, + [CSR_MPMMASK] = { any, read_mpmmask, write_mpmmask }, + [CSR_MPMBASE] = { any, read_mpmbase, write_mpmbase }, + + /* Supervisor Pointer Masking */ + [CSR_SMTE] = { smode, read_smte, write_smte }, + [CSR_SPMMASK] = { smode, read_spmmask, write_spmmask }, + [CSR_SPMBASE] = { smode, read_spmbase, write_spmbase }, + /* Performance Counters */ [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero }, [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },