diff mbox series

[v2,5/5,RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension

Message ID 20201015152139.28903-5-space.monkey.delivers@gmail.com (mailing list archive)
State New, archived
Headers show
Series [v2,1/5,RISCV_PM] Add J-extension into RISC-V | expand

Commit Message

Alexey Baturo Oct. 15, 2020, 3:21 p.m. UTC 
From: Anatoly Parshintsev <kupokupokupopo@gmail.com>

Signed-off-by: Anatoly Parshintsev <kupokupokupopo@gmail.com>
---
 target/riscv/cpu.h       | 19 +++++++++++++++++++
 target/riscv/translate.c | 39 +++++++++++++++++++++++++++++++++++++--
 2 files changed, 56 insertions(+), 2 deletions(-)

Comments

Richard Henderson Oct. 15, 2020, 5:07 p.m. UTC | #1 
On 10/15/20 8:21 AM, Alexey Baturo wrote:
> +        switch (priv) {
> +        case PRV_U:
> +            pm_enabled = env->mmte & U_PM_ENABLE;
> +            break;
> +        case PRV_S:
> +            pm_enabled = env->mmte & S_PM_ENABLE;
> +            break;
> +        case PRV_M:
> +            pm_enabled = env->mmte & M_PM_ENABLE;
> +            break;
> +        default:
> +            assert(0 && "Unreachable");

g_assert_not_reached();

> +    /* PointerMasking extension */
> +    uint8_t pm_enabled;

bool

> +    if (s->pm_enabled == 0) {

!s->pm_enabled

> +    if (riscv_has_ext(env, RVJ)) {
> +        ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
> +        int priv = cpu_mmu_index(env, false);
> +        ctx->pm_mask = pm_mask[priv];
> +        ctx->pm_base = pm_base[priv];
> +    } else {
> +        ctx->pm_enabled = 0;
> +    }

Don't need the if.  And should it in fact be placed outside the ifdef?  This
shouldn't be related to !CONFIG_USER_ONLY here and nowhere else.


r~
Alexey Baturo Oct. 15, 2020, 5:33 p.m. UTC | #2 
> g_assert_not_reached();
Would fix, thanks.

> bool
Would fix.

>!s->pm_enabled
Same.

> Don't need the if.
Would remove, thanks.

> And should it in fact be placed outside the ifdef?
Sure, you're right.

Richard, thank you for your time and effort reviewing these changes!

чт, 15 окт. 2020 г. в 20:07, Richard Henderson <richard.henderson@linaro.org
>:

> On 10/15/20 8:21 AM, Alexey Baturo wrote:
> > +        switch (priv) {
> > +        case PRV_U:
> > +            pm_enabled = env->mmte & U_PM_ENABLE;
> > +            break;
> > +        case PRV_S:
> > +            pm_enabled = env->mmte & S_PM_ENABLE;
> > +            break;
> > +        case PRV_M:
> > +            pm_enabled = env->mmte & M_PM_ENABLE;
> > +            break;
> > +        default:
> > +            assert(0 && "Unreachable");
>
> g_assert_not_reached();
>
> > +    /* PointerMasking extension */
> > +    uint8_t pm_enabled;
>
> bool
>
> > +    if (s->pm_enabled == 0) {
>
> !s->pm_enabled
>
> > +    if (riscv_has_ext(env, RVJ)) {
> > +        ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
> > +        int priv = cpu_mmu_index(env, false);
> > +        ctx->pm_mask = pm_mask[priv];
> > +        ctx->pm_base = pm_base[priv];
> > +    } else {
> > +        ctx->pm_enabled = 0;
> > +    }
>
> Don't need the if.  And should it in fact be placed outside the ifdef?
> This
> shouldn't be related to !CONFIG_USER_ONLY here and nowhere else.
>
>
> r~
>
diff mbox series

Patch

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 21e47b8283..6c301b7ab1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -385,6 +385,7 @@  FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
 FIELD(TB_FLAGS, LMUL, 3, 2)
 FIELD(TB_FLAGS, SEW, 5, 3)
 FIELD(TB_FLAGS, VILL, 8, 1)
+FIELD(TB_FLAGS, PM_ENABLED, 9, 1)
 
 /*
  * A simplification for VLMAX
@@ -431,6 +432,24 @@  static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
     if (riscv_cpu_fp_enabled(env)) {
         flags |= env->mstatus & MSTATUS_FS;
     }
+    if (riscv_has_ext(env, RVJ)) {
+        int priv = cpu_mmu_index(env, false);
+        bool pm_enabled = false;
+        switch (priv) {
+        case PRV_U:
+            pm_enabled = env->mmte & U_PM_ENABLE;
+            break;
+        case PRV_S:
+            pm_enabled = env->mmte & S_PM_ENABLE;
+            break;
+        case PRV_M:
+            pm_enabled = env->mmte & M_PM_ENABLE;
+            break;
+        default:
+            assert(0 && "Unreachable");
+        }
+        flags = FIELD_DP32(flags, TB_FLAGS, PM_ENABLED, pm_enabled);
+    }
 #endif
     *pflags = flags;
 }
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index a7cbf909f3..58b05ee2c7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -36,6 +36,9 @@  static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
 static TCGv load_res;
 static TCGv load_val;
+/* globals for PM CSRs */
+static TCGv pm_mask[4];
+static TCGv pm_base[4];
 
 #include "exec/gen-icount.h"
 
@@ -63,6 +66,10 @@  typedef struct DisasContext {
     uint16_t vlen;
     uint16_t mlen;
     bool vl_eq_vlmax;
+    /* PointerMasking extension */
+    uint8_t pm_enabled;
+    TCGv pm_mask;
+    TCGv pm_base;
 } DisasContext;
 
 #ifdef TARGET_RISCV64
@@ -102,13 +109,19 @@  static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
 }
 
 /*
- * Temp stub: generates address adjustment for PointerMasking
+ * Generates address adjustment for PointerMasking
  */
 static void gen_pm_adjust_address(DisasContext *s,
                                   TCGv_i64      dst,
                                   TCGv_i64      src)
 {
-    tcg_gen_mov_i64(dst, src);
+    if (s->pm_enabled == 0) {
+        /* Load unmodified address */
+        tcg_gen_mov_i64(dst, src);
+    } else {
+        tcg_gen_andc_i64(dst, src, s->pm_mask);
+        tcg_gen_or_i64(dst, dst, s->pm_base);
+    }
 }
 
 /*
@@ -814,8 +827,17 @@  static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
     } else {
         ctx->virt_enabled = false;
     }
+    if (riscv_has_ext(env, RVJ)) {
+        ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED);
+        int priv = cpu_mmu_index(env, false);
+        ctx->pm_mask = pm_mask[priv];
+        ctx->pm_base = pm_base[priv];
+    } else {
+        ctx->pm_enabled = 0;
+    }
 #else
     ctx->virt_enabled = false;
+    ctx->pm_enabled = 0;
 #endif
     ctx->misa = env->misa;
     ctx->frm = -1;  /* unknown rounding mode */
@@ -945,4 +967,17 @@  void riscv_translate_init(void)
                              "load_res");
     load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
                              "load_val");
+    /* Assign PM CSRs to tcg globals */
+    pm_mask[PRV_U] = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask),
+                                        "upmmask");
+    pm_base[PRV_U] = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase),
+                                        "upmbase");
+    pm_mask[PRV_S] = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask),
+                                        "spmmask");
+    pm_base[PRV_S] = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase),
+                                        "spmbase");
+    pm_mask[PRV_M] = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask),
+                                        "mpmmask");
+    pm_base[PRV_M] = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase),
+                                        "mpmbase");
 }