diff mbox series

[2/4] microvm: make pcie irq base runtime configurable

Message ID 20201016114328.18835-3-kraxel@redhat.com
State New, archived
Headers show
Series RfC: microvm: add second ioapic | expand

Commit Message

Gerd Hoffmann Oct. 16, 2020, 11:43 a.m. UTC
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
---
 include/hw/i386/microvm.h |  2 +-
 hw/i386/microvm.c         | 11 ++++++-----
 2 files changed, 7 insertions(+), 6 deletions(-)

Comments

Igor Mammedov Oct. 23, 2020, 6:58 p.m. UTC | #1
On Fri, 16 Oct 2020 13:43:26 +0200
Gerd Hoffmann <kraxel@redhat.com> wrote:

> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>

Reviewed-by: Igor Mammedov <imammedo@redhat.com>

> ---
>  include/hw/i386/microvm.h |  2 +-
>  hw/i386/microvm.c         | 11 ++++++-----
>  2 files changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h
> index 0154ad5bd707..ede9625756b8 100644
> --- a/include/hw/i386/microvm.h
> +++ b/include/hw/i386/microvm.h
> @@ -63,7 +63,6 @@
>  #define PCIE_MMIO_SIZE        0x20000000
>  #define PCIE_ECAM_BASE        0xe0000000
>  #define PCIE_ECAM_SIZE        0x10000000
> -#define PCIE_IRQ_BASE         12
>  
>  /* Machine type options */
>  #define MICROVM_MACHINE_PIT                 "pit"
> @@ -93,6 +92,7 @@ struct MicrovmMachineState {
>      bool auto_kernel_cmdline;
>  
>      /* Machine state */
> +    uint32_t pcie_irq_base;
>      uint32_t virtio_irq_base;
>      uint32_t virtio_num_transports;
>      bool kernel_cmdline_fixed;
> diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
> index eaf5da31f7e1..638e95c39e8c 100644
> --- a/hw/i386/microvm.c
> +++ b/hw/i386/microvm.c
> @@ -180,6 +180,7 @@ static void microvm_devices_init(MicrovmMachineState *mms)
>      mms->virtio_irq_base = 5;
>      mms->virtio_num_transports = 8;
>      if (x86_machine_is_acpi_enabled(x86ms)) {
> +        mms->pcie_irq_base = 12;
>          mms->virtio_irq_base = 16;
>      }
>  
> @@ -213,12 +214,12 @@ static void microvm_devices_init(MicrovmMachineState *mms)
>          mms->gpex.mmio32.size = PCIE_MMIO_SIZE;
>          mms->gpex.ecam.base   = PCIE_ECAM_BASE;
>          mms->gpex.ecam.size   = PCIE_ECAM_SIZE;
> -        mms->gpex.irq         = PCIE_IRQ_BASE;
> +        mms->gpex.irq         = mms->pcie_irq_base;
>          create_gpex(mms);
> -        x86ms->pci_irq_mask = ((1 << (PCIE_IRQ_BASE + 0)) |
> -                               (1 << (PCIE_IRQ_BASE + 1)) |
> -                               (1 << (PCIE_IRQ_BASE + 2)) |
> -                               (1 << (PCIE_IRQ_BASE + 3)));
> +        x86ms->pci_irq_mask = ((1 << (mms->pcie_irq_base + 0)) |
> +                               (1 << (mms->pcie_irq_base + 1)) |
> +                               (1 << (mms->pcie_irq_base + 2)) |
> +                               (1 << (mms->pcie_irq_base + 3)));
>      } else {
>          x86ms->pci_irq_mask = 0;
>      }
diff mbox series

Patch

diff --git a/include/hw/i386/microvm.h b/include/hw/i386/microvm.h
index 0154ad5bd707..ede9625756b8 100644
--- a/include/hw/i386/microvm.h
+++ b/include/hw/i386/microvm.h
@@ -63,7 +63,6 @@ 
 #define PCIE_MMIO_SIZE        0x20000000
 #define PCIE_ECAM_BASE        0xe0000000
 #define PCIE_ECAM_SIZE        0x10000000
-#define PCIE_IRQ_BASE         12
 
 /* Machine type options */
 #define MICROVM_MACHINE_PIT                 "pit"
@@ -93,6 +92,7 @@  struct MicrovmMachineState {
     bool auto_kernel_cmdline;
 
     /* Machine state */
+    uint32_t pcie_irq_base;
     uint32_t virtio_irq_base;
     uint32_t virtio_num_transports;
     bool kernel_cmdline_fixed;
diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c
index eaf5da31f7e1..638e95c39e8c 100644
--- a/hw/i386/microvm.c
+++ b/hw/i386/microvm.c
@@ -180,6 +180,7 @@  static void microvm_devices_init(MicrovmMachineState *mms)
     mms->virtio_irq_base = 5;
     mms->virtio_num_transports = 8;
     if (x86_machine_is_acpi_enabled(x86ms)) {
+        mms->pcie_irq_base = 12;
         mms->virtio_irq_base = 16;
     }
 
@@ -213,12 +214,12 @@  static void microvm_devices_init(MicrovmMachineState *mms)
         mms->gpex.mmio32.size = PCIE_MMIO_SIZE;
         mms->gpex.ecam.base   = PCIE_ECAM_BASE;
         mms->gpex.ecam.size   = PCIE_ECAM_SIZE;
-        mms->gpex.irq         = PCIE_IRQ_BASE;
+        mms->gpex.irq         = mms->pcie_irq_base;
         create_gpex(mms);
-        x86ms->pci_irq_mask = ((1 << (PCIE_IRQ_BASE + 0)) |
-                               (1 << (PCIE_IRQ_BASE + 1)) |
-                               (1 << (PCIE_IRQ_BASE + 2)) |
-                               (1 << (PCIE_IRQ_BASE + 3)));
+        x86ms->pci_irq_mask = ((1 << (mms->pcie_irq_base + 0)) |
+                               (1 << (mms->pcie_irq_base + 1)) |
+                               (1 << (mms->pcie_irq_base + 2)) |
+                               (1 << (mms->pcie_irq_base + 3)));
     } else {
         x86ms->pci_irq_mask = 0;
     }