@@ -438,6 +438,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
+ if (cpu->cfg.ext_j) {
+ env->mmte |= PM_EXT_INITIAL;
+ }
if (cpu->cfg.ext_v) {
target_misa |= RVV;
if (!is_power_of_2(cpu->cfg.vlen)) {
@@ -226,6 +226,18 @@ struct CPURISCVState {
/* True if in debugger mode. */
bool debugger;
+
+ /*
+ * CSRs for PM
+ * TODO: move these csr to appropriate groups
+ */
+ target_ulong mmte;
+ target_ulong mpmmask;
+ target_ulong mpmbase;
+ target_ulong spmmask;
+ target_ulong spmbase;
+ target_ulong upmmask;
+ target_ulong upmbase;
#endif
float_status fp_status;
@@ -354,6 +354,21 @@
#define CSR_MHPMCOUNTER30H 0xb9e
#define CSR_MHPMCOUNTER31H 0xb9f
+/* Custom user register */
+#define CSR_UMTE 0x8c0
+#define CSR_UPMMASK 0x8c1
+#define CSR_UPMBASE 0x8c2
+
+/* Custom machine register */
+#define CSR_MMTE 0x7c0
+#define CSR_MPMMASK 0x7c1
+#define CSR_MPMBASE 0x7c2
+
+/* Custom supervisor register */
+#define CSR_SMTE 0x9c0
+#define CSR_SPMMASK 0x9c1
+#define CSR_SPMBASE 0x9c2
+
/* Legacy Machine Protection and Translation (priv v1.9.1) */
#define CSR_MBASE 0x380
#define CSR_MBOUND 0x381
@@ -604,4 +619,55 @@
#define MIE_UTIE (1 << IRQ_U_TIMER)
#define MIE_SSIE (1 << IRQ_S_SOFT)
#define MIE_USIE (1 << IRQ_U_SOFT)
+
+/* general mte CSR bits*/
+#define PM_ENABLE 0x00000001ULL
+#define PM_CURRENT 0x00000002ULL
+#define PM_XS_MASK 0x00000003ULL
+
+/* PM XS bits values */
+#define PM_EXT_DISABLE 0x00000000ULL
+#define PM_EXT_INITIAL 0x00000001ULL
+#define PM_EXT_CLEAN 0x00000002ULL
+#define PM_EXT_DIRTY 0x00000003ULL
+
+/* offsets for every pair of control bits per each priv level */
+#define XS_OFFSET 0ULL
+#define U_OFFSET 2ULL
+#define S_OFFSET 4ULL
+#define M_OFFSET 6ULL
+
+#define PM_XS_BITS (PM_XS_MASK << XS_OFFSET)
+#define U_PM_ENABLE (PM_ENABLE << U_OFFSET)
+#define U_PM_CURRENT (PM_CURRENT << U_OFFSET)
+#define S_PM_ENABLE (PM_ENABLE << S_OFFSET)
+#define S_PM_CURRENT (PM_CURRENT << S_OFFSET)
+#define M_PM_ENABLE (PM_ENABLE << M_OFFSET)
+
+/* mmte CSR bits */
+#define MMTE_PM_XS_BITS PM_XS_BITS
+#define MMTE_U_PM_ENABLE U_PM_ENABLE
+#define MMTE_U_PM_CURRENT U_PM_CURRENT
+#define MMTE_S_PM_ENABLE S_PM_ENABLE
+#define MMTE_S_PM_CURRENT S_PM_CURRENT
+#define MMTE_M_PM_ENABLE M_PM_ENABLE
+#define MMTE_MASK (MMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT | \
+ MMTE_S_PM_ENABLE | MMTE_S_PM_CURRENT | \
+ MMTE_M_PM_ENABLE | MMTE_PM_XS_BITS)
+
+/* smte CSR bits */
+#define SMTE_PM_XS_BITS PM_XS_BITS
+#define SMTE_U_PM_ENABLE U_PM_ENABLE
+#define SMTE_U_PM_CURRENT U_PM_CURRENT
+#define SMTE_S_PM_ENABLE S_PM_ENABLE
+#define SMTE_S_PM_CURRENT S_PM_CURRENT
+#define SMTE_MASK (SMTE_U_PM_ENABLE | SMTE_U_PM_CURRENT | \
+ SMTE_S_PM_ENABLE | SMTE_S_PM_CURRENT | \
+ SMTE_PM_XS_BITS)
+
+/* umte CSR bits */
+#define UMTE_U_PM_ENABLE U_PM_ENABLE
+#define UMTE_U_PM_CURRENT U_PM_CURRENT
+#define UMTE_MASK (UMTE_U_PM_ENABLE | MMTE_U_PM_CURRENT)
+
#endif
@@ -140,6 +140,11 @@ static int any(CPURISCVState *env, int csrno)
return 0;
}
+static int umode(CPURISCVState *env, int csrno)
+{
+ return -!riscv_has_ext(env, RVU);
+}
+
static int smode(CPURISCVState *env, int csrno)
{
return -!riscv_has_ext(env, RVS);
@@ -1250,6 +1255,257 @@ static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
+/*
+ * Functions to access Pointer Masking feature registers
+ * We have to check if current priv lvl could modify
+ * csr in given mode
+ */
+static int check_pm_current_disabled(CPURISCVState *env, int csrno)
+{
+ int csr_priv = get_field(csrno, 0xC00);
+ /*
+ * If priv lvls differ that means we're accessing csr from higher priv lvl,
+ * so allow the access
+ */
+ if (env->priv != csr_priv) {
+ return 0;
+ }
+ int cur_bit_pos;
+ switch (env->priv) {
+ case PRV_M:
+ /* m-mode is always allowed to modify registers, so allow */
+ return 0;
+ case PRV_S:
+ cur_bit_pos = S_PM_CURRENT;
+ break;
+ case PRV_U:
+ cur_bit_pos = U_PM_CURRENT;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ int pm_current = get_field(env->mmte, cur_bit_pos);
+ /* It's same priv lvl, so we allow to modify csr only if pm_current==1 */
+ return !pm_current;
+}
+
+static int read_mmte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ *val = 0;
+ return 0;
+ }
+ *val = env->mmte & MMTE_MASK;
+ return 0;
+}
+
+static int write_mmte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ target_ulong wpri_val = val & MMTE_MASK;
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "MMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ env->mmte = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_smte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ *val = 0;
+ return 0;
+ }
+ *val = env->mmte & SMTE_MASK;
+ return 0;
+}
+
+static int write_smte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ target_ulong wpri_val = val & SMTE_MASK;
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "SMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ target_ulong new_val = val | (env->mmte & ~SMTE_MASK);
+ write_mmte(env, csrno, new_val);
+ return 0;
+}
+
+static int read_umte(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ *val = 0;
+ return 0;
+ }
+ *val = env->mmte & UMTE_MASK;
+ return 0;
+}
+
+static int write_umte(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ target_ulong wpri_val = val & UMTE_MASK;
+ assert(val == wpri_val);
+ if (val != wpri_val) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "UMTE: WPRI violation written 0x%lx vs expected 0x%lx\n",
+ val, wpri_val);
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ target_ulong new_val = val | (env->mmte & ~UMTE_MASK);
+ write_mmte(env, csrno, new_val);
+ return 0;
+}
+
+static int read_mpmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->mpmmask;
+ return 0;
+}
+
+static int write_mpmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ env->mpmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_spmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->spmmask;
+ return 0;
+}
+
+static int write_spmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->spmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_upmmask(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->upmmask;
+ return 0;
+}
+
+static int write_upmmask(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->upmmask = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_mpmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->mpmbase;
+ return 0;
+}
+
+static int write_mpmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ env->mpmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_spmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->spmbase;
+ return 0;
+}
+
+static int write_spmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->spmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
+
+static int read_upmbase(CPURISCVState *env, int csrno, target_ulong *val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ *val = env->upmbase;
+ return 0;
+}
+
+static int write_upmbase(CPURISCVState *env, int csrno, target_ulong val)
+{
+ if (!riscv_has_ext(env, RVJ)) {
+ return -RISCV_EXCP_ILLEGAL_INST;
+ }
+ if (check_pm_current_disabled(env, csrno)) {
+ return 0;
+ }
+ env->upmbase = val;
+ env->mstatus |= MSTATUS_XS | MSTATUS_SD;
+ env->mmte |= PM_EXT_DIRTY;
+ return 0;
+}
#endif
/*
@@ -1471,6 +1727,21 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_PMPCFG0 ... CSR_PMPCFG3] = { pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
+ /* User Pointer Masking */
+ [CSR_UMTE] = { umode, read_umte, write_umte },
+ [CSR_UPMMASK] = { umode, read_upmmask, write_upmmask },
+ [CSR_UPMBASE] = { umode, read_upmbase, write_upmbase },
+
+ /* Machine Pointer Masking */
+ [CSR_MMTE] = { any, read_mmte, write_mmte },
+ [CSR_MPMMASK] = { any, read_mpmmask, write_mpmmask },
+ [CSR_MPMBASE] = { any, read_mpmbase, write_mpmbase },
+
+ /* Supervisor Pointer Masking */
+ [CSR_SMTE] = { smode, read_smte, write_smte },
+ [CSR_SPMMASK] = { smode, read_spmmask, write_spmmask },
+ [CSR_SPMBASE] = { smode, read_spmbase, write_spmbase },
+
/* Performance Counters */
[CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
[CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> --- target/riscv/cpu.c | 3 + target/riscv/cpu.h | 12 ++ target/riscv/cpu_bits.h | 66 ++++++++++ target/riscv/csr.c | 271 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 352 insertions(+)