| Message ID | 20201022080440.10069-2-space.monkey.delivers@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V Pointer Masking implementation | expand |
On Thu, Oct 22, 2020 at 1:05 AM Alexey Baturo <baturo.alexey@gmail.com> wrote: > > Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 2 ++ > 2 files changed, 3 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 0bbfd7f457..4e305249b3 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -516,6 +516,7 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > /* This is experimental so mark with 'x-' */ > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > + DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), This line should be in the last commit. It shouldn't be exposed to users until the very end. Alistair > DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), > DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index de275782e6..eca611a367 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -66,6 +66,7 @@ > #define RVS RV('S') > #define RVU RV('U') > #define RVH RV('H') > +#define RVJ RV('J') > > /* S extension denotes that Supervisor mode exists, however it is possible > to have a core that support S mode but does not have an MMU and there > @@ -277,6 +278,7 @@ struct RISCVCPU { > bool ext_s; > bool ext_u; > bool ext_h; > + bool ext_j; > bool ext_v; > bool ext_counters; > bool ext_ifencei; > -- > 2.20.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f457..4e305249b3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -516,6 +516,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de275782e6..eca611a367 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,6 +66,7 @@ #define RVS RV('S') #define RVU RV('U') #define RVH RV('H') +#define RVJ RV('J') /* S extension denotes that Supervisor mode exists, however it is possible to have a core that support S mode but does not have an MMU and there @@ -277,6 +278,7 @@ struct RISCVCPU { bool ext_s; bool ext_u; bool ext_h; + bool ext_j; bool ext_v; bool ext_counters; bool ext_ifencei;
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 2 ++ 2 files changed, 3 insertions(+)