diff mbox series

[V3,2/6] target/riscv: Add basic vmstate description of CPU

Message ID 20201023091225.224-3-jiangyifei@huawei.com (mailing list archive)
State New, archived
Headers show
Series Support RISC-V migration | expand

Commit Message

Yifei Jiang Oct. 23, 2020, 9:12 a.m. UTC 
Add basic CPU state description to the newly created machine.c

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
 target/riscv/cpu.c       |  8 +----
 target/riscv/internals.h |  4 +++
 target/riscv/machine.c   | 74 ++++++++++++++++++++++++++++++++++++++++
 target/riscv/meson.build |  3 +-
 4 files changed, 81 insertions(+), 8 deletions(-)
 create mode 100644 target/riscv/machine.c

Comments

Alistair Francis Oct. 23, 2020, 11:52 p.m. UTC | #1 
On Fri, Oct 23, 2020 at 2:13 AM Yifei Jiang <jiangyifei@huawei.com> wrote:
>
> Add basic CPU state description to the newly created machine.c
>
> Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c       |  8 +----
>  target/riscv/internals.h |  4 +++
>  target/riscv/machine.c   | 74 ++++++++++++++++++++++++++++++++++++++++
>  target/riscv/meson.build |  3 +-
>  4 files changed, 81 insertions(+), 8 deletions(-)
>  create mode 100644 target/riscv/machine.c
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index dd05a220c7..6a0264fc6b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -22,6 +22,7 @@
>  #include "qemu/ctype.h"
>  #include "qemu/log.h"
>  #include "cpu.h"
> +#include "internals.h"
>  #include "exec/exec-all.h"
>  #include "qapi/error.h"
>  #include "qemu/error-report.h"
> @@ -498,13 +499,6 @@ static void riscv_cpu_init(Object *obj)
>      cpu_set_cpustate_pointers(cpu);
>  }
>
> -#ifndef CONFIG_USER_ONLY
> -static const VMStateDescription vmstate_riscv_cpu = {
> -    .name = "cpu",
> -    .unmigratable = 1,
> -};
> -#endif
> -
>  static Property riscv_cpu_properties[] = {
>      DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
>      DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
> diff --git a/target/riscv/internals.h b/target/riscv/internals.h
> index f1a546dba6..b15ad394bb 100644
> --- a/target/riscv/internals.h
> +++ b/target/riscv/internals.h
> @@ -38,6 +38,10 @@ target_ulong fclass_d(uint64_t frs1);
>  #define SEW32 2
>  #define SEW64 3
>
> +#ifndef CONFIG_USER_ONLY
> +extern const VMStateDescription vmstate_riscv_cpu;
> +#endif
> +
>  static inline uint64_t nanbox_s(float32 f)
>  {
>      return f | MAKE_64BIT_MASK(32, 32);
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> new file mode 100644
> index 0000000000..32edbcba7c
> --- /dev/null
> +++ b/target/riscv/machine.c
> @@ -0,0 +1,74 @@
> +/*
> + * RISC-V VMState Description
> + *
> + * Copyright (c) 2020 Huawei Technologies Co., Ltd
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program.  If not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "cpu.h"
> +#include "qemu/error-report.h"
> +#include "sysemu/kvm.h"
> +#include "migration/cpu.h"
> +
> +const VMStateDescription vmstate_riscv_cpu = {
> +    .name = "cpu",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> +        VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
> +        VMSTATE_UINTTL(env.pc, RISCVCPU),
> +        VMSTATE_UINTTL(env.load_res, RISCVCPU),
> +        VMSTATE_UINTTL(env.load_val, RISCVCPU),
> +        VMSTATE_UINTTL(env.frm, RISCVCPU),
> +        VMSTATE_UINTTL(env.badaddr, RISCVCPU),
> +        VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
> +        VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
> +        VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
> +        VMSTATE_UINTTL(env.misa, RISCVCPU),
> +        VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
> +        VMSTATE_UINT32(env.features, RISCVCPU),
> +        VMSTATE_UINTTL(env.priv, RISCVCPU),
> +        VMSTATE_UINTTL(env.virt, RISCVCPU),
> +        VMSTATE_UINTTL(env.resetvec, RISCVCPU),
> +        VMSTATE_UINTTL(env.mhartid, RISCVCPU),
> +        VMSTATE_UINT64(env.mstatus, RISCVCPU),
> +        VMSTATE_UINTTL(env.mip, RISCVCPU),
> +        VMSTATE_UINT32(env.miclaim, RISCVCPU),
> +        VMSTATE_UINTTL(env.mie, RISCVCPU),
> +        VMSTATE_UINTTL(env.mideleg, RISCVCPU),
> +        VMSTATE_UINTTL(env.sptbr, RISCVCPU),
> +        VMSTATE_UINTTL(env.satp, RISCVCPU),
> +        VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
> +        VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
> +        VMSTATE_UINTTL(env.medeleg, RISCVCPU),
> +        VMSTATE_UINTTL(env.stvec, RISCVCPU),
> +        VMSTATE_UINTTL(env.sepc, RISCVCPU),
> +        VMSTATE_UINTTL(env.scause, RISCVCPU),
> +        VMSTATE_UINTTL(env.mtvec, RISCVCPU),
> +        VMSTATE_UINTTL(env.mepc, RISCVCPU),
> +        VMSTATE_UINTTL(env.mcause, RISCVCPU),
> +        VMSTATE_UINTTL(env.mtval, RISCVCPU),
> +        VMSTATE_UINTTL(env.scounteren, RISCVCPU),
> +        VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
> +        VMSTATE_UINTTL(env.sscratch, RISCVCPU),
> +        VMSTATE_UINTTL(env.mscratch, RISCVCPU),
> +        VMSTATE_UINT64(env.mfromhost, RISCVCPU),
> +        VMSTATE_UINT64(env.mtohost, RISCVCPU),
> +        VMSTATE_UINT64(env.timecmp, RISCVCPU),
> +
> +        VMSTATE_END_OF_LIST()
> +    }
> +};
> diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index abd647fea1..14a5c62dac 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -27,7 +27,8 @@ riscv_ss.add(files(
>  riscv_softmmu_ss = ss.source_set()
>  riscv_softmmu_ss.add(files(
>    'pmp.c',
> -  'monitor.c'
> +  'monitor.c',
> +  'machine.c'
>  ))
>
>  target_arch += {'riscv': riscv_ss}
> --
> 2.19.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index dd05a220c7..6a0264fc6b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -22,6 +22,7 @@ 
 #include "qemu/ctype.h"
 #include "qemu/log.h"
 #include "cpu.h"
+#include "internals.h"
 #include "exec/exec-all.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
@@ -498,13 +499,6 @@  static void riscv_cpu_init(Object *obj)
     cpu_set_cpustate_pointers(cpu);
 }
 
-#ifndef CONFIG_USER_ONLY
-static const VMStateDescription vmstate_riscv_cpu = {
-    .name = "cpu",
-    .unmigratable = 1,
-};
-#endif
-
 static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index f1a546dba6..b15ad394bb 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -38,6 +38,10 @@  target_ulong fclass_d(uint64_t frs1);
 #define SEW32 2
 #define SEW64 3
 
+#ifndef CONFIG_USER_ONLY
+extern const VMStateDescription vmstate_riscv_cpu;
+#endif
+
 static inline uint64_t nanbox_s(float32 f)
 {
     return f | MAKE_64BIT_MASK(32, 32);
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
new file mode 100644
index 0000000000..32edbcba7c
--- /dev/null
+++ b/target/riscv/machine.c
@@ -0,0 +1,74 @@ 
+/*
+ * RISC-V VMState Description
+ *
+ * Copyright (c) 2020 Huawei Technologies Co., Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "qemu/error-report.h"
+#include "sysemu/kvm.h"
+#include "migration/cpu.h"
+
+const VMStateDescription vmstate_riscv_cpu = {
+    .name = "cpu",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
+        VMSTATE_UINT64_ARRAY(env.fpr, RISCVCPU, 32),
+        VMSTATE_UINTTL(env.pc, RISCVCPU),
+        VMSTATE_UINTTL(env.load_res, RISCVCPU),
+        VMSTATE_UINTTL(env.load_val, RISCVCPU),
+        VMSTATE_UINTTL(env.frm, RISCVCPU),
+        VMSTATE_UINTTL(env.badaddr, RISCVCPU),
+        VMSTATE_UINTTL(env.guest_phys_fault_addr, RISCVCPU),
+        VMSTATE_UINTTL(env.priv_ver, RISCVCPU),
+        VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
+        VMSTATE_UINTTL(env.misa, RISCVCPU),
+        VMSTATE_UINTTL(env.misa_mask, RISCVCPU),
+        VMSTATE_UINT32(env.features, RISCVCPU),
+        VMSTATE_UINTTL(env.priv, RISCVCPU),
+        VMSTATE_UINTTL(env.virt, RISCVCPU),
+        VMSTATE_UINTTL(env.resetvec, RISCVCPU),
+        VMSTATE_UINTTL(env.mhartid, RISCVCPU),
+        VMSTATE_UINT64(env.mstatus, RISCVCPU),
+        VMSTATE_UINTTL(env.mip, RISCVCPU),
+        VMSTATE_UINT32(env.miclaim, RISCVCPU),
+        VMSTATE_UINTTL(env.mie, RISCVCPU),
+        VMSTATE_UINTTL(env.mideleg, RISCVCPU),
+        VMSTATE_UINTTL(env.sptbr, RISCVCPU),
+        VMSTATE_UINTTL(env.satp, RISCVCPU),
+        VMSTATE_UINTTL(env.sbadaddr, RISCVCPU),
+        VMSTATE_UINTTL(env.mbadaddr, RISCVCPU),
+        VMSTATE_UINTTL(env.medeleg, RISCVCPU),
+        VMSTATE_UINTTL(env.stvec, RISCVCPU),
+        VMSTATE_UINTTL(env.sepc, RISCVCPU),
+        VMSTATE_UINTTL(env.scause, RISCVCPU),
+        VMSTATE_UINTTL(env.mtvec, RISCVCPU),
+        VMSTATE_UINTTL(env.mepc, RISCVCPU),
+        VMSTATE_UINTTL(env.mcause, RISCVCPU),
+        VMSTATE_UINTTL(env.mtval, RISCVCPU),
+        VMSTATE_UINTTL(env.scounteren, RISCVCPU),
+        VMSTATE_UINTTL(env.mcounteren, RISCVCPU),
+        VMSTATE_UINTTL(env.sscratch, RISCVCPU),
+        VMSTATE_UINTTL(env.mscratch, RISCVCPU),
+        VMSTATE_UINT64(env.mfromhost, RISCVCPU),
+        VMSTATE_UINT64(env.mtohost, RISCVCPU),
+        VMSTATE_UINT64(env.timecmp, RISCVCPU),
+
+        VMSTATE_END_OF_LIST()
+    }
+};
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index abd647fea1..14a5c62dac 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -27,7 +27,8 @@  riscv_ss.add(files(
 riscv_softmmu_ss = ss.source_set()
 riscv_softmmu_ss.add(files(
   'pmp.c',
-  'monitor.c'
+  'monitor.c',
+  'machine.c'
 ))
 
 target_arch += {'riscv': riscv_ss}