From patchwork Fri Oct 23 09:12:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yifei Jiang X-Patchwork-Id: 11852593 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 48CCD92C for ; Fri, 23 Oct 2020 09:17:09 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E5B4224182 for ; Fri, 23 Oct 2020 09:17:08 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E5B4224182 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Received: from localhost ([::1]:51162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kVtC7-0001Gj-PT for patchwork-qemu-devel@patchwork.kernel.org; Fri, 23 Oct 2020 05:17:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54468) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVt8A-0004di-8K; Fri, 23 Oct 2020 05:13:02 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:5206 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVt85-0004kh-RG; Fri, 23 Oct 2020 05:13:01 -0400 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 4246D1897854D9784819; Fri, 23 Oct 2020 17:12:51 +0800 (CST) Received: from huawei.com (10.174.186.209) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.487.0; Fri, 23 Oct 2020 17:12:42 +0800 From: Yifei Jiang To: , Subject: [PATCH V3 3/6] target/riscv: Add PMP state description Date: Fri, 23 Oct 2020 17:12:22 +0800 Message-ID: <20201023091225.224-4-jiangyifei@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201023091225.224-1-jiangyifei@huawei.com> References: <20201023091225.224-1-jiangyifei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.186.209] X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.190; envelope-from=jiangyifei@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/23 05:12:52 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, richard.henderson@linaro.org, Yifei Jiang , Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, wu.wubin@huawei.com, dengkai1@huawei.com Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" In the case of supporting PMP feature, add PMP state description to vmstate_riscv_cpu. 'vmstate_pmp_addr' and 'num_rules' could be regenerated by pmp_update_rule(). But there exists the problem of updating num_rules repeatedly in pmp_update_rule(). So here extracts pmp_update_rule_addr() and pmp_update_rule_nums() to update 'vmstate_pmp_addr' and 'num_rules' respectively. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin Reviewed-by: Alistair Francis --- target/riscv/machine.c | 50 ++++++++++++++++++++++++++++++++++++++++++ target/riscv/pmp.c | 29 ++++++++++++++---------- target/riscv/pmp.h | 2 ++ 3 files changed, 70 insertions(+), 11 deletions(-) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 32edbcba7c..fc1461d88e 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -22,6 +22,52 @@ #include "sysemu/kvm.h" #include "migration/cpu.h" +static bool pmp_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + + return riscv_feature(env, RISCV_FEATURE_PMP); +} + +static int pmp_post_load(void *opaque, int version_id) +{ + RISCVCPU *cpu = opaque; + CPURISCVState *env = &cpu->env; + int i; + + for (i = 0; i < MAX_RISCV_PMPS; i++) { + pmp_update_rule_addr(env, i); + } + pmp_update_rule_nums(env); + + return 0; +} + +static const VMStateDescription vmstate_pmp_entry = { + .name = "cpu/pmp/entry", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(addr_reg, pmp_entry_t), + VMSTATE_UINT8(cfg_reg, pmp_entry_t), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_pmp = { + .name = "cpu/pmp", + .version_id = 1, + .minimum_version_id = 1, + .needed = pmp_needed, + .post_load = pmp_post_load, + .fields = (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(env.pmp_state.pmp, RISCVCPU, MAX_RISCV_PMPS, + 0, vmstate_pmp_entry, pmp_entry_t), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 1, @@ -70,5 +116,9 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINT64(env.timecmp, RISCVCPU), VMSTATE_END_OF_LIST() + }, + .subsections = (const VMStateDescription * []) { + &vmstate_pmp, + NULL } }; diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index c394e867f8..2eda8e1e2f 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -136,18 +136,8 @@ static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea) } } - -/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea' - * end address values. - * This function is called relatively infrequently whereas the check that - * an address is within a pmp rule is called often, so optimise that one - */ -static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) +void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index) { - int i; - - env->pmp_state.num_rules = 0; - uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg; target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg; target_ulong prev_addr = 0u; @@ -186,7 +176,13 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) env->pmp_state.addr[pmp_index].sa = sa; env->pmp_state.addr[pmp_index].ea = ea; +} +void pmp_update_rule_nums(CPURISCVState *env) +{ + int i; + + env->pmp_state.num_rules = 0; for (i = 0; i < MAX_RISCV_PMPS; i++) { const uint8_t a_field = pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); @@ -196,6 +192,17 @@ static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) } } +/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea' + * end address values. + * This function is called relatively infrequently whereas the check that + * an address is within a pmp rule is called often, so optimise that one + */ +static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) +{ + pmp_update_rule_addr(env, pmp_index); + pmp_update_rule_nums(env); +} + static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr) { int result = 0; diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index 6a8f072871..6c6b4c9bef 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -62,5 +62,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, target_ulong size, pmp_priv_t priv, target_ulong mode); bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa, target_ulong *tlb_size); +void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); +void pmp_update_rule_nums(CPURISCVState *env); #endif