diff mbox series

[RFC,v3,13/13] hw/arm/virt-acpi-build: Enable cpu and cache topology

Message ID 20201109030452.2197-14-fangying1@huawei.com (mailing list archive)
State New, archived
Headers show
Series hw/arm/virt: Introduce cpu and cache topology support | expand

Commit Message

fangying Nov. 9, 2020, 3:04 a.m. UTC 
A helper struct AcpiCacheOffset is introduced to describe the offset
of three level caches. The cache hierarchy is built according to
ACPI spec v6.3 5.2.29.2. Let's enable CPU cache topology now.

Signed-off-by: Ying Fang <fangying1@huawei.com>
---
 hw/acpi/aml-build.c         | 19 +++++++++-----
 hw/arm/virt-acpi-build.c    | 52 ++++++++++++++++++++++++++++++++-----
 include/hw/acpi/acpi-defs.h |  6 +++++
 include/hw/acpi/aml-build.h |  7 ++---
 4 files changed, 68 insertions(+), 16 deletions(-)

Comments

Jonathan Cameron Nov. 9, 2020, 5:36 p.m. UTC | #1 
On Mon, 9 Nov 2020 11:04:52 +0800
Ying Fang <fangying1@huawei.com> wrote:

> A helper struct AcpiCacheOffset is introduced to describe the offset
> of three level caches. The cache hierarchy is built according to
> ACPI spec v6.3 5.2.29.2. Let's enable CPU cache topology now.
> 
> Signed-off-by: Ying Fang <fangying1@huawei.com>
> ---
>  hw/acpi/aml-build.c         | 19 +++++++++-----
>  hw/arm/virt-acpi-build.c    | 52 ++++++++++++++++++++++++++++++++-----
>  include/hw/acpi/acpi-defs.h |  6 +++++
>  include/hw/acpi/aml-build.h |  7 ++---
>  4 files changed, 68 insertions(+), 16 deletions(-)
> 
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 1a38110149..93a81fbaf5 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -1799,27 +1799,32 @@ void build_cache_hierarchy(GArray *tbl,
>  /*
>   * ACPI 6.3: 5.2.29.1 Processor hierarchy node structure (Type 0)
>   */
> -void build_socket_hierarchy(GArray *tbl, uint32_t parent, uint32_t id)
> +void build_socket_hierarchy(GArray *tbl, uint32_t parent,
> +                            uint32_t offset, uint32_t id)
>  {
>      build_append_byte(tbl, 0);          /* Type 0 - processor */
> -    build_append_byte(tbl, 20);         /* Length, no private resources */
> +    build_append_byte(tbl, 24);         /* Length, with private resources */
>      build_append_int_noprefix(tbl, 0, 2);  /* Reserved */
>      build_append_int_noprefix(tbl, 1, 4);  /* Flags: Physical package */
>      build_append_int_noprefix(tbl, parent, 4);  /* Parent */
>      build_append_int_noprefix(tbl, id, 4);     /* ACPI processor ID */
> -    build_append_int_noprefix(tbl, 0, 4);  /* Number of private resources */
> +    build_append_int_noprefix(tbl, 1, 4);  /*  Number of private resources */
> +    build_append_int_noprefix(tbl, offset, 4);  /* Private resources */
>  }
>  
> -void build_processor_hierarchy(GArray *tbl, uint32_t flags,
> -                               uint32_t parent, uint32_t id)
> +void build_processor_hierarchy(GArray *tbl, uint32_t flags, uint32_t parent,
> +                               AcpiCacheOffset offset, uint32_t id)
>  {
>      build_append_byte(tbl, 0);          /* Type 0 - processor */
> -    build_append_byte(tbl, 20);         /* Length, no private resources */
> +    build_append_byte(tbl, 32);         /* Length, with private resources */
>      build_append_int_noprefix(tbl, 0, 2);      /* Reserved */
>      build_append_int_noprefix(tbl, flags, 4);  /* Flags */
>      build_append_int_noprefix(tbl, parent, 4); /* Parent */
>      build_append_int_noprefix(tbl, id, 4);     /* ACPI processor ID */
> -    build_append_int_noprefix(tbl, 0, 4);  /* Number of private resources */
> +    build_append_int_noprefix(tbl, 3, 4);  /* Number of private resources */
> +    build_append_int_noprefix(tbl, offset.l1d_offset, 4);/* Private resources */
> +    build_append_int_noprefix(tbl, offset.l1i_offset, 4);/* Private resources */
> +    build_append_int_noprefix(tbl, offset.l2_offset, 4); /* Private resources */

So this is an interesting corner of the ACPI spec.  Do we need to include
the level 2 cache in the private resources or not?

My reading is that it is optional and we have at least one obscure bug in Linux
due to the ambiguity in the spec.  You won't hit that here for reasons found
in that thread though (cache types are different).

https://lore.kernel.org/linux-acpi/20201105174233.1146-2-shiju.jose@huawei.com/

So I suggest we make the only access to the l2 cache be via the l1 nodes
as per the example in ACPI 6.3 Figure 5.13 "Cache Type Structure - Type 1 Example"

i.e. Drop the l2 entry here and reduced the Length to 28.

Thanks,

Jonathan

>  }
>  
>  void build_smt_hierarchy(GArray *tbl, uint32_t parent, uint32_t id)
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 5784370257..ad49006b42 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -429,29 +429,69 @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
>                   "SRAT", table_data->len - srat_start, 3, NULL, NULL);
>  }
>  
> -static void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms)
> +static inline void arm_acpi_cache_info(CPUCacheInfo *cpu_cache,
> +                                       AcpiCacheInfo *acpi_cache)
>  {
> +    acpi_cache->size = cpu_cache->size;
> +    acpi_cache->sets = cpu_cache->sets;
> +    acpi_cache->associativity = cpu_cache->associativity;
> +    acpi_cache->attributes = cpu_cache->attributes;
> +    acpi_cache->line_size = cpu_cache->line_size;
> +}
> +
> +static void build_pptt(GArray *table_data, BIOSLinker *linker,
> +                       VirtMachineState *vms)
> +{
> +    MachineState *ms = MACHINE(vms);
>      int pptt_start = table_data->len;
>      int uid = 0, cpus = 0, socket;
>      unsigned int smp_cores = ms->smp.cores;
>      unsigned int smp_threads = ms->smp.threads;
> +    AcpiCacheOffset offset;
> +    ARMCPU *cpu = ARM_CPU(qemu_get_cpu(cpus));
> +    AcpiCacheInfo cache_info;
>  
>      acpi_data_push(table_data, sizeof(AcpiTableHeader));
>  
>      for (socket = 0; cpus < ms->possible_cpus->len; socket++) {
> -        uint32_t socket_offset = table_data->len - pptt_start;
> +        uint32_t l3_offset = table_data->len - pptt_start;
> +        uint32_t socket_offset;
>          int core;
>  
> -        build_socket_hierarchy(table_data, 0, socket);
> +        /* L3 cache type structure */
> +        arm_acpi_cache_info(cpu->caches.l3_cache, &cache_info);
> +        build_cache_hierarchy(table_data, 0, &cache_info);
> +
> +        socket_offset = table_data->len - pptt_start;
> +        build_socket_hierarchy(table_data, 0, l3_offset, socket);
>  
>          for (core = 0; core < smp_cores; core++) {
>              uint32_t core_offset = table_data->len - pptt_start;
>              int thread;
>  
> +            /* L2 cache tpe structure */
> +            offset.l2_offset = table_data->len - pptt_start;
> +            arm_acpi_cache_info(cpu->caches.l2_cache, &cache_info);
> +            build_cache_hierarchy(table_data, 0, &cache_info);
> +
> +            /* L1d cache type structure */
> +            offset.l1d_offset = table_data->len - pptt_start;
> +            arm_acpi_cache_info(cpu->caches.l1d_cache, &cache_info);
> +            build_cache_hierarchy(table_data, offset.l2_offset, &cache_info);
> +
> +            /* L1i cache type structure */
> +            offset.l1i_offset = table_data->len - pptt_start;
> +            arm_acpi_cache_info(cpu->caches.l1i_cache, &cache_info);
> +            build_cache_hierarchy(table_data, offset.l2_offset, &cache_info);
> +
> +            core_offset = table_data->len - pptt_start;
>              if (smp_threads <= 1) {
> -                build_processor_hierarchy(table_data, 2, socket_offset, uid++);
> +                build_processor_hierarchy(table_data, 2, socket_offset,
> +                                          offset, uid++);
>               } else {
> -                build_processor_hierarchy(table_data, 0, socket_offset, core);
> +
> +                build_processor_hierarchy(table_data, 0, socket_offset,
> +                                          offset, core);
>                  for (thread = 0; thread < smp_threads; thread++) {
>                      build_smt_hierarchy(table_data, core_offset, uid++);
>                  }
> @@ -727,7 +767,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
>  
>      if (cpu_topology_enabled) {
>          acpi_add_table(table_offsets, tables_blob);
> -        build_pptt(tables_blob, tables->linker, ms);
> +        build_pptt(tables_blob, tables->linker, vms);
>      }
>  
>      acpi_add_table(table_offsets, tables_blob);
> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
> index 3df38ab449..e48b7fa506 100644
> --- a/include/hw/acpi/acpi-defs.h
> +++ b/include/hw/acpi/acpi-defs.h
> @@ -626,4 +626,10 @@ typedef struct AcpiCacheInfo {
>      uint16_t line_size;
>  } AcpiCacheInfo;
>  
> +typedef struct AcpiCacheOffset {
> +    uint32_t l1d_offset;
> +    uint32_t l1i_offset;
> +    uint32_t l2_offset;
> +} AcpiCacheOffset;
> +
>  #endif
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index 01078753a8..a15ccb2c91 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -440,10 +440,11 @@ void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms);
>  void build_cache_hierarchy(GArray *tbl,
>                uint32_t next_level, AcpiCacheInfo *cache_info);
>  
> -void build_socket_hierarchy(GArray *tbl, uint32_t parent, uint32_t id);
> +void build_socket_hierarchy(GArray *tbl, uint32_t parent,
> +                            uint32_t offset, uint32_t id);
>  
> -void build_processor_hierarchy(GArray *tbl, uint32_t flags,
> -                               uint32_t parent, uint32_t id);
> +void build_processor_hierarchy(GArray *tbl, uint32_t flags, uint32_t parent,
> +                               AcpiCacheOffset offset, uint32_t id);
>  
>  void build_smt_hierarchy(GArray *tbl, uint32_t parent, uint32_t id);
>
diff mbox series

Patch

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 1a38110149..93a81fbaf5 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -1799,27 +1799,32 @@  void build_cache_hierarchy(GArray *tbl,
 /*
  * ACPI 6.3: 5.2.29.1 Processor hierarchy node structure (Type 0)
  */
-void build_socket_hierarchy(GArray *tbl, uint32_t parent, uint32_t id)
+void build_socket_hierarchy(GArray *tbl, uint32_t parent,
+                            uint32_t offset, uint32_t id)
 {
     build_append_byte(tbl, 0);          /* Type 0 - processor */
-    build_append_byte(tbl, 20);         /* Length, no private resources */
+    build_append_byte(tbl, 24);         /* Length, with private resources */
     build_append_int_noprefix(tbl, 0, 2);  /* Reserved */
     build_append_int_noprefix(tbl, 1, 4);  /* Flags: Physical package */
     build_append_int_noprefix(tbl, parent, 4);  /* Parent */
     build_append_int_noprefix(tbl, id, 4);     /* ACPI processor ID */
-    build_append_int_noprefix(tbl, 0, 4);  /* Number of private resources */
+    build_append_int_noprefix(tbl, 1, 4);  /*  Number of private resources */
+    build_append_int_noprefix(tbl, offset, 4);  /* Private resources */
 }
 
-void build_processor_hierarchy(GArray *tbl, uint32_t flags,
-                               uint32_t parent, uint32_t id)
+void build_processor_hierarchy(GArray *tbl, uint32_t flags, uint32_t parent,
+                               AcpiCacheOffset offset, uint32_t id)
 {
     build_append_byte(tbl, 0);          /* Type 0 - processor */
-    build_append_byte(tbl, 20);         /* Length, no private resources */
+    build_append_byte(tbl, 32);         /* Length, with private resources */
     build_append_int_noprefix(tbl, 0, 2);      /* Reserved */
     build_append_int_noprefix(tbl, flags, 4);  /* Flags */
     build_append_int_noprefix(tbl, parent, 4); /* Parent */
     build_append_int_noprefix(tbl, id, 4);     /* ACPI processor ID */
-    build_append_int_noprefix(tbl, 0, 4);  /* Number of private resources */
+    build_append_int_noprefix(tbl, 3, 4);  /* Number of private resources */
+    build_append_int_noprefix(tbl, offset.l1d_offset, 4);/* Private resources */
+    build_append_int_noprefix(tbl, offset.l1i_offset, 4);/* Private resources */
+    build_append_int_noprefix(tbl, offset.l2_offset, 4); /* Private resources */
 }
 
 void build_smt_hierarchy(GArray *tbl, uint32_t parent, uint32_t id)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 5784370257..ad49006b42 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -429,29 +429,69 @@  build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
                  "SRAT", table_data->len - srat_start, 3, NULL, NULL);
 }
 
-static void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms)
+static inline void arm_acpi_cache_info(CPUCacheInfo *cpu_cache,
+                                       AcpiCacheInfo *acpi_cache)
 {
+    acpi_cache->size = cpu_cache->size;
+    acpi_cache->sets = cpu_cache->sets;
+    acpi_cache->associativity = cpu_cache->associativity;
+    acpi_cache->attributes = cpu_cache->attributes;
+    acpi_cache->line_size = cpu_cache->line_size;
+}
+
+static void build_pptt(GArray *table_data, BIOSLinker *linker,
+                       VirtMachineState *vms)
+{
+    MachineState *ms = MACHINE(vms);
     int pptt_start = table_data->len;
     int uid = 0, cpus = 0, socket;
     unsigned int smp_cores = ms->smp.cores;
     unsigned int smp_threads = ms->smp.threads;
+    AcpiCacheOffset offset;
+    ARMCPU *cpu = ARM_CPU(qemu_get_cpu(cpus));
+    AcpiCacheInfo cache_info;
 
     acpi_data_push(table_data, sizeof(AcpiTableHeader));
 
     for (socket = 0; cpus < ms->possible_cpus->len; socket++) {
-        uint32_t socket_offset = table_data->len - pptt_start;
+        uint32_t l3_offset = table_data->len - pptt_start;
+        uint32_t socket_offset;
         int core;
 
-        build_socket_hierarchy(table_data, 0, socket);
+        /* L3 cache type structure */
+        arm_acpi_cache_info(cpu->caches.l3_cache, &cache_info);
+        build_cache_hierarchy(table_data, 0, &cache_info);
+
+        socket_offset = table_data->len - pptt_start;
+        build_socket_hierarchy(table_data, 0, l3_offset, socket);
 
         for (core = 0; core < smp_cores; core++) {
             uint32_t core_offset = table_data->len - pptt_start;
             int thread;
 
+            /* L2 cache tpe structure */
+            offset.l2_offset = table_data->len - pptt_start;
+            arm_acpi_cache_info(cpu->caches.l2_cache, &cache_info);
+            build_cache_hierarchy(table_data, 0, &cache_info);
+
+            /* L1d cache type structure */
+            offset.l1d_offset = table_data->len - pptt_start;
+            arm_acpi_cache_info(cpu->caches.l1d_cache, &cache_info);
+            build_cache_hierarchy(table_data, offset.l2_offset, &cache_info);
+
+            /* L1i cache type structure */
+            offset.l1i_offset = table_data->len - pptt_start;
+            arm_acpi_cache_info(cpu->caches.l1i_cache, &cache_info);
+            build_cache_hierarchy(table_data, offset.l2_offset, &cache_info);
+
+            core_offset = table_data->len - pptt_start;
             if (smp_threads <= 1) {
-                build_processor_hierarchy(table_data, 2, socket_offset, uid++);
+                build_processor_hierarchy(table_data, 2, socket_offset,
+                                          offset, uid++);
              } else {
-                build_processor_hierarchy(table_data, 0, socket_offset, core);
+
+                build_processor_hierarchy(table_data, 0, socket_offset,
+                                          offset, core);
                 for (thread = 0; thread < smp_threads; thread++) {
                     build_smt_hierarchy(table_data, core_offset, uid++);
                 }
@@ -727,7 +767,7 @@  void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
 
     if (cpu_topology_enabled) {
         acpi_add_table(table_offsets, tables_blob);
-        build_pptt(tables_blob, tables->linker, ms);
+        build_pptt(tables_blob, tables->linker, vms);
     }
 
     acpi_add_table(table_offsets, tables_blob);
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index 3df38ab449..e48b7fa506 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -626,4 +626,10 @@  typedef struct AcpiCacheInfo {
     uint16_t line_size;
 } AcpiCacheInfo;
 
+typedef struct AcpiCacheOffset {
+    uint32_t l1d_offset;
+    uint32_t l1i_offset;
+    uint32_t l2_offset;
+} AcpiCacheOffset;
+
 #endif
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 01078753a8..a15ccb2c91 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -440,10 +440,11 @@  void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms);
 void build_cache_hierarchy(GArray *tbl,
               uint32_t next_level, AcpiCacheInfo *cache_info);
 
-void build_socket_hierarchy(GArray *tbl, uint32_t parent, uint32_t id);
+void build_socket_hierarchy(GArray *tbl, uint32_t parent,
+                            uint32_t offset, uint32_t id);
 
-void build_processor_hierarchy(GArray *tbl, uint32_t flags,
-                               uint32_t parent, uint32_t id);
+void build_processor_hierarchy(GArray *tbl, uint32_t flags, uint32_t parent,
+                               AcpiCacheOffset offset, uint32_t id);
 
 void build_smt_hierarchy(GArray *tbl, uint32_t parent, uint32_t id);