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09 Nov 2020 19:55:02 -0800 IronPort-SDR: rO0XqHEz9/pkAUhchlyGz1p8E7DH31COg352P1T+ncWxJX3/xP+cAH0Dn+C/nfgaA5XGe6ITnc DGLGab/O7s7IOfEgotMJ6WtdOn8G8whkujkfXoIMZwGqtPzTwaJ76cdJz50ewvSuxUDiGSIs6F JOjqEdbGis05xAsH9B9Z5y+EeXJeWlu0wiWFqflW/sfUxFGYAwl0US6Wm41eouv2sTkS546mfj yJdb8DyKQX68gJhAE6gSCplrv4lPIvcHkXqFfUImyolJyoY5Vd1r3fNDBY5EF3CysU95MJaXlq tQo= WDCIronportException: Internal Received: from usa001882.ad.shared (HELO risc6-mainframe.hgst.com) ([10.86.60.209]) by uls-op-cesaip01.wdc.com with ESMTP; 09 Nov 2020 20:09:00 -0800 From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org Subject: [PULL 6/6] hw/intc/ibex_plic: Clear the claim register when read Date: Mon, 9 Nov 2020 19:57:03 -0800 Message-Id: <20201110035703.83786-7-alistair.francis@wdc.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201110035703.83786-1-alistair.francis@wdc.com> References: <20201110035703.83786-1-alistair.francis@wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=57671029a=alistair.francis@wdc.com; helo=esa2.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/11/09 23:09:00 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" After claiming the interrupt by reading the claim register we want to clear the register to make sure the interrupt doesn't appear at the next read. This matches the documentation for the claim register as when an interrupt is claimed by a target the relevant bit of IP is cleared (which we already do): https://docs.opentitan.org/hw/ip/rv_plic/doc/index.html This also matches the current hardware. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-id: 68d4575deef2559b7a747f3bda193fcf43af4558.1604629928.git.alistair.francis@wdc.com --- hw/intc/ibex_plic.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c index f49fa67c91..235e6b88ff 100644 --- a/hw/intc/ibex_plic.c +++ b/hw/intc/ibex_plic.c @@ -139,6 +139,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr, /* Return the current claimed interrupt */ ret = s->claim; + /* Clear the claimed interrupt */ + s->claim = 0x00000000; + /* Update the interrupt status after the claim */ ibex_plic_update(s); }