| Message ID | 20201111094725.3768755-1-anup.patel@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/riscv: sifive_u: Add UART1 DT node in the generated DTB | expand |
On Wed, Nov 11, 2020 at 1:48 AM Anup Patel <anup.patel@wdc.com> wrote: > > The sifive_u machine emulates two UARTs but we have only UART0 DT > node in the generated DTB so this patch adds UART1 DT node in the > generated DTB. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/sifive_u.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 2f19a9cda2..146944a293 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -387,6 +387,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); > g_free(nodename); > > + nodename = g_strdup_printf("/soc/serial@%lx", > + (long)memmap[SIFIVE_U_DEV_UART1].base); > + qemu_fdt_add_subnode(fdt, nodename); > + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); > + qemu_fdt_setprop_cells(fdt, nodename, "reg", > + 0x0, memmap[SIFIVE_U_DEV_UART1].base, > + 0x0, memmap[SIFIVE_U_DEV_UART1].size); > + qemu_fdt_setprop_cells(fdt, nodename, "clocks", > + prci_phandle, PRCI_CLK_TLCLK); > + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); > + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); > + > + qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); > + g_free(nodename); > + > nodename = g_strdup_printf("/soc/serial@%lx", > (long)memmap[SIFIVE_U_DEV_UART0].base); > qemu_fdt_add_subnode(fdt, nodename); > -- > 2.25.1 > >
On Wed, Nov 11, 2020 at 1:48 AM Anup Patel <anup.patel@wdc.com> wrote: > > The sifive_u machine emulates two UARTs but we have only UART0 DT > node in the generated DTB so this patch adds UART1 DT node in the > generated DTB. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > hw/riscv/sifive_u.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 2f19a9cda2..146944a293 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -387,6 +387,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, > qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); > g_free(nodename); > > + nodename = g_strdup_printf("/soc/serial@%lx", > + (long)memmap[SIFIVE_U_DEV_UART1].base); > + qemu_fdt_add_subnode(fdt, nodename); > + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); > + qemu_fdt_setprop_cells(fdt, nodename, "reg", > + 0x0, memmap[SIFIVE_U_DEV_UART1].base, > + 0x0, memmap[SIFIVE_U_DEV_UART1].size); > + qemu_fdt_setprop_cells(fdt, nodename, "clocks", > + prci_phandle, PRCI_CLK_TLCLK); > + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); > + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); > + > + qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); > + g_free(nodename); > + > nodename = g_strdup_printf("/soc/serial@%lx", > (long)memmap[SIFIVE_U_DEV_UART0].base); > qemu_fdt_add_subnode(fdt, nodename); > -- > 2.25.1 > >
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 2f19a9cda2..146944a293 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -387,6 +387,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); g_free(nodename); + nodename = g_strdup_printf("/soc/serial@%lx", + (long)memmap[SIFIVE_U_DEV_UART1].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_DEV_UART1].base, + 0x0, memmap[SIFIVE_U_DEV_UART1].size); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ); + + qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename); + g_free(nodename); + nodename = g_strdup_printf("/soc/serial@%lx", (long)memmap[SIFIVE_U_DEV_UART0].base); qemu_fdt_add_subnode(fdt, nodename);
The sifive_u machine emulates two UARTs but we have only UART0 DT node in the generated DTB so this patch adds UART1 DT node in the generated DTB. Signed-off-by: Anup Patel <anup.patel@wdc.com> --- hw/riscv/sifive_u.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)