| Message ID | 20201116160831.31000-12-peter.maydell@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: More v8.1M features | expand |
On 11/16/20 8:08 AM, Peter Maydell wrote: > We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR > in the previous commit; use it in a couple of places in existing code, > where we're masking out everything except NZCV for the "load to Rt=15 > sets CPSR.NZCV" special case. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/translate-vfp.c.inc | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 84e806004e4..1ccaccbc834 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -743,7 +743,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, * helper call for the "VMRS to CPSR.NZCV" insn. */ tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); - tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); storefn(s, opaque, tmp); break; default: @@ -884,7 +884,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) case ARM_VFP_FPSCR: if (a->rt == 15) { tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); - tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); } else { tmp = tcg_temp_new_i32(); gen_helper_vfp_get_fpscr(tmp, cpu_env);
We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR in the previous commit; use it in a couple of places in existing code, where we're masking out everything except NZCV for the "load to Rt=15 sets CPSR.NZCV" special case. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/translate-vfp.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)