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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm1934851wrm.62.2020.11.19.13.56.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Nov 2020 13:56:25 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 05/28] target/arm: Implement CLRM instruction Date: Thu, 19 Nov 2020 21:55:54 +0000 Message-Id: <20201119215617.29887-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201119215617.29887-1-peter.maydell@linaro.org> References: <20201119215617.29887-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" In v8.1M the new CLRM instruction allows zeroing an arbitrary set of the general-purpose registers and APSR. Implement this. The encoding is a subset of the LDMIA T2 encoding, using what would be Rn=0b1111 (which UNDEFs for LDMIA). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/t32.decode | 6 +++++- target/arm/translate.c | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 1 deletion(-) diff --git a/target/arm/t32.decode b/target/arm/t32.decode index cfcc71bfb0a..f045eb62c84 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -609,7 +609,11 @@ UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot STM_t32 1110 1000 10.0 .... ................ @ldstm i=1 b=0 STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1 -LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0 +{ + # Rn=15 UNDEFs for LDM; M-profile CLRM uses that encoding + CLRM 1110 1000 1001 1111 list:16 + LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0 +} LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1 &rfe !extern rn w pu diff --git a/target/arm/translate.c b/target/arm/translate.c index 9f2b6018a21..47a1a5739c8 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7968,6 +7968,44 @@ static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a) return do_ldm(s, a, 1); } +static bool trans_CLRM(DisasContext *s, arg_CLRM *a) +{ + int i; + TCGv_i32 zero; + + if (!dc_isar_feature(aa32_m_sec_state, s)) { + return false; + } + + if (extract32(a->list, 13, 1)) { + return false; + } + + if (!a->list) { + /* UNPREDICTABLE; we choose to UNDEF */ + return false; + } + + zero = tcg_const_i32(0); + for (i = 0; i < 15; i++) { + if (extract32(a->list, i, 1)) { + /* Clear R[i] */ + tcg_gen_mov_i32(cpu_R[i], zero); + } + } + if (extract32(a->list, 15, 1)) { + /* + * Clear APSR (by calling the MSR helper with the same argument + * as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0) + */ + TCGv_i32 maskreg = tcg_const_i32(0xc << 8); + gen_helper_v7m_msr(cpu_env, maskreg, zero); + tcg_temp_free_i32(maskreg); + } + tcg_temp_free_i32(zero); + return true; +} + /* * Branch, branch with link */