@@ -773,6 +773,24 @@ typedef struct QEMU_PACKED NvmeSmartLog {
uint8_t reserved2[320];
} NvmeSmartLog;
+typedef struct NvmeEffectsLog {
+ uint32_t acs[256];
+ uint32_t iocs[256];
+ uint8_t rsvd2048[2048];
+} NvmeEffectsLog;
+
+enum {
+ NVME_EFFECTS_CSUPP = 1 << 0,
+ NVME_EFFECTS_LBCC = 1 << 1,
+ NVME_EFFECTS_NCC = 1 << 2,
+ NVME_EFFECTS_NIC = 1 << 3,
+ NVME_EFFECTS_CCC = 1 << 4,
+ NVME_EFFECTS_CSE_SINGLE = 1 << 16,
+ NVME_EFFECTS_CSE_MULTI = 1 << 17,
+ NVME_EFFECTS_CSE_MASK = 3 << 16,
+ NVME_EFFECTS_UUID_SEL = 1 << 19,
+};
+
enum NvmeSmartWarn {
NVME_SMART_SPARE = 1 << 0,
NVME_SMART_TEMPERATURE = 1 << 1,
@@ -785,6 +803,7 @@ enum NvmeLogIdentifier {
NVME_LOG_ERROR_INFO = 0x01,
NVME_LOG_SMART_INFO = 0x02,
NVME_LOG_FW_SLOT_INFO = 0x03,
+ NVME_LOG_EFFECTS = 0x05,
};
typedef struct QEMU_PACKED NvmePSD {
@@ -901,8 +920,9 @@ enum NvmeIdCtrlFrmw {
};
enum NvmeIdCtrlLpa {
- NVME_LPA_NS_SMART = 1 << 0,
- NVME_LPA_EXTENDED = 1 << 2,
+ NVME_LPA_NS_SMART = 1 << 0,
+ NVME_LPA_EFFECTS_LOG = 1 << 1,
+ NVME_LPA_EXTENDED = 1 << 2,
};
#define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf)
@@ -1119,5 +1139,6 @@ static inline void _nvme_check_size(void)
QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096);
QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) != 16);
QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) != 4);
+ QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) != 4096);
}
#endif
@@ -1782,6 +1782,63 @@ static uint16_t nvme_error_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
DMA_DIRECTION_FROM_DEVICE, req);
}
+static void nvme_effects_nvm(NvmeEffectsLog *effects)
+{
+ effects->iocs[NVME_CMD_FLUSH] = NVME_EFFECTS_CSUPP | NVME_EFFECTS_LBCC;
+ effects->iocs[NVME_CMD_WRITE] = NVME_EFFECTS_CSUPP | NVME_EFFECTS_LBCC;
+ effects->iocs[NVME_CMD_READ] = NVME_EFFECTS_CSUPP;
+ effects->iocs[NVME_CMD_COMPARE] = NVME_EFFECTS_CSUPP;
+ effects->iocs[NVME_CMD_WRITE_ZEROES] = NVME_EFFECTS_CSUPP |
+ NVME_EFFECTS_LBCC;
+ effects->iocs[NVME_CMD_DSM] = NVME_EFFECTS_CSUPP | NVME_EFFECTS_LBCC;
+ effects->iocs[NVME_CMD_COPY] = NVME_EFFECTS_CSUPP | NVME_EFFECTS_LBCC;
+}
+
+static uint16_t nvme_effects_log(NvmeCtrl *n, uint32_t buf_len, uint64_t off,
+ NvmeRequest *req)
+{
+ NvmeEffectsLog effects = (NvmeEffectsLog) {
+ .acs = {
+ [NVME_ADM_CMD_DELETE_SQ] = NVME_EFFECTS_CSUPP,
+ [NVME_ADM_CMD_CREATE_SQ] = NVME_EFFECTS_CSUPP,
+ [NVME_ADM_CMD_GET_LOG_PAGE] = NVME_EFFECTS_CSUPP,
+ [NVME_ADM_CMD_DELETE_CQ] = NVME_EFFECTS_CSUPP,
+ [NVME_ADM_CMD_CREATE_CQ] = NVME_EFFECTS_CSUPP,
+ [NVME_ADM_CMD_IDENTIFY] = NVME_EFFECTS_CSUPP,
+ [NVME_ADM_CMD_ABORT] = NVME_EFFECTS_CSUPP,
+ [NVME_ADM_CMD_SET_FEATURES] = NVME_EFFECTS_CSUPP |
+ NVME_EFFECTS_CCC |
+ NVME_EFFECTS_NIC |
+ NVME_EFFECTS_NCC,
+ [NVME_ADM_CMD_GET_FEATURES] = NVME_EFFECTS_CSUPP,
+ [NVME_ADM_CMD_ASYNC_EV_REQ] = NVME_EFFECTS_CSUPP
+ },
+ };
+
+ uint32_t trans_len;
+
+ if (off >= sizeof(NvmeEffectsLog)) {
+ return NVME_INVALID_FIELD | NVME_DNR;
+ }
+
+ switch (NVME_CC_CSS(n->bar.cc)) {
+ case NVME_CC_CSS_ADMIN_ONLY:
+ break;
+
+ case NVME_CC_CSS_NVM:
+ nvme_effects_nvm(&effects);
+ break;
+
+ default:
+ return NVME_INTERNAL_DEV_ERROR | NVME_DNR;
+ }
+
+ trans_len = MIN(sizeof(effects) - off, buf_len);
+
+ return nvme_dma(n, (uint8_t *)&effects + off, trans_len,
+ DMA_DIRECTION_FROM_DEVICE, req);
+}
+
static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req)
{
NvmeCmd *cmd = &req->cmd;
@@ -1825,6 +1882,8 @@ static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req)
return nvme_smart_info(n, rae, len, off, req);
case NVME_LOG_FW_SLOT_INFO:
return nvme_fw_log_info(n, len, off, req);
+ case NVME_LOG_EFFECTS:
+ return nvme_effects_log(n, len, off, req);
default:
trace_pci_nvme_err_invalid_log_page(nvme_cid(req), lid);
return NVME_INVALID_FIELD | NVME_DNR;
@@ -3286,7 +3345,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
id->acl = 3;
id->aerl = n->params.aerl;
id->frmw = (NVME_NUM_FW_SLOTS << 1) | NVME_FRMW_SLOT1_RO;
- id->lpa = NVME_LPA_NS_SMART | NVME_LPA_EXTENDED;
+ id->lpa = NVME_LPA_NS_SMART | NVME_LPA_EXTENDED | NVME_LPA_EFFECTS_LOG;
/* recommended default value (~70 C) */
id->wctemp = cpu_to_le16(NVME_TEMPERATURE_WARNING);